Add driver for the StarFive JHB100 Peripheral-0 clock controller.
Signed-off-by: Changhuang Liang <[email protected]>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-per0.c | 603 ++++++++++++++++++
3 files changed, 612 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per0.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 729bdfce7b8a..adf97444f460 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -73,6 +73,14 @@ config CLK_STARFIVE_JH7110_VOUT
Say yes here to support the Video-Output clock controller
on the StarFive JH7110 SoC.
+config CLK_STARFIVE_JHB100_PER0
+ bool "StarFive JHB100 peripheral-0 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS2
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the peripheral-0 clock controller
+ on the StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 90b6390296bd..2f605d0fd6da 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) +=
clk-starfive-jh7110-stg.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per0.c
b/drivers/clk/starfive/clk-starfive-jhb100-per0.c
new file mode 100644
index 000000000000..bcfde1afe137
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-per0.c
@@ -0,0 +1,603 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 Peripheral-0 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <[email protected]>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-common.h"
+
+#define JHB100_PER0CLK_NUM_CLKS
(JHB100_PER0CLK_MAIN_ICG_EN_TRNG + 1)
+
+/* external clocks */
+#define JHB100_PER0CLK_OSC (JHB100_PER0CLK_NUM_CLKS + 0)
+#define JHB100_PER0CLK_PLL6 (JHB100_PER0CLK_NUM_CLKS + 1)
+#define JHB100_PER0CLK_CFG_400 (JHB100_PER0CLK_NUM_CLKS + 2)
+#define JHB100_PER0CLK_CFG_800 (JHB100_PER0CLK_NUM_CLKS + 3)
+#define JHB100_PER0CLK_NCNOC_INIT (JHB100_PER0CLK_NUM_CLKS + 4)
+#define JHB100_PER0CLK_NCNOC_TARG (JHB100_PER0CLK_NUM_CLKS + 5)
+
+char *jhb100_per0_ext_clk[] = {
+ "osc",
+ "pll6",
+ "cfg_400",
+ "cfg_800",
+ "ncnoc_init",
+ "ncnoc_targ",
+};
+
+static const struct starfive_clk_data jhb100_per0crg_clk_data[] = {
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C0, "cdr_i3c0", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C1, "cdr_i3c1", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C2, "cdr_i3c2", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C3, "cdr_i3c3", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C4, "cdr_i3c4", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C5, "cdr_i3c5", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C6, "cdr_i3c6", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C7, "cdr_i3c7", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C8, "cdr_i3c8", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C9, "cdr_i3c9", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C10, "cdr_i3c10", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C11, "cdr_i3c11", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C12, "cdr_i3c12", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C13, "cdr_i3c13", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C14, "cdr_i3c14", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE_GATE(JHB100_PER0CLK_CDR_I3C15, "cdr_i3c15", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_800),
+ STARFIVE__DIV(JHB100_PER0CLK_200, "per0_200", 3,
+ JHB100_PER0CLK_NCNOC_INIT),
+ STARFIVE__DIV(JHB100_PER0CLK_600_DIV6, "per0_600_div6", 6,
+ JHB100_PER0CLK_NCNOC_INIT),
+ STARFIVE__DIV(JHB100_PER0CLK_600_DIV6_DIV5, "per0_600_div6_div5", 5,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_TIMER0_DUALTIMER0, "timer0_dualtimer0", 0,
+ JHB100_PER0CLK_600_DIV6_DIV5),
+ STARFIVE_GATE(JHB100_PER0CLK_TIMER1_DUALTIMER0, "timer1_dualtimer0", 0,
+ JHB100_PER0CLK_600_DIV6_DIV5),
+ STARFIVE_GATE(JHB100_PER0CLK_TIMER0_DUALTIMER1, "timer0_dualtimer1", 0,
+ JHB100_PER0CLK_600_DIV6_DIV5),
+ STARFIVE_GATE(JHB100_PER0CLK_TIMER1_DUALTIMER1, "timer1_dualtimer1", 0,
+ JHB100_PER0CLK_600_DIV6_DIV5),
+ STARFIVE_GATE(JHB100_PER0CLK_TIMER0_DUALTIMER2, "timer0_dualtimer2", 0,
+ JHB100_PER0CLK_600_DIV6_DIV5),
+ STARFIVE_GATE(JHB100_PER0CLK_TIMER1_DUALTIMER2, "timer1_dualtimer2", 0,
+ JHB100_PER0CLK_600_DIV6_DIV5),
+ STARFIVE__DIV(JHB100_PER0CLK_1200_PH0_LVDS0, "1200_ph0_lvds0", 2,
+ JHB100_PER0CLK_PH0_LTPI0),
+ STARFIVE__DIV(JHB100_PER0CLK_1200_PH0_LVDS1, "1200_ph0_lvds1", 2,
+ JHB100_PER0CLK_PH0_LTPI1),
+ STARFIVE__DIV(JHB100_PER0CLK_1200_CORE0, "1200_core0", 2,
+ JHB100_PER0CLK_PLL6),
+ STARFIVE__DIV(JHB100_PER0CLK_1200_CORE1, "1200_core1", 2,
+ JHB100_PER0CLK_PLL6),
+ STARFIVE__DIV(JHB100_PER0CLK_1200_SHIFT90_LVDS0, "1200_shift90_lvds0",
2,
+ JHB100_PER0CLK_PH90_LTPI0),
+ STARFIVE__DIV(JHB100_PER0CLK_1200_SHIFT90_LVDS1, "1200_shift90_lvds1",
2,
+ JHB100_PER0CLK_PH90_LTPI1),
+ STARFIVE__DIV(JHB100_PER0CLK_1200_DIV5_CORE0, "1200_div5_core0", 5,
+ JHB100_PER0CLK_1200_CORE0),
+ STARFIVE__DIV(JHB100_PER0CLK_1200_DIV5_CORE1, "1200_div5_core1", 5,
+ JHB100_PER0CLK_1200_CORE1),
+ STARFIVE__DIV(JHB100_PER0CLK_PH0_LTPI0, "ph0_ltpi0", 48,
+ JHB100_PER0CLK_PLL6),
+ STARFIVE__DIV(JHB100_PER0CLK_PH0_LTPI1, "ph0_ltpi1", 48,
+ JHB100_PER0CLK_PLL6),
+ STARFIVE_IDIV(JHB100_PER0CLK_PH90_LTPI0, "ph90_ltpi0", 0, 48,
+ JHB100_PER0CLK_PLL6),
+ STARFIVE_IDIV(JHB100_PER0CLK_PH90_LTPI1, "ph90_ltpi1", 0, 48,
+ JHB100_PER0CLK_PLL6),
+ STARFIVE__DIV(JHB100_PER0CLK_240_CORE_LTPI0, "240_core_ltpi0", 4,
+ JHB100_PER0CLK_1200_DIV5_CORE0),
+ STARFIVE__DIV(JHB100_PER0CLK_240_CORE_LTPI1, "240_core_ltpi1", 4,
+ JHB100_PER0CLK_1200_DIV5_CORE1),
+ STARFIVE_GATE(JHB100_PER0CLK_AXI_DMA_I2C_INIT, "axi_dma_i2c_init",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_400),
+ STARFIVE_GATE(JHB100_PER0CLK_AXI_DMA_I3C_INIT, "axi_dma_i3c_init",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_400),
+ STARFIVE_GATE(JHB100_PER0CLK_AXI_DMA_UART_INIT, "axi_dma_uart_init",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_CFG_400),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_DMAC0, "core_dmac0",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_DMAC1, "core_dmac1",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_DMAC2, "core_dmac2",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C0, "hdr_tx_i3c0",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C1, "hdr_tx_i3c1",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C2, "hdr_tx_i3c2",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C3, "hdr_tx_i3c3",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C4, "hdr_tx_i3c4",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C5, "hdr_tx_i3c5",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C6, "hdr_tx_i3c6",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C7, "hdr_tx_i3c7",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C8, "hdr_tx_i3c8",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C9, "hdr_tx_i3c9",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C10, "hdr_tx_i3c10",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C11, "hdr_tx_i3c11",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C12, "hdr_tx_i3c12",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C13, "hdr_tx_i3c13",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C14, "hdr_tx_i3c14",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HDR_TX_I3C15, "hdr_tx_i3c15",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C0, "core_i2c0", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C1, "core_i2c1", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C2, "core_i2c2", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C3, "core_i2c3", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C4, "core_i2c4", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C5, "core_i2c5", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C6, "core_i2c6", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C7, "core_i2c7", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C8, "core_i2c8", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C9, "core_i2c9", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C10, "core_i2c10",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C11, "core_i2c11",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C12, "core_i2c12",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C13, "core_i2c13",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C14, "core_i2c14",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I2C15, "core_i2c15",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_WDOGCLK_WDT0, "wdogclk_wdt0",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_WDOGCLK_WDT1, "wdogclk_wdt1",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_WDOGCLK_WDT2, "wdogclk_wdt2",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_WDOGCLK_WDT3, "wdogclk_wdt3",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_WDOGCLK_WDT_EXTERNAL,
"wdogclk_wdt_external",
+ CLK_IGNORE_UNUSED, JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_SCLK_UART4, "sclk_uart4",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_SCLK_UART5, "sclk_uart5",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_SCLK_UART6, "sclk_uart6",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_SCLK_UART7, "sclk_uart7",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_SCLK_UART8, "sclk_uart8",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_SCLK_UART9, "sclk_uart9",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_SCLK_UART10, "sclk_uart10",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_SCLK_UART11, "sclk_uart11",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_SCLK_UART12, "sclk_uart12",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_SCLK_UART13, "sclk_uart13",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_SCLK_UART14, "sclk_uart14",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_PCLK_DMA_UART_CFG, "pclk_dma_uart_cfg",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_PCLK_DMA_I2C_CFG, "pclk_dma_i2c_cfg",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_PCLK_DMA_I3C_CFG, "pclk_dma_i3c_cfg",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_PCLK_DUALTIMER0, "pclk_dualtimer0", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_PCLK_DUALTIMER1, "pclk_dualtimer1", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_PCLK_DUALTIMER2, "pclk_dualtimer2", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_HCLK_TRNG, "hclk_trng", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C0, "apb_i2c0", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C1, "apb_i2c1", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C2, "apb_i2c2", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C3, "apb_i2c3", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C4, "apb_i2c4", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C5, "apb_i2c5", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C6, "apb_i2c6", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C7, "apb_i2c7", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C8, "apb_i2c8", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C9, "apb_i2c9", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C10, "apb_i2c10", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C11, "apb_i2c11", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C12, "apb_i2c12", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C13, "apb_i2c13", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C14, "apb_i2c14", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2C15, "apb_i2c15", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF0, "apb_i2cf0", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF1, "apb_i2cf1", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF2, "apb_i2cf2", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF3, "apb_i2cf3", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF4, "apb_i2cf4", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF5, "apb_i2cf5", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF6, "apb_i2cf6", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF7, "apb_i2cf7", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF8, "apb_i2cf8", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF9, "apb_i2cf9", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF10, "apb_i2cf10",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF11, "apb_i2cf11",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF12, "apb_i2cf12",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF13, "apb_i2cf13",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF14, "apb_i2cf14",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I2CF15, "apb_i2cf15",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C0, "apb_i3c0", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C1, "apb_i3c1", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C2, "apb_i3c2", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C3, "apb_i3c3", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C4, "apb_i3c4", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C5, "apb_i3c5", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C6, "apb_i3c6", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C7, "apb_i3c7", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C8, "apb_i3c8", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C9, "apb_i3c9", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C10, "apb_i3c10", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C11, "apb_i3c11", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C12, "apb_i3c12", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C13, "apb_i3c13", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C14, "apb_i3c14", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_I3C15, "apb_i3c15", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART0, "apb_uart0", CLK_IS_CRITICAL,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART1, "apb_uart1", CLK_IS_CRITICAL,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART2, "apb_uart2", CLK_IS_CRITICAL,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART3, "apb_uart3", CLK_IS_CRITICAL,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART4, "apb_uart4", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART5, "apb_uart5", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART6, "apb_uart6", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART7, "apb_uart7", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART8, "apb_uart8", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART9, "apb_uart9", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART10, "apb_uart10",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART11, "apb_uart11",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART12, "apb_uart12",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART13, "apb_uart13",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_APB_UART14, "apb_uart14",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C0, "dma_i3c0", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C1, "dma_i3c1", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C2, "dma_i3c2", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C3, "dma_i3c3", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C4, "dma_i3c4", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C5, "dma_i3c5", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C6, "dma_i3c6", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C7, "dma_i3c7", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C8, "dma_i3c8", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C9, "dma_i3c9", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C10, "dma_i3c10", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C11, "dma_i3c11", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C12, "dma_i3c12", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C13, "dma_i3c13", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C14, "dma_i3c14", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_DMA_I3C15, "dma_i3c15", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C0, "core_i3c0", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C1, "core_i3c1", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C2, "core_i3c2", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C3, "core_i3c3", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C4, "core_i3c4", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C5, "core_i3c5", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C6, "core_i3c6", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C7, "core_i3c7", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C8, "core_i3c8", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C9, "core_i3c9", CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C10, "core_i3c10",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C11, "core_i3c11",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C12, "core_i3c12",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C13, "core_i3c13",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C14, "core_i3c14",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_CORE_I3C15, "core_i3c15",
CLK_IGNORE_UNUSED,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_DMAC_AXI_PERIPH0_HS_CLK_I2C,
"dmac_axi_periph0_hs_clk_i2c",
+ CLK_IGNORE_UNUSED, JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C0, "main_icg_en_i3c0", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C1, "main_icg_en_i3c1", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C2, "main_icg_en_i3c2", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C3, "main_icg_en_i3c3", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C4, "main_icg_en_i3c4", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C5, "main_icg_en_i3c5", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C6, "main_icg_en_i3c6", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C7, "main_icg_en_i3c7", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C8, "main_icg_en_i3c8", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C9, "main_icg_en_i3c9", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C10, "main_icg_en_i3c10", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C11, "main_icg_en_i3c11", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C12, "main_icg_en_i3c12", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C13, "main_icg_en_i3c13", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C14, "main_icg_en_i3c14", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I3C15, "main_icg_en_i3c15", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER0,
"main_icg_en_dualtimer0",
+ CLK_IS_CRITICAL, JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER1,
"main_icg_en_dualtimer1",
+ CLK_IS_CRITICAL, JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER2,
"main_icg_en_dualtimer2",
+ CLK_IS_CRITICAL, JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_LTPI0, "main_icg_en_ltpi0", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_LTPI1, "main_icg_en_ltpi1", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DMAC_I2C,
"main_icg_en_dmac_i2c",
+ CLK_IS_CRITICAL, JHB100_PER0CLK_CFG_400),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DMAC_I3C,
"main_icg_en_dmac_i3c",
+ CLK_IS_CRITICAL, JHB100_PER0CLK_CFG_400),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_DMAC_UART,
"main_icg_en_dmac_uart",
+ CLK_IS_CRITICAL, JHB100_PER0CLK_CFG_400),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL4, "main_icg_en_sol4", 0,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL5, "main_icg_en_sol5", 0,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL6, "main_icg_en_sol6", 0,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL7, "main_icg_en_sol7", 0,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL8, "main_icg_en_sol8", 0,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL9, "main_icg_en_sol9", 0,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL10, "main_icg_en_sol10", 0,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL11, "main_icg_en_sol11", 0,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL12, "main_icg_en_sol12", 0,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL13, "main_icg_en_sol13", 0,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SOL14, "main_icg_en_sol14", 0,
+ JHB100_PER0CLK_200),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C0, "main_icg_en_i2c0", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C1, "main_icg_en_i2c1", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C2, "main_icg_en_i2c2", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C3, "main_icg_en_i2c3", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C4, "main_icg_en_i2c4", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C5, "main_icg_en_i2c5", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C6, "main_icg_en_i2c6", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C7, "main_icg_en_i2c7", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C8, "main_icg_en_i2c8", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C9, "main_icg_en_i2c9", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C10, "main_icg_en_i2c10", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C11, "main_icg_en_i2c11", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C12, "main_icg_en_i2c12", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C13, "main_icg_en_i2c13", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C14, "main_icg_en_i2c14", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_I2C15, "main_icg_en_i2c15", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_WDT0, "main_icg_en_wdt0", 0,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_WDT1, "main_icg_en_wdt1", 0,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_WDT2, "main_icg_en_wdt2", 0,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_WDT3, "main_icg_en_wdt3", 0,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_WDT_EXTERNAL,
"main_icg_en_wdt_external", 0,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART4, "main_icg_en_uart4",
CLK_IS_CRITICAL,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART5, "main_icg_en_uart5",
CLK_IS_CRITICAL,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART6, "main_icg_en_uart6",
CLK_IS_CRITICAL,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART7, "main_icg_en_uart7",
CLK_IS_CRITICAL,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART8, "main_icg_en_uart8",
CLK_IS_CRITICAL,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART9, "main_icg_en_uart9",
CLK_IS_CRITICAL,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART10, "main_icg_en_uart10",
CLK_IS_CRITICAL,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART11, "main_icg_en_uart11",
CLK_IS_CRITICAL,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART12, "main_icg_en_uart12",
CLK_IS_CRITICAL,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART13, "main_icg_en_uart13",
CLK_IS_CRITICAL,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_UART14, "main_icg_en_uart14",
CLK_IS_CRITICAL,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_LDO0, "main_icg_en_ldo0", 0,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_LDO1, "main_icg_en_ldo1", 0,
+ JHB100_PER0CLK_OSC),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_PERIPH0,
"main_icg_en_sensors_periph0", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_DMAC,
"main_icg_en_sensors_dmac", 0,
+ JHB100_PER0CLK_600_DIV6),
+ STARFIVE_GATE(JHB100_PER0CLK_MAIN_ICG_EN_TRNG, "main_icg_en_trng", 0,
+ JHB100_PER0CLK_NCNOC_TARG),
+};
+
+const struct jhb100_crg_domain_info jhb100_per0crg_info = {
+ .clk_data = jhb100_per0crg_clk_data,
+ .num_clk = ARRAY_SIZE(jhb100_per0crg_clk_data),
+ .ext_clk = jhb100_per0_ext_clk,
+ .num_ext_clk = ARRAY_SIZE(jhb100_per0_ext_clk),
+ .rst_name = "jhb100-r-per0",
+ .power_domain = false,
+};
+
+static const struct of_device_id jhb100_per0crg_match[] = {
+ {
+ .compatible = "starfive,jhb100-per0crg",
+ .data = &jhb100_per0crg_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per0crg_match);
+
+static struct platform_driver jhb100_per0crg_driver = {
+ .probe = starfive_crg_probe,
+ .driver = {
+ .name = "clk-starfive-jhb100-per0",
+ .of_match_table = jhb100_per0crg_match,
+ },
+};
+module_platform_driver(jhb100_per0crg_driver);
+
+MODULE_AUTHOR("Changhuang Liang <[email protected]>");
+MODULE_DESCRIPTION("StarFive JHB100 Peripheral-0 Clock Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
