Add support for JHB100 System-1 clock generator (SYS1CRG).
Signed-off-by: Changhuang Liang <[email protected]>
---
drivers/clk/starfive/Kconfig | 8 ++
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-sys1.c | 105 ++++++++++++++++++
3 files changed, 114 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys1.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 7926e02ccd7d..b6042bcb5992 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -83,3 +83,11 @@ config CLK_STARFIVE_JHB100_SYS0
help
Say yes here to support the system-0 clock controller on the
StarFive JHB100 SoC.
+
+config CLK_STARFIVE_JHB100_SYS1
+ bool "StarFive JHB100 system-1 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS0
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the system-1 clock controller on the
+ StarFive JHB100 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 2c5e66d1d44e..b3571e2f0555 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) +=
clk-starfive-jh7110-isp.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys1.c
b/drivers/clk/starfive/clk-starfive-jhb100-sys1.c
new file mode 100644
index 000000000000..46ef9cc63f9d
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-sys1.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 System-1 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <[email protected]>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-common.h"
+
+#define JHB100_SYS1CLK_NUM_CLKS
(JHB100_SYS1CLK_BMCPER3_CFG_125 + 1)
+
+/* external clocks */
+#define JHB100_SYS1CLK_OSC (JHB100_SYS1CLK_NUM_CLKS + 0)
+#define JHB100_SYS1CLK_PLL0 (JHB100_SYS1CLK_NUM_CLKS + 1)
+#define JHB100_SYS1CLK_PLL1 (JHB100_SYS1CLK_NUM_CLKS + 2)
+#define JHB100_SYS1CLK_PLL2 (JHB100_SYS1CLK_NUM_CLKS + 3)
+#define JHB100_SYS1CLK_PLL4 (JHB100_SYS1CLK_NUM_CLKS + 4)
+#define JHB100_SYS1CLK_PLL5 (JHB100_SYS1CLK_NUM_CLKS + 5)
+#define JHB100_SYS1CLK_NPU_NCNOC_INIT (JHB100_SYS1CLK_NUM_CLKS + 6)
+
+char *jhb100_sys1_ext_clk[] = {
+ "osc",
+ "pll0",
+ "pll1",
+ "pll2",
+ "pll4",
+ "pll5",
+ "npu_ncnoc_init",
+};
+
+static const struct starfive_clk_data jhb100_sys1crg_clk_data[] __initconst = {
+ /* root */
+ STARFIVE__DIV(JHB100_SYS1CLK_APB_MAIN_SYS1, "apb_main_sys1", 12,
+ JHB100_SYS1CLK_PLL1),
+ /* sensor */
+ STARFIVE_GATE(JHB100_SYS1CLK_APB_SENSOR_ICG_BUF, "apb_sensor_icg_buf",
+ CLK_IS_CRITICAL, JHB100_SYS1CLK_APB_MAIN_SYS1),
+ /* hostss1 */
+ STARFIVE__DIV(JHB100_SYS1CLK_GPIO_ESPI1_EXT, "gpio_espi1_ext", 14,
+ JHB100_SYS1CLK_PLL2),
+ STARFIVE__DIV(JHB100_SYS1CLK_HOSTSS1_NCNOC_CFG, "hostss1_ncnoc_cfg", 12,
+ JHB100_SYS1CLK_PLL1),
+ STARFIVE_GATE(JHB100_SYS1CLK_HOSTSS1_PHY_SCAN_1000_ICG_BUF,
+ "hostss1_phy_scan_1000_icg_buf", CLK_IS_CRITICAL,
+ JHB100_SYS1CLK_PLL1),
+ /* npu */
+ STARFIVE__DIV(JHB100_SYS1CLK_NPU_NCNOC_CFG, "npu_ncnoc_cfg", 6,
+ JHB100_SYS1CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS1CLK_NPU_CORE_DIV, "npu_core_div", 10,
+ JHB100_SYS1CLK_PLL0),
+ STARFIVE_GATE(JHB100_SYS1CLK_DOM_NPU_CORE_CLK, "dom_npu_core_clk",
+ CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_CORE_DIV),
+ STARFIVE_GATE(JHB100_SYS1CLK_DOM_NPU_BUS_CLK, "dom_npu_bus_clk",
+ CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_NCNOC_INIT),
+ STARFIVE_GATE(JHB100_SYS1CLK_DOM_NPU_INIT_CLK, "dom_npu_init_clk",
+ CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_NCNOC_CFG),
+ STARFIVE_GATE(JHB100_SYS1CLK_DOM_NPU_OSC_CLK, "dom_npu_osc_clk",
+ CLK_IS_CRITICAL, JHB100_SYS1CLK_OSC),
+ /* vout */
+ STARFIVE__DIV(JHB100_SYS1CLK_VOUT_NCNOC_TARG, "vout_ncnoc_targ", 12,
+ JHB100_SYS1CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS1CLK_VOUT_PIX0, "vout_pix0", 4,
+ JHB100_SYS1CLK_PLL4),
+ STARFIVE__DIV(JHB100_SYS1CLK_VOUT_PIX1, "vout_pix1", 4,
+ JHB100_SYS1CLK_PLL5),
+ /* bmcperiph3 */
+ STARFIVE__DIV(JHB100_SYS1CLK_BMCPER3_NCNOC_TARG, "bmcper3_ncnoc_targ",
12,
+ JHB100_SYS1CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS1CLK_BMCPER3_CFG_125, "bmcper3_cfg_125", 10,
+ JHB100_SYS1CLK_PLL1),
+
+};
+
+const struct jhb100_crg_domain_info jhb100_sys1crg_info = {
+ .clk_data = jhb100_sys1crg_clk_data,
+ .num_clk = ARRAY_SIZE(jhb100_sys1crg_clk_data),
+ .ext_clk = jhb100_sys1_ext_clk,
+ .num_ext_clk = ARRAY_SIZE(jhb100_sys1_ext_clk),
+ .rst_name = "jhb100-r-sys1",
+ .power_domain = false,
+};
+
+static const struct of_device_id jhb100_sys1crg_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys1crg",
+ .data = &jhb100_sys1crg_info,
+ },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jhb100_sys1crg_driver = {
+ .driver = {
+ .name = "clk-starfive-jhb100-sys1",
+ .of_match_table = jhb100_sys1crg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jhb100_sys1crg_driver, starfive_crg_probe);
--
2.25.1
