> > Ok well I cannot cope with the stress of starting up my workstation this > week and I didn't catch any quartus log in your former post? > MiB >
Lol, rough week eh? Post directly after has the quartus snippet with the error, re-ran it,full terminal print attached. Again, only happens if in pinfile: (SSerialTag, x"00", ClockMedTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask), if: (SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask), it will build fine, but SS does not work. -- website: http://www.machinekit.io blog: http://blog.machinekit.io github: https://github.com/machinekit --- You received this message because you are subscribed to the Google Groups "Machinekit" group. To unsubscribe from this group and stop receiving emails from it, send an email to machinekit+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/machinekit/09220b16-ba90-4f24-b5fb-787c2f95ab35%40googlegroups.com.
~$ docker pull cdsteinkuehler/jessie-quartus-15.1.2 Using default tag: latest latest: Pulling from cdsteinkuehler/jessie-quartus-15.1.2 Digest: sha256:78dd9671b810920632a8454ef76cc6a88a702df810c3d400d0da044451a0a0f8 Status: Image is up to date for cdsteinkuehler/jessie-quartus-15.1.2:latest ~$ git clone https://github.com/machinekit/mksocfpga.git/ fatal: destination path 'mksocfpga' already exists and is not an empty directory. ~$ cd mksocfpga ~/mksocfpga$ docker run -itv $(pwd):/work cdsteinkuehler/jessie-quartus-15.1.2 /bin/bash builder@44885c2907a7:/$ cd /work/HW/QuartusProjects/DE10_Nano_FB_Cramps <HW/QuartusProjects/DE10_Nano_FB_Cramps$ ./build.sh st_fpga_soc_dc1f Cleaning stamp files (which will trigger rebuild) TIP: Use 'make scrub_clean' to get a deeper clean rm: cannot remove ‘stamp/quartus.stamp’: No such file or directory Building configuration st_fpga_soc_dc1f qsys-generate soc_system.qsys --synthesis=VERILOG 2019.07.26.21:52:15 Info: Saving generation log to /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/soc_system_generation.rpt 2019.07.26.21:52:15 Info: Starting: <b>Create HDL design files for synthesis</b> 2019.07.26.21:52:15 Info: qsys-generate /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system.qsys --synthesis=VERILOG --output-directory=/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis --family="Cyclone V" --part=5CSEBA6U23I7 2019.07.26.21:52:15 Info: Loading DE10_Nano_FB_Cramps/soc_system.qsys 2019.07.26.21:52:15 Info: Reading input file 2019.07.26.21:52:15 Info: Adding ILC [interrupt_latency_counter 15.1] 2019.07.26.21:52:15 Info: Parameterizing module ILC 2019.07.26.21:52:15 Info: Adding alt_vip_itc_0 [alt_vip_itc 14.0] 2019.07.26.21:52:15 Info: Parameterizing module alt_vip_itc_0 2019.07.26.21:52:15 Info: Adding alt_vip_vfr_hdmi [alt_vip_vfr 14.0] 2019.07.26.21:52:15 Info: Parameterizing module alt_vip_vfr_hdmi 2019.07.26.21:52:15 Info: Adding button_pio [altera_avalon_pio 15.1] 2019.07.26.21:52:15 Info: Parameterizing module button_pio 2019.07.26.21:52:15 Info: Adding clk_0 [clock_source 15.1] 2019.07.26.21:52:15 Info: Parameterizing module clk_0 2019.07.26.21:52:15 Info: Adding dipsw_pio [altera_avalon_pio 15.1] 2019.07.26.21:52:15 Info: Parameterizing module dipsw_pio 2019.07.26.21:52:15 Info: Adding fpga_only_master [altera_jtag_avalon_master 15.1] 2019.07.26.21:52:15 Info: Parameterizing module fpga_only_master 2019.07.26.21:52:15 Info: Adding hm2reg_io_0 [hm2reg_io 1.0] 2019.07.26.21:52:15 Info: Parameterizing module hm2reg_io_0 2019.07.26.21:52:15 Info: Adding hps_0 [altera_hps 15.1] 2019.07.26.21:52:15 Info: Parameterizing module hps_0 2019.07.26.21:52:15 Info: Adding hps_only_master [altera_jtag_avalon_master 15.1] 2019.07.26.21:52:15 Info: Parameterizing module hps_only_master 2019.07.26.21:52:15 Info: Adding intr_capturer_0 [intr_capturer 100.99.98.97] 2019.07.26.21:52:15 Info: Parameterizing module intr_capturer_0 2019.07.26.21:52:15 Info: Adding jtag_uart [altera_avalon_jtag_uart 15.1] 2019.07.26.21:52:15 Info: Parameterizing module jtag_uart 2019.07.26.21:52:15 Info: Adding led_pio [altera_avalon_pio 15.1] 2019.07.26.21:52:15 Info: Parameterizing module led_pio 2019.07.26.21:52:15 Info: Adding mm_bridge_0 [altera_avalon_mm_bridge 15.1] 2019.07.26.21:52:15 Info: Parameterizing module mm_bridge_0 2019.07.26.21:52:15 Info: Adding pll_lcd [altera_pll 15.1] 2019.07.26.21:52:15 Info: Parameterizing module pll_lcd 2019.07.26.21:52:15 Info: Adding sysid_qsys [altera_avalon_sysid_qsys 15.1] 2019.07.26.21:52:15 Info: Parameterizing module sysid_qsys 2019.07.26.21:52:15 Info: Building connections 2019.07.26.21:52:15 Info: Parameterizing connections 2019.07.26.21:52:15 Info: Validating 2019.07.26.21:52:23 Info: Done reading input file 2019.07.26.21:52:25 Warning: soc_system.alt_vip_vfr_hdmi: The module properties SIMULATION_MODEL_IN_VERILOG and SIMULATION_MODEL_IN_VHDL can not both be set when using the SIMULATION file property: src_hdl/alt_vipvfr131_vfr.v, src_hdl/alt_vipvfr131_vfr_controller.v, src_hdl/alt_vipvfr131_vfr_control_packet_encoder.v, src_hdl/alt_vipvfr131_prc.v, src_hdl/alt_vipvfr131_prc_core.v, src_hdl/alt_vipvfr131_prc_read_master.v, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_package.vhd, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_avalon_mm_master.v, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_unpack_data.v, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_avalon_mm_slave.v, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_stream_output.v, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_pulling_width_adapter.vhd, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_general_fifo.vhd, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_fifo_usedw_calculator.vhd, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_gray_clock_crosser.vhd, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_std_logic_vector_delay.vhd, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_one_bit_delay.vhd, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_logic_fifo.vhd, /home/builder/altera_lite/15.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_ram_fifo.vhd 2019.07.26.21:52:25 Info: soc_system.button_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2019.07.26.21:52:25 Info: soc_system.dipsw_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2019.07.26.21:52:25 Info: soc_system.hps_0: HPS Main PLL counter settings: n = 0 m = 63 2019.07.26.21:52:25 Info: soc_system.hps_0: HPS peripherial PLL counter settings: n = 0 m = 39 2019.07.26.21:52:25 Info: soc_system.pll_lcd: The legal reference clock frequency is 5.0 MHz..700.0 MHz 2019.07.26.21:52:25 Info: soc_system.pll_lcd: Able to implement PLL with user settings 2019.07.26.21:52:25 Info: soc_system.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID 2019.07.26.21:52:25 Info: soc_system.sysid_qsys: Time stamp will be automatically updated when this component is generated. 2019.07.26.21:52:25 Warning: soc_system.alt_vip_vfr_hdmi: Interrupt sender <b>alt_vip_vfr_hdmi.interrupt_sender</b> is not connected to an interrupt receiver 2019.07.26.21:52:57 Info: soc_system: Generating <b>soc_system</b> "<b>soc_system</b>" for QUARTUS_SYNTH 2019.07.26.21:53:02 Info: Interconnect is inserted between master alt_vip_vfr_hdmi.avalon_master and slave hps_0.f2h_sdram0_data because the master is of type avalon and the slave is of type axi. 2019.07.26.21:53:03 Info: Interconnect is inserted between master hps_0.h2f_lw_axi_master and slave mm_bridge_0.s0 because the master is of type axi and the slave is of type avalon. 2019.07.26.21:53:04 Info: Inserting clock-crossing logic between cmd_demux.src2 and cmd_mux_002.sink0 2019.07.26.21:53:04 Info: Inserting clock-crossing logic between cmd_demux_001.src2 and cmd_mux_002.sink1 2019.07.26.21:53:04 Info: Inserting clock-crossing logic between rsp_demux_002.src0 and rsp_mux.sink2 2019.07.26.21:53:04 Info: Inserting clock-crossing logic between rsp_demux_002.src1 and rsp_mux_001.sink2 2019.07.26.21:53:05 Info: Interconnect is inserted between master hps_only_master.master and slave hps_0.f2h_axi_slave because the master is of type avalon and the slave is of type axi. 2019.07.26.21:53:06 Warning: hps_0.f2h_irq0: Cannot connect clock for <b>irq_mapper_001.sender</b> 2019.07.26.21:53:06 Warning: hps_0.f2h_irq0: Cannot connect reset for <b>irq_mapper_001.sender</b> 2019.07.26.21:53:06 Warning: hps_0.f2h_irq1: Cannot connect clock for <b>irq_mapper_002.sender</b> 2019.07.26.21:53:06 Warning: hps_0.f2h_irq1: Cannot connect reset for <b>irq_mapper_002.sender</b> 2019.07.26.21:53:10 Info: ILC: "<b>soc_system</b>" instantiated <b>interrupt_latency_counter</b> "<b>ILC</b>" 2019.07.26.21:53:15 Info: alt_vip_itc_0: "<b>soc_system</b>" instantiated <b>alt_vip_itc</b> "<b>alt_vip_itc_0</b>" 2019.07.26.21:53:20 Info: alt_vip_vfr_hdmi: "<b>soc_system</b>" instantiated <b>alt_vip_vfr</b> "<b>alt_vip_vfr_hdmi</b>" 2019.07.26.21:53:20 Info: button_pio: Starting RTL generation for module 'soc_system_button_pio' 2019.07.26.21:53:20 Info: button_pio: Generation command is [exec /home/builder/altera_lite/15.1/quartus/linux64/perl/bin/perl -I /home/builder/altera_lite/15.1/quartus/linux64/perl/lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/europa -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/perl_lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_button_pio --dir=/tmp/alt8103_8289465790330488508.dir/0006_button_pio_gen/ --quartus_dir=/home/builder/altera_lite/15.1/quartus --verilog --config=/tmp/alt8103_8289465790330488508.dir/0006_button_pio_gen//soc_system_button_pio_component_configuration.pl --do_build_sim=0 ] 2019.07.26.21:53:20 Info: button_pio: Done RTL generation for module 'soc_system_button_pio' 2019.07.26.21:53:20 Info: button_pio: "<b>soc_system</b>" instantiated <b>altera_avalon_pio</b> "<b>button_pio</b>" 2019.07.26.21:53:20 Info: dipsw_pio: Starting RTL generation for module 'soc_system_dipsw_pio' 2019.07.26.21:53:20 Info: dipsw_pio: Generation command is [exec /home/builder/altera_lite/15.1/quartus/linux64/perl/bin/perl -I /home/builder/altera_lite/15.1/quartus/linux64/perl/lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/europa -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/perl_lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_dipsw_pio --dir=/tmp/alt8103_8289465790330488508.dir/0007_dipsw_pio_gen/ --quartus_dir=/home/builder/altera_lite/15.1/quartus --verilog --config=/tmp/alt8103_8289465790330488508.dir/0007_dipsw_pio_gen//soc_system_dipsw_pio_component_configuration.pl --do_build_sim=0 ] 2019.07.26.21:53:20 Info: dipsw_pio: Done RTL generation for module 'soc_system_dipsw_pio' 2019.07.26.21:53:20 Info: dipsw_pio: "<b>soc_system</b>" instantiated <b>altera_avalon_pio</b> "<b>dipsw_pio</b>" 2019.07.26.21:53:20 Info: fpga_only_master: "<b>soc_system</b>" instantiated <b>altera_jtag_avalon_master</b> "<b>fpga_only_master</b>" 2019.07.26.21:53:20 Info: hm2reg_io_0: "<b>soc_system</b>" instantiated <b>hm2reg_io</b> "<b>hm2reg_io_0</b>" 2019.07.26.21:53:20 Info: hps_0: "Running for module: hps_0" 2019.07.26.21:53:21 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 63 2019.07.26.21:53:21 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 39 2019.07.26.21:53:22 Info: hps_0: "<b>soc_system</b>" instantiated <b>altera_hps</b> "<b>hps_0</b>" 2019.07.26.21:53:22 Info: intr_capturer_0: "<b>soc_system</b>" instantiated <b>intr_capturer</b> "<b>intr_capturer_0</b>" 2019.07.26.21:53:22 Info: jtag_uart: Starting RTL generation for module 'soc_system_jtag_uart' 2019.07.26.21:53:22 Info: jtag_uart: Generation command is [exec /home/builder/altera_lite/15.1/quartus/linux64/perl/bin/perl -I /home/builder/altera_lite/15.1/quartus/linux64/perl/lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/europa -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/perl_lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=soc_system_jtag_uart --dir=/tmp/alt8103_8289465790330488508.dir/0010_jtag_uart_gen/ --quartus_dir=/home/builder/altera_lite/15.1/quartus --verilog --config=/tmp/alt8103_8289465790330488508.dir/0010_jtag_uart_gen//soc_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] 2019.07.26.21:53:23 Info: jtag_uart: Done RTL generation for module 'soc_system_jtag_uart' 2019.07.26.21:53:23 Info: jtag_uart: "<b>soc_system</b>" instantiated <b>altera_avalon_jtag_uart</b> "<b>jtag_uart</b>" 2019.07.26.21:53:23 Info: led_pio: Starting RTL generation for module 'soc_system_led_pio' 2019.07.26.21:53:23 Info: led_pio: Generation command is [exec /home/builder/altera_lite/15.1/quartus/linux64/perl/bin/perl -I /home/builder/altera_lite/15.1/quartus/linux64/perl/lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/europa -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin/perl_lib -I /home/builder/altera_lite/15.1/quartus/sopc_builder/bin -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/builder/altera_lite/15.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_led_pio --dir=/tmp/alt8103_8289465790330488508.dir/0011_led_pio_gen/ --quartus_dir=/home/builder/altera_lite/15.1/quartus --verilog --config=/tmp/alt8103_8289465790330488508.dir/0011_led_pio_gen//soc_system_led_pio_component_configuration.pl --do_build_sim=0 ] 2019.07.26.21:53:23 Info: led_pio: Done RTL generation for module 'soc_system_led_pio' 2019.07.26.21:53:23 Info: led_pio: "<b>soc_system</b>" instantiated <b>altera_avalon_pio</b> "<b>led_pio</b>" 2019.07.26.21:53:23 Info: mm_bridge_0: "<b>soc_system</b>" instantiated <b>altera_avalon_mm_bridge</b> "<b>mm_bridge_0</b>" 2019.07.26.21:53:23 Info: pll_lcd: "<b>soc_system</b>" instantiated <b>altera_pll</b> "<b>pll_lcd</b>" 2019.07.26.21:53:23 Info: sysid_qsys: "<b>soc_system</b>" instantiated <b>altera_avalon_sysid_qsys</b> "<b>sysid_qsys</b>" 2019.07.26.21:53:23 Info: mm_interconnect_0: "<b>soc_system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>" 2019.07.26.21:53:23 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 2019.07.26.21:53:23 Info: mm_interconnect_1: "<b>soc_system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>" 2019.07.26.21:53:25 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 2019.07.26.21:53:25 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 2019.07.26.21:53:25 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0 2019.07.26.21:53:25 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0 2019.07.26.21:53:25 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0 2019.07.26.21:53:25 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0 2019.07.26.21:53:25 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0 2019.07.26.21:53:25 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0 2019.07.26.21:53:25 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0 2019.07.26.21:53:26 Info: mm_interconnect_2: "<b>soc_system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_2</b>" 2019.07.26.21:53:26 Info: mm_interconnect_3: "<b>soc_system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_3</b>" 2019.07.26.21:53:26 Info: irq_mapper: "<b>soc_system</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>" 2019.07.26.21:53:26 Info: irq_mapper_001: "<b>soc_system</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper_001</b>" 2019.07.26.21:53:26 Info: irq_mapper_002: "<b>soc_system</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper_002</b>" 2019.07.26.21:53:26 Info: rst_controller: "<b>soc_system</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>" 2019.07.26.21:53:26 Info: jtag_phy_embedded_in_jtag_master: "<b>fpga_only_master</b>" instantiated <b>altera_jtag_dc_streaming</b> "<b>jtag_phy_embedded_in_jtag_master</b>" 2019.07.26.21:53:26 Info: timing_adt: "<b>fpga_only_master</b>" instantiated <b>timing_adapter</b> "<b>timing_adt</b>" 2019.07.26.21:53:26 Info: fifo: "<b>fpga_only_master</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>fifo</b>" 2019.07.26.21:53:26 Info: b2p: "<b>fpga_only_master</b>" instantiated <b>altera_avalon_st_bytes_to_packets</b> "<b>b2p</b>" 2019.07.26.21:53:26 Info: p2b: "<b>fpga_only_master</b>" instantiated <b>altera_avalon_st_packets_to_bytes</b> "<b>p2b</b>" 2019.07.26.21:53:26 Info: transacto: "<b>fpga_only_master</b>" instantiated <b>altera_avalon_packets_to_master</b> "<b>transacto</b>" 2019.07.26.21:53:26 Info: b2p_adapter: "<b>fpga_only_master</b>" instantiated <b>channel_adapter</b> "<b>b2p_adapter</b>" 2019.07.26.21:53:26 Info: p2b_adapter: "<b>fpga_only_master</b>" instantiated <b>channel_adapter</b> "<b>p2b_adapter</b>" 2019.07.26.21:53:26 Info: fpga_interfaces: "<b>hps_0</b>" instantiated <b>altera_interface_generator</b> "<b>fpga_interfaces</b>" 2019.07.26.21:53:26 Info: hps_io: "<b>hps_0</b>" instantiated <b>altera_hps_io</b> "<b>hps_io</b>" 2019.07.26.21:53:26 Info: alt_vip_vfr_hdmi_avalon_master_translator: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>alt_vip_vfr_hdmi_avalon_master_translator</b>" 2019.07.26.21:53:26 Info: alt_vip_vfr_hdmi_avalon_master_agent: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_agent</b> "<b>alt_vip_vfr_hdmi_avalon_master_agent</b>" 2019.07.26.21:53:26 Info: hps_0_f2h_sdram0_data_agent: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_axi_slave_ni</b> "<b>hps_0_f2h_sdram0_data_agent</b>" 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v</b> 2019.07.26.21:53:26 Info: router: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>" 2019.07.26.21:53:26 Info: router_001: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>" 2019.07.26.21:53:26 Info: alt_vip_vfr_hdmi_avalon_master_limiter: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>alt_vip_vfr_hdmi_avalon_master_limiter</b>" 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v</b> 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v</b> 2019.07.26.21:53:26 Info: hps_0_f2h_sdram0_data_wr_burst_adapter: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>hps_0_f2h_sdram0_data_wr_burst_adapter</b>" 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b> 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv</b> 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v</b> 2019.07.26.21:53:26 Info: cmd_demux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>" 2019.07.26.21:53:26 Info: cmd_mux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>" 2019.07.26.21:53:26 Info: rsp_demux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>" 2019.07.26.21:53:26 Info: rsp_mux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>" 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b> 2019.07.26.21:53:26 Info: mm_bridge_0_s0_translator: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>mm_bridge_0_s0_translator</b>" 2019.07.26.21:53:26 Info: hps_0_h2f_lw_axi_master_agent: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_axi_master_ni</b> "<b>hps_0_h2f_lw_axi_master_agent</b>" 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b> 2019.07.26.21:53:26 Info: mm_bridge_0_s0_agent: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>mm_bridge_0_s0_agent</b>" 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b> 2019.07.26.21:53:26 Info: router: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>" 2019.07.26.21:53:26 Info: router_002: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>" 2019.07.26.21:53:26 Info: cmd_demux: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>" 2019.07.26.21:53:26 Info: cmd_mux: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>" 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b> 2019.07.26.21:53:26 Info: rsp_demux: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>" 2019.07.26.21:53:26 Info: rsp_mux: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>" 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b> 2019.07.26.21:53:26 Info: avalon_st_adapter: "<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>" 2019.07.26.21:53:26 Info: router: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>" 2019.07.26.21:53:26 Info: router_002: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>" 2019.07.26.21:53:26 Info: cmd_demux: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>" 2019.07.26.21:53:26 Info: cmd_mux: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>" 2019.07.26.21:53:26 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b> 2019.07.26.21:53:26 Info: rsp_demux: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>" 2019.07.26.21:53:26 Info: rsp_demux_002: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_002</b>" 2019.07.26.21:53:27 Info: rsp_mux: "<b>mm_interconnect_2</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>" 2019.07.26.21:53:27 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b> 2019.07.26.21:53:27 Info: crosser: "<b>mm_interconnect_2</b>" instantiated <b>altera_avalon_st_handshake_clock_crosser</b> "<b>crosser</b>" 2019.07.26.21:53:27 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_clock_crosser.v</b> 2019.07.26.21:53:27 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v</b> 2019.07.26.21:53:27 Warning: Overwriting different file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_std_synchronizer_nocut.v</b> 2019.07.26.21:53:27 Info: router: "<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>" 2019.07.26.21:53:27 Info: router_001: "<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>" 2019.07.26.21:53:27 Info: cmd_demux: "<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>" 2019.07.26.21:53:27 Info: cmd_mux: "<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>" 2019.07.26.21:53:27 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b> 2019.07.26.21:53:27 Info: rsp_demux: "<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>" 2019.07.26.21:53:27 Info: rsp_mux: "<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>" 2019.07.26.21:53:27 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b> 2019.07.26.21:53:27 Info: hps_0_f2h_axi_slave_wr_cmd_width_adapter: "<b>mm_interconnect_3</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>hps_0_f2h_axi_slave_wr_cmd_width_adapter</b>" 2019.07.26.21:53:27 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b> 2019.07.26.21:53:27 Info: Reusing file <b>/work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b> 2019.07.26.21:53:58 Info: border: "<b>hps_io</b>" instantiated <b>altera_interface_generator</b> "<b>border</b>" 2019.07.26.21:53:58 Info: error_adapter_0: "<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>" 2019.07.26.21:53:58 Info: soc_system: Done "<b>soc_system</b>" with 71 modules, 177 files 2019.07.26.21:53:59 Info: qsys-generate succeeded. 2019.07.26.21:53:59 Info: Finished: <b>Create HDL design files for synthesis</b> quartus_map DE10_Nano_FB_Cramps.qpf Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 15.1.2 Build 193 02/01/2016 SJ Lite Edition Info: Copyright (C) 1991-2016 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Altera and sold by Altera or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Fri Jul 26 21:54:01 2019 Info: Command: quartus_map DE10_Nano_FB_Cramps.qpf Critical Warning (138067): Current license file does not support incremental compilation. The Quartus Prime software removes all the user-specified design partitions in the design automatically. Info (20032): Parallel compilation is enabled and will use up to 8 processors Warning (20031): Parallel compilation is enabled for 8 processors, but there are only 4 processors in the system. Runtime may increase due to over usage of the processor space. Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed! Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/firmware_id.vhd Info (12022): Found design unit 1: firmware_id-arch File: /work/HW/QuartusProjects/Common/firmware_id.vhd Line: 81 Info (12023): Found entity 1: firmware_id File: /work/HW/QuartusProjects/Common/firmware_id.vhd Line: 72 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/config/DExx_Nano_xxx_Cramps/hostmot3_cfg.vhd Info (12022): Found design unit 1: HostMot3_cfg-arch File: /work/HW/hm2/config/DExx_Nano_xxx_Cramps/hostmot3_cfg.vhd Line: 126 Info (12023): Found entity 1: HostMot3_cfg File: /work/HW/hm2/config/DExx_Nano_xxx_Cramps/hostmot3_cfg.vhd Line: 73 Info (12021): Found 1 design units, including 0 entities, in source file /work/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_st_fpga_soc_dc1f.sv Info (12022): Found design unit 1: boardtype (SystemVerilog) File: /work/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_st_fpga_soc_dc1f.sv Line: 1 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/cv-megawizard/lpm_pack.vhd Info (12022): Found design unit 1: LPM_COMPONENTS File: /work/HW/cv-megawizard/lpm_pack.vhd Line: 170 Info (12022): Found design unit 2: LPM_COMPONENTS-body File: /work/HW/cv-megawizard/lpm_pack.vhd Line: 678 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/cv-megawizard/lpm-ip/lpm_mux16.vhd Info (12022): Found design unit 1: lpm_mux16-SYN File: /work/HW/cv-megawizard/lpm-ip/lpm_mux16.vhd Line: 68 Info (12023): Found entity 1: lpm_mux16 File: /work/HW/cv-megawizard/lpm-ip/lpm_mux16.vhd Line: 43 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.vhd Info (12022): Found design unit 1: lpm_shiftreg16-SYN File: /work/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.vhd Line: 54 Info (12023): Found entity 1: lpm_shiftreg16 File: /work/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.vhd Line: 43 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/cv-megawizard/SRL16E.vhd Info (12022): Found design unit 1: SRL16E-arch File: /work/HW/cv-megawizard/SRL16E.vhd Line: 26 Info (12023): Found entity 1: SRL16E File: /work/HW/cv-megawizard/SRL16E.vhd Line: 9 Info (12021): Found 1 design units, including 0 entities, in source file /work/HW/hm2/config/IDROMConst.vhd Info (12022): Found design unit 1: IDROMConst File: /work/HW/hm2/config/IDROMConst.vhd Line: 70 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/PinExists.vhd Info (12022): Found design unit 1: PinExists File: /work/HW/hm2/functions/PinExists.vhd Line: 71 Info (12022): Found design unit 2: PinExists-body File: /work/HW/hm2/functions/PinExists.vhd Line: 75 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/oneofndecode.vhd Info (12022): Found design unit 1: oneofndecode File: /work/HW/hm2/functions/oneofndecode.vhd Line: 70 Info (12022): Found design unit 2: oneofndecode-body File: /work/HW/hm2/functions/oneofndecode.vhd Line: 74 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/NumberOfModules.vhd Info (12022): Found design unit 1: NumberOfModules File: /work/HW/hm2/functions/NumberOfModules.vhd Line: 71 Info (12022): Found design unit 2: NumberOfModules-body File: /work/HW/hm2/functions/NumberOfModules.vhd Line: 75 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/ModuleExists.vhd Info (12022): Found design unit 1: ModuleExists File: /work/HW/hm2/functions/ModuleExists.vhd Line: 71 Info (12022): Found design unit 2: ModuleExists-body File: /work/HW/hm2/functions/ModuleExists.vhd Line: 75 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/MaxPinsPerModule.vhd Info (12022): Found design unit 1: MaxPinsPerModule File: /work/HW/hm2/functions/MaxPinsPerModule.vhd Line: 71 Info (12022): Found design unit 2: MaxPinsPerModule-body File: /work/HW/hm2/functions/MaxPinsPerModule.vhd Line: 75 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/MaxOutputPinsPerModule.vhd Info (12022): Found design unit 1: MaxOutputPinsPerModule File: /work/HW/hm2/functions/MaxOutputPinsPerModule.vhd Line: 71 Info (12022): Found design unit 2: MaxOutputPinsPerModule-body File: /work/HW/hm2/functions/MaxOutputPinsPerModule.vhd Line: 75 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/MaxIOPinsPerModule.vhd Info (12022): Found design unit 1: MaxIOPinsPerModule File: /work/HW/hm2/functions/MaxIOPinsPerModule.vhd Line: 71 Info (12022): Found design unit 2: MaxIOPinsPerModule-body File: /work/HW/hm2/functions/MaxIOPinsPerModule.vhd Line: 75 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/MaxInputPinsPerModule.vhd Info (12022): Found design unit 1: MaxInputPinsPerModule File: /work/HW/hm2/functions/MaxInputPinsPerModule.vhd Line: 71 Info (12022): Found design unit 2: MaxInputPinsPerModule-body File: /work/HW/hm2/functions/MaxInputPinsPerModule.vhd Line: 75 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/log2.vhd Info (12022): Found design unit 1: log2 File: /work/HW/hm2/functions/log2.vhd Line: 70 Info (12022): Found design unit 2: log2-body File: /work/HW/hm2/functions/log2.vhd Line: 74 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/InputPinsPerModule.vhd Info (12022): Found design unit 1: InputPinsPerModule File: /work/HW/hm2/functions/InputPinsPerModule.vhd Line: 71 Info (12022): Found design unit 2: InputPinsPerModule-body File: /work/HW/hm2/functions/InputPinsPerModule.vhd Line: 75 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/decodedstrobe.vhd Info (12022): Found design unit 1: decodedstrobe File: /work/HW/hm2/functions/decodedstrobe.vhd Line: 70 Info (12022): Found design unit 2: decodedstrobe-body File: /work/HW/hm2/functions/decodedstrobe.vhd Line: 74 Info (12021): Found 2 design units, including 0 entities, in source file /work/HW/hm2/functions/CountPinsInRange.vhd Info (12022): Found design unit 1: CountPinsInRange File: /work/HW/hm2/functions/CountPinsInRange.vhd Line: 71 Info (12022): Found design unit 2: CountPinsInRange-body File: /work/HW/hm2/functions/CountPinsInRange.vhd Line: 75 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/hostmot3.vhd Info (12022): Found design unit 1: HostMot3-dataflow File: /work/HW/hm2/hostmot3.vhd Line: 142 Info (12023): Found entity 1: HostMot3 File: /work/HW/hm2/hostmot3.vhd Line: 84 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeIOPorts.vhd Info (12022): Found design unit 1: MakeIOPorts-dataflow File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 93 Info (12023): Found entity 1: MakeIOPorts File: /work/HW/hm2/wrappers/MakeIOPorts.vhd Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeHm2Dpllmods.vhd Info (12022): Found design unit 1: MakeHm2Dpllmods-dataflow File: /work/HW/hm2/wrappers/MakeHm2Dpllmods.vhd Line: 62 Info (12023): Found entity 1: MakeHm2Dpllmods File: /work/HW/hm2/wrappers/MakeHm2Dpllmods.vhd Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeStepgens.vhd Info (12022): Found design unit 1: MakeStepgens-dataflow File: /work/HW/hm2/wrappers/MakeStepgens.vhd Line: 62 Info (12023): Found entity 1: MakeStepgens File: /work/HW/hm2/wrappers/MakeStepgens.vhd Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeQCounters.vhd Info (12022): Found design unit 1: MakeQCounters-dataflow File: /work/HW/hm2/wrappers/MakeQCounters.vhd Line: 62 Info (12023): Found entity 1: MakeQCounters File: /work/HW/hm2/wrappers/MakeQCounters.vhd Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeMuxedQCounters.vhd Info (12022): Found design unit 1: MakeMuxedQCounters-dataflow File: /work/HW/hm2/wrappers/MakeMuxedQCounters.vhd Line: 62 Info (12023): Found entity 1: MakeMuxedQCounters File: /work/HW/hm2/wrappers/MakeMuxedQCounters.vhd Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakePwmgens.vhd Info (12022): Found design unit 1: MakePWMgens-dataflow File: /work/HW/hm2/wrappers/MakePwmgens.vhd Line: 62 Info (12023): Found entity 1: MakePWMgens File: /work/HW/hm2/wrappers/MakePwmgens.vhd Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeTPPWMGens.vhd Info (12022): Found design unit 1: MakeTPPWMGens-dataflow File: /work/HW/hm2/wrappers/MakeTPPWMGens.vhd Line: 62 Info (12023): Found entity 1: MakeTPPWMGens File: /work/HW/hm2/wrappers/MakeTPPWMGens.vhd Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeSPIs.vhd Info (12022): Found design unit 1: MakeSPIs-dataflow File: /work/HW/hm2/wrappers/MakeSPIs.vhd Line: 63 Info (12023): Found entity 1: MakeSPIs File: /work/HW/hm2/wrappers/MakeSPIs.vhd Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeBSPIs.vhd Info (12022): Found design unit 1: MakeBSPIs-dataflow File: /work/HW/hm2/wrappers/MakeBSPIs.vhd Line: 65 Info (12023): Found entity 1: MakeBSPIs File: /work/HW/hm2/wrappers/MakeBSPIs.vhd Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wrappers/MakeDBSPIs.vhd Info (12022): Found design unit 1: MakeDBSPIs-dataflow File: /work/HW/hm2/wrappers/MakeDBSPIs.vhd Line: 67 Info (12023): Found entity 1: MakeDBSPIs File: /work/HW/hm2/wrappers/MakeDBSPIs.vhd Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/kubstepgenzi.vhd Info (12022): Found design unit 1: stepgeni-Behavioral File: /work/HW/hm2/kubstepgenzi.vhd Line: 111 Info (12023): Found entity 1: stepgeni File: /work/HW/hm2/kubstepgenzi.vhd Line: 73 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/kubstepgenz.vhd Info (12022): Found design unit 1: stepgen-Behavioral File: /work/HW/hm2/kubstepgenz.vhd Line: 108 Info (12023): Found entity 1: stepgen File: /work/HW/hm2/kubstepgenz.vhd Line: 73 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wordrb.vhd Info (12022): Found design unit 1: wordrb-behavioral File: /work/HW/hm2/wordrb.vhd Line: 79 Info (12023): Found entity 1: wordrb File: /work/HW/hm2/wordrb.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/wordpr.vhd Info (12022): Found design unit 1: wordpr-behavioral File: /work/HW/hm2/wordpr.vhd Line: 92 Info (12023): Found entity 1: wordpr File: /work/HW/hm2/wordpr.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/watchdog.vhd Info (12022): Found design unit 1: watchdog-Behavioral File: /work/HW/hm2/watchdog.vhd Line: 88 Info (12023): Found entity 1: watchdog File: /work/HW/hm2/watchdog.vhd Line: 72 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/pwmrefh.vhd Info (12022): Found design unit 1: pwmrefh-behavioral File: /work/HW/hm2/pwmrefh.vhd Line: 86 Info (12023): Found entity 1: pwmrefh File: /work/HW/hm2/pwmrefh.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/pwmpdmgenh.vhd Info (12022): Found design unit 1: pwmpdmgenh-behavioral File: /work/HW/hm2/pwmpdmgenh.vhd Line: 88 Info (12023): Found entity 1: pwmpdmgenh File: /work/HW/hm2/pwmpdmgenh.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/irqlogics.vhd Info (12022): Found design unit 1: irqlogics-Behavioral File: /work/HW/hm2/irqlogics.vhd Line: 85 Info (12023): Found entity 1: irqlogics File: /work/HW/hm2/irqlogics.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/hostmotid.vhd Info (12022): Found design unit 1: hostmotid-Behavioral File: /work/HW/hm2/hostmotid.vhd Line: 85 Info (12023): Found entity 1: hostmotid File: /work/HW/hm2/hostmotid.vhd Line: 72 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/hmtimers.vhd Info (12022): Found design unit 1: hm2dpll-behavioral File: /work/HW/hm2/hmtimers.vhd Line: 95 Info (12023): Found entity 1: hm2dpll File: /work/HW/hm2/hmtimers.vhd Line: 69 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/drqlogic.vhd Info (12022): Found design unit 1: dmdrqlogic-Behavioral File: /work/HW/hm2/drqlogic.vhd Line: 21 Info (12023): Found entity 1: dmdrqlogic File: /work/HW/hm2/drqlogic.vhd Line: 8 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/boutreg.vhd Info (12022): Found design unit 1: boutreg-Behavioral File: /work/HW/hm2/boutreg.vhd Line: 87 Info (12023): Found entity 1: boutreg File: /work/HW/hm2/boutreg.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/ubrategen.vhd Info (12022): Found design unit 1: rategen-Behavioral File: /work/HW/hm2/ubrategen.vhd Line: 80 Info (12023): Found entity 1: rategen File: /work/HW/hm2/ubrategen.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/qcountersf.vhd Info (12022): Found design unit 1: qcounter-behavioral File: /work/HW/hm2/qcountersf.vhd Line: 91 Info (12023): Found entity 1: qcounter File: /work/HW/hm2/qcountersf.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/qcounterate.vhd Info (12022): Found design unit 1: qcounterate-Behavioral File: /work/HW/hm2/qcounterate.vhd Line: 80 Info (12023): Found entity 1: qcounterate File: /work/HW/hm2/qcounterate.vhd Line: 71 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/qcountersfp.vhd Info (12022): Found design unit 1: qcounterp-behavioral File: /work/HW/hm2/qcountersfp.vhd Line: 92 Info (12023): Found entity 1: qcounterp File: /work/HW/hm2/qcountersfp.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/timestamp.vhd Info (12022): Found design unit 1: timestamp-Behavioral File: /work/HW/hm2/timestamp.vhd Line: 82 Info (12023): Found entity 1: timestamp File: /work/HW/hm2/timestamp.vhd Line: 72 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/qcounteratesk.vhd Info (12022): Found design unit 1: qcounteratesk-Behavioral File: /work/HW/hm2/qcounteratesk.vhd Line: 84 Info (12023): Found entity 1: qcounteratesk File: /work/HW/hm2/qcounteratesk.vhd Line: 74 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/srl16delay.vhd Info (12022): Found design unit 1: srl16delay-Behavioral File: /work/HW/hm2/srl16delay.vhd Line: 78 Info (12023): Found entity 1: srl16delay File: /work/HW/hm2/srl16delay.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/bufferedspi.vhd Info (12022): Found design unit 1: bufferedspi-behavioral File: /work/HW/hm2/bufferedspi.vhd Line: 94 Info (12023): Found entity 1: bufferedspi File: /work/HW/hm2/bufferedspi.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/threephasepwm.vhd Info (12022): Found design unit 1: threephasepwm-behavioral File: /work/HW/hm2/threephasepwm.vhd Line: 95 Info (12023): Found entity 1: threephasepwm File: /work/HW/hm2/threephasepwm.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/simplespix.vhd Info (12022): Found design unit 1: simplespi-behavioral File: /work/HW/hm2/simplespix.vhd Line: 92 Info (12023): Found entity 1: simplespi File: /work/HW/hm2/simplespix.vhd Line: 70 Info (12021): Found 2 design units, including 1 entities, in source file /work/HW/hm2/idrom.vhd Info (12022): Found design unit 1: IDROM-syn File: /work/HW/hm2/idrom.vhd Line: 104 Info (12023): Found entity 1: IDROM File: /work/HW/hm2/idrom.vhd Line: 73 Info (12021): Found 1 design units, including 0 entities, in source file /work/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_st_fpga_soc_dc1f.vhd Info (12022): Found design unit 1: Pintypes (pin) File: /work/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_st_fpga_soc_dc1f.vhd Line: 72 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/capsense.sv Info (12023): Found entity 1: capsense File: /work/HW/QuartusProjects/Common/capsense.sv Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/top_io_modules.sv Info (12023): Found entity 1: top_io_modules File: /work/HW/QuartusProjects/Common/top_io_modules.sv Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/cv-ip/debounce/debounce.v Info (12023): Found entity 1: debounce File: /work/HW/cv-ip/debounce/debounce.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/cv-ip/altsource_probe/hps_reset.v Info (12023): Found entity 1: hps_reset File: /work/HW/cv-ip/altsource_probe/hps_reset.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/cv-ip/edge_detect/altera_edge_detector.v Info (12023): Found entity 1: altera_edge_detector File: /work/HW/cv-ip/edge_detect/altera_edge_detector.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/cv-ip/intr_capturer/intr_capturer.v Info (12023): Found entity 1: intr_capturer File: /work/HW/cv-ip/intr_capturer/intr_capturer.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/led_blinker.sv Info (12023): Found entity 1: led_blinker File: /work/HW/QuartusProjects/Common/led_blinker.sv Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/soc_system.v Info (12023): Found entity 1: soc_system File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/soc_system.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_reset_controller.v Info (12023): Found entity 1: altera_reset_controller File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_reset_controller.v Line: 42 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_reset_synchronizer.v Info (12023): Found entity 1: altera_reset_synchronizer File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_reset_synchronizer.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_irq_mapper_002.sv Info (12023): Found entity 1: soc_system_irq_mapper_002 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_irq_mapper_002.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_irq_mapper_001.sv Info (12023): Found entity 1: soc_system_irq_mapper_001 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_irq_mapper_001.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_irq_mapper.sv Info (12023): Found entity 1: soc_system_irq_mapper File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_irq_mapper.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_3.v Info (12023): Found entity 1: soc_system_mm_interconnect_3 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_3.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_width_adapter.sv Info (12023): Found entity 1: altera_merlin_width_adapter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_address_alignment.sv Info (12023): Found entity 1: altera_merlin_address_alignment File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv Line: 26 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Line: 40 Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Info (12023): Found entity 1: altera_merlin_arbitrator File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 103 Info (12023): Found entity 2: altera_merlin_arb_adder File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 228 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_3_rsp_mux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_3_rsp_mux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_3_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_3_rsp_demux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_3_rsp_demux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_3_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_3_cmd_mux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_3_cmd_mux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_3_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_3_cmd_demux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_3_cmd_demux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_3_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv Info (12023): Found entity 1: altera_merlin_traffic_limiter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv Line: 49 Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv Info (12023): Found entity 1: altera_merlin_reorder_memory File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 28 Info (12023): Found entity 2: memory_pointer_controller File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 185 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_sc_fifo.v Info (12023): Found entity 1: altera_avalon_sc_fifo File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v Line: 22 Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_3_router_001.sv Info (12023): Found entity 1: soc_system_mm_interconnect_3_router_001_default_decode File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_3_router_001.sv Line: 45 Info (12023): Found entity 2: soc_system_mm_interconnect_3_router_001 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_3_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_3_router.sv Info (12023): Found entity 1: soc_system_mm_interconnect_3_router_default_decode File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_3_router.sv Line: 45 Info (12023): Found entity 2: soc_system_mm_interconnect_3_router File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_3_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_axi_slave_ni.sv Info (12023): Found entity 1: altera_merlin_axi_slave_ni File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_axi_slave_ni.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_master_agent.sv Info (12023): Found entity 1: altera_merlin_master_agent File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_master_agent.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_master_translator.sv Info (12023): Found entity 1: altera_merlin_master_translator File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_master_translator.sv Line: 32 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2.v Info (12023): Found entity 1: soc_system_mm_interconnect_2 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_avalon_st_adapter.v Info (12023): Found entity 1: soc_system_mm_interconnect_1_avalon_st_adapter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: soc_system_mm_interconnect_1_avalon_st_adapter_error_adapter_0 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_handshake_clock_crosser File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_clock_crosser File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_clock_crosser.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_std_synchronizer_nocut.v Info (12023): Found entity 1: altera_std_synchronizer_nocut File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_std_synchronizer_nocut.v Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_rsp_mux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_2_rsp_mux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_rsp_demux_002.sv Info (12023): Found entity 1: soc_system_mm_interconnect_2_rsp_demux_002 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_rsp_demux_002.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_rsp_demux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_2_rsp_demux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_cmd_mux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_2_cmd_mux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_cmd_demux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_2_cmd_demux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router_002.sv Info (12023): Found entity 1: soc_system_mm_interconnect_2_router_002_default_decode File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router_002.sv Line: 45 Info (12023): Found entity 2: soc_system_mm_interconnect_2_router_002 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router.sv Info (12023): Found entity 1: soc_system_mm_interconnect_2_router_default_decode File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router.sv Line: 45 Info (12023): Found entity 2: soc_system_mm_interconnect_2_router File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_2_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_slave_agent.sv Info (12023): Found entity 1: altera_merlin_slave_agent File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_slave_translator.sv Info (12023): Found entity 1: altera_merlin_slave_translator File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_slave_translator.sv Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1.v Info (12023): Found entity 1: soc_system_mm_interconnect_1 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_mux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_1_rsp_mux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_demux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_1_rsp_demux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_mux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_1_cmd_mux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_demux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_1_cmd_demux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv Info (12023): Found entity 1: altera_merlin_burst_adapter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Line: 39 Info (12021): Found 5 design units, including 5 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 40 Info (12023): Found entity 2: altera_merlin_burst_adapter_adder File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 55 Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 77 Info (12023): Found entity 4: altera_merlin_burst_adapter_min File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 98 Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 264 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_new File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_incr_burst_converter.sv Info (12023): Found entity 1: altera_incr_burst_converter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_incr_burst_converter.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_wrap_burst_converter.sv Info (12023): Found entity 1: altera_wrap_burst_converter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_wrap_burst_converter.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_default_burst_converter.sv Info (12023): Found entity 1: altera_default_burst_converter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_default_burst_converter.sv Line: 30 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Info (12023): Found entity 1: altera_avalon_st_pipeline_stage File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Line: 22 Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_002.sv Info (12023): Found entity 1: soc_system_mm_interconnect_1_router_002_default_decode File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_002.sv Line: 45 Info (12023): Found entity 2: soc_system_mm_interconnect_1_router_002 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router.sv Info (12023): Found entity 1: soc_system_mm_interconnect_1_router_default_decode File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router.sv Line: 45 Info (12023): Found entity 2: soc_system_mm_interconnect_1_router File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv Info (12023): Found entity 1: altera_merlin_axi_master_ni File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v Info (12023): Found entity 1: soc_system_mm_interconnect_0 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_0_rsp_mux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_0_rsp_demux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_0_cmd_mux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: soc_system_mm_interconnect_0_cmd_demux File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: soc_system_mm_interconnect_0_router_001_default_decode File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: soc_system_mm_interconnect_0_router_001 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv Info (12023): Found entity 1: soc_system_mm_interconnect_0_router_default_decode File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: soc_system_mm_interconnect_0_router File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_sysid_qsys.v Info (12023): Found entity 1: soc_system_sysid_qsys File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_sysid_qsys.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_pll_lcd.v Info (12023): Found entity 1: soc_system_pll_lcd File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_pll_lcd.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_mm_bridge.v Info (12023): Found entity 1: altera_avalon_mm_bridge File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_mm_bridge.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_led_pio.v Info (12023): Found entity 1: soc_system_led_pio File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_led_pio.v Line: 21 Info (12021): Found 5 design units, including 5 entities, in source file soc_system/synthesis/submodules/soc_system_jtag_uart.v Info (12023): Found entity 1: soc_system_jtag_uart_sim_scfifo_w File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_jtag_uart.v Line: 21 Info (12023): Found entity 2: soc_system_jtag_uart_scfifo_w File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_jtag_uart.v Line: 77 Info (12023): Found entity 3: soc_system_jtag_uart_sim_scfifo_r File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_jtag_uart.v Line: 162 Info (12023): Found entity 4: soc_system_jtag_uart_scfifo_r File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_jtag_uart.v Line: 240 Info (12023): Found entity 5: soc_system_jtag_uart File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_jtag_uart.v Line: 327 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/intr_capturer.v Info (12023): Found entity 1: intr_capturer File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/intr_capturer.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0.v Info (12023): Found entity 1: soc_system_hps_0 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_hps_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v Info (12023): Found entity 1: soc_system_hps_0_hps_io File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram.v Info (12023): Found entity 1: hps_sdram File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v Info (12023): Found entity 1: altera_mem_if_hhp_qseq_synth_top File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_memphy File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_dll_cyclonev File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v Info (12023): Found entity 1: hps_sdram_p0_reset_sync File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0.sv Info (12023): Found entity 1: hps_sdram_p0 File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Info (12023): Found entity 1: hps_sdram_p0_altdqdqs File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_io_pads File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Info (12023): Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Info (12023): Found entity 1: hps_sdram_p0_acv_ldc File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v Info (12023): Found entity 1: hps_sdram_p0_generic_ddio File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_oct_cyclonev File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Info (12023): Found entity 1: hps_sdram_p0_clock_pair_generator File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Line: 29 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_reset.v Info (12023): Found entity 1: hps_sdram_p0_reset File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_reset.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv Info (12023): Found entity 1: hps_sdram_p0_phy_csr File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v Info (12023): Found entity 1: hps_sdram_p0_iss_probe File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_pll.sv Info (12023): Found entity 1: hps_sdram_pll File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_pll.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv Info (12023): Found entity 1: soc_system_hps_0_hps_io_border File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv Info (12023): Found entity 1: soc_system_hps_0_fpga_interfaces File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hm2reg_io.v Info (12023): Found entity 1: hm2reg_io File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hm2reg_io.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_fpga_only_master.v Info (12023): Found entity 1: soc_system_fpga_only_master File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_fpga_only_master.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_fpga_only_master_p2b_adapter.sv Info (12023): Found entity 1: soc_system_fpga_only_master_p2b_adapter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_fpga_only_master_p2b_adapter.sv Line: 55 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_fpga_only_master_b2p_adapter.sv Info (12023): Found entity 1: soc_system_fpga_only_master_b2p_adapter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_fpga_only_master_b2p_adapter.sv Line: 55 Info (12021): Found 7 design units, including 7 entities, in source file soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Info (12023): Found entity 1: altera_avalon_packets_to_master File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 22 Info (12023): Found entity 2: packets_to_fifo File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 142 Info (12023): Found entity 3: fifo_buffer_single_clock_fifo File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 512 Info (12023): Found entity 4: fifo_buffer_scfifo_with_controls File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 573 Info (12023): Found entity 5: fifo_buffer File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 627 Info (12023): Found entity 6: fifo_to_packet File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 697 Info (12023): Found entity 7: packets_to_master File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_packets_to_master.v Line: 851 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_packets_to_bytes.v Info (12023): Found entity 1: altera_avalon_st_packets_to_bytes File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_packets_to_bytes.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_bytes_to_packets.v Info (12023): Found entity 1: altera_avalon_st_bytes_to_packets File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_bytes_to_packets.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_fpga_only_master_timing_adt.sv Info (12023): Found entity 1: soc_system_fpga_only_master_timing_adt File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_fpga_only_master_timing_adt.sv Line: 60 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_jtag_interface.v Info (12023): Found entity 1: altera_avalon_st_jtag_interface File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_jtag_interface.v Line: 20 Info (12021): Found 3 design units, including 3 entities, in source file soc_system/synthesis/submodules/altera_jtag_dc_streaming.v Info (12023): Found entity 1: altera_jtag_control_signal_crosser File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_jtag_dc_streaming.v Line: 30 Info (12023): Found entity 2: altera_jtag_src_crosser File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_jtag_dc_streaming.v Line: 72 Info (12023): Found entity 3: altera_jtag_dc_streaming File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_jtag_dc_streaming.v Line: 135 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_jtag_sld_node.v Info (12023): Found entity 1: altera_jtag_sld_node File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_jtag_sld_node.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_jtag_streaming.v Info (12023): Found entity 1: altera_jtag_streaming File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_jtag_streaming.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_idle_remover.v Info (12023): Found entity 1: altera_avalon_st_idle_remover File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_idle_remover.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_idle_inserter.v Info (12023): Found entity 1: altera_avalon_st_idle_inserter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/altera_avalon_st_idle_inserter.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_dipsw_pio.v Info (12023): Found entity 1: soc_system_dipsw_pio File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_dipsw_pio.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_button_pio.v Info (12023): Found entity 1: soc_system_button_pio File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/soc_system_button_pio.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_vfr.v Info (12023): Found entity 1: alt_vipvfr131_vfr File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_vfr.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_vfr_controller.v Info (12023): Found entity 1: alt_vipvfr131_vfr_controller File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_vfr_controller.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_vfr_control_packet_encoder.v Info (12023): Found entity 1: alt_vipvfr131_vfr_control_packet_encoder File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_vfr_control_packet_encoder.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_prc.v Info (12023): Found entity 1: alt_vipvfr131_prc File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_prc.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_prc_core.v Info (12023): Found entity 1: alt_vipvfr131_prc_core File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_prc_core.v Line: 3 Warning (10238): Verilog Module Declaration warning at alt_vipvfr131_prc_read_master.v(47): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "alt_vipvfr131_prc_read_master" File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_prc_read_master.v Line: 47 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_prc_read_master.v Info (12023): Found entity 1: alt_vipvfr131_prc_read_master File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_prc_read_master.v Line: 1 Info (12021): Found 2 design units, including 0 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_package.vhd Info (12022): Found design unit 1: alt_vipvfr131_common_package (soc_system) File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_package.vhd Line: 18 Info (12022): Found design unit 2: alt_vipvfr131_common_package-body File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_package.vhd Line: 3661 Info (12021): Found 2 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd Info (12022): Found design unit 1: alt_vipvfr131_common_avalon_mm_bursting_master_fifo-rtl File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd Line: 95 Info (12023): Found entity 1: alt_vipvfr131_common_avalon_mm_bursting_master_fifo File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_master.v Info (12023): Found entity 1: alt_vipvfr131_common_avalon_mm_master File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_master.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_unpack_data.v Info (12023): Found entity 1: alt_vipvfr131_common_unpack_data File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_unpack_data.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_slave.v Info (12023): Found entity 1: alt_vipvfr131_common_avalon_mm_slave File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_slave.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_stream_output.v Info (12023): Found entity 1: alt_vipvfr131_common_stream_output File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_stream_output.v Line: 1 Info (12021): Found 2 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_pulling_width_adapter.vhd Info (12022): Found design unit 1: alt_vipvfr131_common_pulling_width_adapter-rtl File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_pulling_width_adapter.vhd Line: 39 Info (12023): Found entity 1: alt_vipvfr131_common_pulling_width_adapter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_pulling_width_adapter.vhd Line: 7 Info (12021): Found 2 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_general_fifo.vhd Info (12022): Found design unit 1: alt_vipvfr131_common_general_fifo-rtl File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_general_fifo.vhd Line: 56 Info (12023): Found entity 1: alt_vipvfr131_common_general_fifo File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_general_fifo.vhd Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_fifo_usedw_calculator.vhd Info (12022): Found design unit 1: alt_vipvfr131_common_fifo_usedw_calculator-rtl File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_fifo_usedw_calculator.vhd Line: 52 Info (12023): Found entity 1: alt_vipvfr131_common_fifo_usedw_calculator File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_fifo_usedw_calculator.vhd Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_gray_clock_crosser.vhd Info (12022): Found design unit 1: alt_vipvfr131_common_gray_clock_crosser-rtl File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_gray_clock_crosser.vhd Line: 39 Info (12023): Found entity 1: alt_vipvfr131_common_gray_clock_crosser File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_gray_clock_crosser.vhd Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_std_logic_vector_delay.vhd Info (12022): Found design unit 1: alt_vipvfr131_common_std_logic_vector_delay-rtl File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_std_logic_vector_delay.vhd Line: 38 Info (12023): Found entity 1: alt_vipvfr131_common_std_logic_vector_delay File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_std_logic_vector_delay.vhd Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_one_bit_delay.vhd Info (12022): Found design unit 1: alt_vipvfr131_common_one_bit_delay-rtl File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_one_bit_delay.vhd Line: 36 Info (12023): Found entity 1: alt_vipvfr131_common_one_bit_delay File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_one_bit_delay.vhd Line: 18 Info (12021): Found 2 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_logic_fifo.vhd Info (12022): Found design unit 1: alt_vipvfr131_common_logic_fifo-rtl File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_logic_fifo.vhd Line: 52 Info (12023): Found entity 1: alt_vipvfr131_common_logic_fifo File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_logic_fifo.vhd Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipvfr131_common_ram_fifo.vhd Info (12022): Found design unit 1: alt_vipvfr131_common_ram_fifo-rtl File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_ram_fifo.vhd Line: 55 Info (12023): Found entity 1: alt_vipvfr131_common_ram_fifo File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_common_ram_fifo.vhd Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_IS2Vid.sv Info (12023): Found entity 1: alt_vipitc131_IS2Vid File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_IS2Vid.sv Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v Info (12023): Found entity 1: alt_vipitc131_IS2Vid_sync_compare File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v Line: 5 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v Info (12023): Found entity 1: alt_vipitc131_IS2Vid_calculate_mode File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_control.v Info (12023): Found entity 1: alt_vipitc131_IS2Vid_control File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_control.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv Info (12023): Found entity 1: alt_vipitc131_IS2Vid_mode_banks File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v Info (12023): Found entity 1: alt_vipitc131_IS2Vid_statemachine File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_common_fifo.v Info (12023): Found entity 1: alt_vipitc131_common_fifo File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_common_fifo.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_common_generic_count.v Info (12023): Found entity 1: alt_vipitc131_common_generic_count File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_common_generic_count.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_common_to_binary.v Info (12023): Found entity 1: alt_vipitc131_common_to_binary File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_common_to_binary.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_common_sync.v Info (12023): Found entity 1: alt_vipitc131_common_sync File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_common_sync.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_common_trigger_sync.v Info (12023): Found entity 1: alt_vipitc131_common_trigger_sync File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_common_trigger_sync.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_common_sync_generation.v Info (12023): Found entity 1: alt_vipitc131_common_sync_generation File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_common_sync_generation.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_common_frame_counter.v Info (12023): Found entity 1: alt_vipitc131_common_frame_counter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_common_frame_counter.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/alt_vipitc131_common_sample_counter.v Info (12023): Found entity 1: alt_vipitc131_common_sample_counter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipitc131_common_sample_counter.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/interrupt_latency_counter.v Info (12023): Found entity 1: interrupt_latency_counter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/interrupt_latency_counter.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/irq_detector.v Info (12023): Found entity 1: irq_detector File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/irq_detector.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/state_machine_counter.v Info (12023): Found entity 1: state_machine_counter File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/state_machine_counter.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file DE10_Nano_FB_Cramps.sv Info (12023): Found entity 1: DE10_Nano_FB_Cramps File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.sv Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/cv-ip/ADC_LTC2308_FIFO/adc_data_fifo.v Info (12023): Found entity 1: adc_data_fifo File: /work/HW/cv-ip/ADC_LTC2308_FIFO/adc_data_fifo.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/adc_ltc2308.v Info (12023): Found entity 1: adc_ltc2308 File: /work/HW/QuartusProjects/Common/adc_ltc2308.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/adc_ltc2308_fifo.sv Info (12023): Found entity 1: adc_ltc2308_fifo File: /work/HW/QuartusProjects/Common/adc_ltc2308_fifo.sv Line: 7 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/bidir_io.sv Info (12023): Found entity 1: bidir_io File: /work/HW/QuartusProjects/Common/bidir_io.sv Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/gpio_adr_decoder_reg.sv Info (12023): Found entity 1: gpio_adr_decoder_reg File: /work/HW/QuartusProjects/Common/gpio_adr_decoder_reg.sv Line: 44 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/I2C_Controller.v Info (12023): Found entity 1: I2C_Controller File: /work/HW/QuartusProjects/Common/I2C_Controller.v Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/I2C_HDMI_Config.v Info (12023): Found entity 1: I2C_HDMI_Config File: /work/HW/QuartusProjects/Common/I2C_HDMI_Config.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file /work/HW/QuartusProjects/Common/I2C_WRITE_WDATA.v Info (12023): Found entity 1: I2C_WRITE_WDATA File: /work/HW/QuartusProjects/Common/I2C_WRITE_WDATA.v Line: 1 Error (10482): VHDL error at PIN_st_fpga_soc_dc1f.vhd(80): object "ClockMedTag" is used but not declared File: /work/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_st_fpga_soc_dc1f.vhd Line: 80 Warning (10236): Verilog HDL Implicit Net warning at top_io_modules.sv(39): created implicit net for "hps_reset_req" File: /work/HW/QuartusProjects/Common/top_io_modules.sv Line: 39 Warning (10236): Verilog HDL Implicit Net warning at altera_edge_detector.v(21): created implicit net for "reset_qual_n" File: /work/HW/cv-ip/edge_detect/altera_edge_detector.v Line: 21 Warning (10236): Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for "pll_dr_clk" File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/hps_sdram_pll.sv Line: 168 Warning (10236): Verilog HDL Implicit Net warning at alt_vipvfr131_prc.v(142): created implicit net for "master_clock" File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_prc.v Line: 142 Warning (10236): Verilog HDL Implicit Net warning at alt_vipvfr131_prc.v(143): created implicit net for "master_reset" File: /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system/synthesis/submodules/alt_vipvfr131_prc.v Line: 143 Info (144001): Generated suppressed messages file /work/HW/QuartusProjects/DE10_Nano_FB_Cramps/output_files/DE10_Nano_FB_Cramps.map.smsg Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 8 warnings Error: Peak virtual memory: 1319 megabytes Error: Processing ended: Fri Jul 26 21:57:21 2019 Error: Elapsed time: 00:03:20 Error: Total CPU time (on all processors): 00:03:39 Makefile:210: recipe for target 'stamp/quartus_pin_assignments.stamp' failed make: *** [stamp/quartus_pin_assignments.stamp] Error 3 builder@44885c2907a7:/work/HW/QuartusProjects/DE10_Nano_FB_Cramps$ Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed!
