The pinfile examples I come across are as you say using the ClockLowTag,
looking at the sserialwa.vhd file in mksocfpga "clockmed" is referenced all
over the place, but I'm not the guy to be trying to figure out what's what
in any type of code unless it's hal or it's obvious. I DL'd the 5i25 source
zip from mesanet (I assume this started with the 5i25 sources), i diff'd
the idromconst.vhd's and the only SS related changes I see are the
additions of a "SSerialNTXEn0Pin" pintype. sserialwa.vhd seems to have
changed this
port map(
addra => regaddr,
addrb => ioradd(log2(InterfaceRegs) +1 downto 2),
clk => clk,
dina => ibus,
-- douta =>
doutb => libus32_3,
wea => hloadregs3
);
makeUARTRs: for i in 0 to Ports -1 generate
auarrx: entity work.uartr8
port map (
clk => clkmed,
ibus => mobus,
obus => iodata,
popfifo => readrxdata(i),
loadbitratel => loadrxbitratel(i),
loadbitratem => loadrxbitratem(i),
loadbitrateh => loadrxbitrateh(i),
readbitratel => '0',
readbitratem => '0',
readbitrateh => '0',
clrfifo => clearrxfifo(i),
readfifocount => readrxfifocount(i),
loadmode => loadrxmode(i),
readmode => readrxmode(i),
fifohasdata => rxfifohasdata(i),
rxmask => drven(i), -- for half duplex rx mask
rxdata => rxdata(i)
);
end generate;
to this (generic map)
port map(
addra => regaddr,
addrb => ioradd(log2(InterfaceRegs) +1 downto 2),
clk => clk,
dina => ibus,
-- douta =>
doutb => libus32_3,
wea => hloadregs3
);
makeUARTRs: for i in 0 to Ports -1 generate
auarrx: entity work.uartr8
generic map (
Clock => BaseClock
)
port map (
clk => clkmed,
ibus => mobus,
obus => iodata,
popfifo => readrxdata(i),
loadbitratel => loadrxbitratel(i),
loadbitratem => loadrxbitratem(i),
loadbitrateh => loadrxbitrateh(i),
readbitratel => '0',
readbitratem => '0',
readbitrateh => '0',
clrfifo => clearrxfifo(i),
readfifocount => readrxfifocount(i),
loadmode => loadrxmode(i),
readmode => readrxmode(i),
loadfilter => loadrxfilter(i),
fifohasdata => rxfifohasdata(i),
rxmask => drven(i), -- for half duplex rx mask
rxdata => rxdata(i)
);
end generate;
Other than that it's just some lines for filters and the addition of the
ntxenable stuff. I noticed MKSOCFPGA is missing sserialremote.vhd's. Other
than that I have no idea.
mesa sources <http://www.mesanet.com/software/parallel/>
On Friday, July 26, 2019 at 6:42:04 PM UTC-4, Charles Steinkuehler wrote:
>
> On 7/26/2019 5:08 PM, justin White wrote:
> >
> >>
> >> Ok well I cannot cope with the stress of starting up my workstation
> this
> >> week and I didn't catch any quartus log in your former post?
> >> MiB
> >>
> >
> > Lol, rough week eh?
> >
> > Post directly after has the quartus snippet with the error, re-ran
> it,full
> > terminal print attached. Again, only happens if in pinfile:
> >
> > (SSerialTag, x"00", ClockMedTag, x"01", SSerialCommandAddr&PadT,
>
> > SSerialNumRegs, x"10", SSerialMPBitMask),
> >
> > if:
> >
> > (SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT,
>
> > SSerialNumRegs, x"10", SSerialMPBitMask),
> >
> > it will build fine, but SS does not work.
>
> The problem is it doesn't look like ClockMedTag is declared in the
> IDROMConst.vhd file, just ClockLowTag and ClockHighTag:
>
>
> https://github.com/machinekit/mksocfpga/blob/master/HW/hm2/config/IDROMConst.vhd#L402-L404
>
>
> ...causing the Quartus error:
>
> Error (10482): VHDL error at PIN_st_fpga_soc_dc1f.vhd(80): object
> "ClockMedTag" is used but not declared File:
> /work/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_st_fpga_soc_dc1f.vhd Line: 80
>
>
> The configs I have that use SSerial are using ClockLowTag and IIRC
> they worked OK. You might check and see if Peter has updated the
> IDROMConst.vhd file, the one in the Machinekit repo might be fairly
> dated. But I think it ought to work when using ClockLowTag, so there
> may be some other weirdness going on.
>
> --
> Charles Steinkuehler
> cha...@steinkuehler.net <javascript:>
>
--
website: http://www.machinekit.io blog: http://blog.machinekit.io github:
https://github.com/machinekit
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