>I was hoping that it wasn't the case that the FSBL was the problem. I have >indeed seen that exact blog post. > >What seems to be troubling is that the FSBL I'm using is generated using 17.2 >with Xilinx SDK - so I'm surprised this wouldn't just work out of the box. Do >you know what / where we can look in FSBL configuration (maybe in the BSP >configuration) that might be the issue?
There is PCW- PS configuration wizard in Vivado where you configure MIO/MDIO and enable ENET0/ENET1 based on your board configuration. If these settings are incorrect then the fsbl you build against would fail to properly initialize PS ENET system. This is all I know. Check the zynqmp TRM for more details. -syed -- _______________________________________________ meta-xilinx mailing list meta-xilinx@yoctoproject.org https://lists.yoctoproject.org/listinfo/meta-xilinx