Hi Giordon,
I think the pins to interact with the Ethernet PHY are not in the GEM
configuration, but in the MDIO.
So in the second screenshot you should look for the MDIO signals (I
guess under "Low Speed").
They should be on MIO 76 and 77 based on the TRM.
Regards,
Matteo
On 06/12/2017 17:23, Giordon Stark wrote:
Hi Syed,
I'm using the machine defined here:
https://github.com/kratsg/meta-l1calo/ (https://github.com/kratsg/meta-l1calo/blob/master/conf/machine/gfex-prototype3.conf).
However this is the current output I'm seeing:
https://gist.github.com/kratsg/9100572d578900cd251c40f1f651d161 where
it's still unable to see the ETH. I have also attached two screenshots
of what this looks like for us in our block design:
https://www.dropbox.com/s/c0xz9t6jm5jds7d/Screenshot%202017-12-06%2011.22.51.png?dl=0
https://www.dropbox.com/s/dzesg3s88axgyao/Screenshot%202017-12-06%2011.23.07.png?dl=0
Thanks a lot. Let me know what we've missed,
Giordon
On Thu, Nov 23, 2017 at 8:56 AM Tang, Shaochun <st...@bnl.gov
<mailto:st...@bnl.gov>> wrote:
Thanks Syed.
Actually, we can find the Ethernet and let it work with the SDK
example. So I think the hardware should be ok, but I am not sure
what the difference between FSBL and SDK example.
Have a nice Thanksgiving.
Best Regards
Shaochun Tang
*From: *Syed Syed <mailto:sy...@xilinx.com>
*Sent: *Thursday, November 23, 2017 7:26 AM
*To: *Giordon Stark <mailto:kra...@gmail.com>
*Cc: *meta-xilinx@yoctoproject.org
<mailto:meta-xilinx@yoctoproject.org>; Tang, Shaochun
<mailto:st...@bnl.gov>
*Subject: *RE: [meta-xilinx] U-boot not recognizing correct
Ethernet PHY ADDR
>I was hoping that it wasn't the case that the FSBL was the
problem. I have indeed seen that exact blog post.
>
>What seems to be troubling is that the FSBL I'm using is
generated using 17.2 with Xilinx SDK - so I'm surprised this
wouldn't just work out of the box. Do you know what / where we can
look in FSBL configuration (maybe in the BSP configuration) that
might be the issue?
There is PCW- PS configuration wizard in Vivado where you
configure MIO/MDIO and enable ENET0/ENET1 based on your board
configuration. If these settings are incorrect then the fsbl you
build against would fail to properly initialize PS ENET system.
This is all I know.
Check the zynqmp TRM for more details.
-syed
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