Hi,

the "new" Jason [I guess we need to find some terminology here :)]
just made aware of the following problem on the new CUDA box which is
a K10:

mpir  ./configure


checking build system type... i486-unknown-linux-gnu
checking host system type... i486-unknown-linux-gnu

^^^^^^ oops

checking for a BSD-compatible install... /usr/bin/install -c
checking whether build environment is sane... yes
checking for gawk... no
checking for mawk... mawk
checking whether make sets $(MAKE)... yes
checking whether to enable maintainer-specific portions of
Makefiles... no
checking ABI=32
checking compiler gcc -m32 -O2 -fomit-frame-pointer ... no
checking compiler gcc -O2 -fomit-frame-pointer ... yes
checking compiler gcc -O2 -fomit-frame-pointer has sizeof(long)==4...
no
checking compiler icc -no-gcc ... no
checking whether cc is gcc... yes
checking compiler cc -m32 -O2 -fomit-frame-pointer ... no
checking compiler cc -O2 -fomit-frame-pointer ... yes
checking compiler cc -O2 -fomit-frame-pointer has sizeof(long)==4...
no
configure: error: could not find a working compiler, see config.log
for
details

cc fails in this case since there is no 32 bit userspace, but that is
not the issue here. Since all the usual suspects have accounts on that
box I am sure this can quickly be fixed.

cpuinfo says:

processor       : 3
vendor_id       : AuthenticAMD
cpu family      : 16
model           : 2
model name      : AMD Phenom(tm) 9950 Quad-Core Processor
stepping        : 3
cpu MHz         : 2611.818
cache size      : 512 KB
physical id     : 0
siblings        : 4
core id         : 3
cpu cores       : 4
fpu             : yes
fpu_exception   : yes
cpuid level     : 5
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext
fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc rep_good pni
cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a
misalignsse 3dnowprefetch osvw ibs
bogomips        : 5223.71
TLB size        : 1024 4K pages
clflush size    : 64
cache_alignment : 64
address sizes   : 48 bits physical, 48 bits virtual
power management: ts ttp tm stc 100mhzsteps hwpstate


Ticket anyone?

Cheers,

Michael



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