The Core2 assembler code for mpn_add_n (and mpn_sub_n?) uses the lahf and sahf op codes to save and restore the carry flag from rax but my Intel documents say that this is only valid in 64 bit mode for some but not all Intel 64-bit processors. To quote:
"It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF [bit 0] = 1" I am hence wondering if this is safe? As far as I can see, since rax isn't used in the routine except at the very end, the instructions: save carry to a: sbb rax, rax load carry from a: add rax, rax would do just as well. But I don't know about speed differences here. Brian --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "mpir-devel" group. To post to this group, send email to mpir-devel@googlegroups.com To unsubscribe from this group, send email to mpir-devel+unsubscr...@googlegroups.com For more options, visit this group at http://groups.google.com/group/mpir-devel?hl=en -~----------~----~----~----~------~----~------~--~---
