On Mar 14, 4:45 pm, Jason Moxham <ja...@njkfrudils.plus.com> wrote:
> I pretty sure all core2 cpus have lahf,sahf , it's just some Pentium D dont
> have it . You can test the lahf_lm feature bit in cpuid to see if it's got it
>
> On Saturday 14 March 2009 16:40:10 Cactus wrote:
>
> > The Core2 assembler code for mpn_add_n (and mpn_sub_n?) uses the lahf
> > and sahf op codes to save and restore the carry flag from rax but my
> > Intel documents say that this is only valid in 64 bit mode for some
> > but not all Intel 64-bit processors. To quote:
>
> > "It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF
> > [bit 0] = 1"
>
> > I am hence wondering if this is safe?
>
> > As far as I can see, since rax isn't used in the routine except at the
> > very end, the instructions:
>
> > save carry to a: sbb rax, rax
> > load carry from a: add rax, rax
>
> > would do just as well.
>
> > But I don't know about speed differences here.
My Intel manuals definitely say that not all 64-bit processors have
these instructions.
And I don't know how we are ensuring that MPIR doesn't end up on any
systems without these instructions.
I don't know what the speed comparison and instruction sequencing
issues would be, but doesn't it make sense to use something that we
know always works?
Brian
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