On 6/6/06, Jack Carroll <[EMAIL PROTECTED]> wrote:
On Tue, Jun 06, 2006 at 06:51:35AM -0400, Timothy Miller wrote: > The fact that the last address bit and > the first read data bit are on different edges of the same clock pulse > makes it a bit tricky.But that's the nature of SPI, at least in some modes.
Yeah. What I really should say is that in my first attempt, it was too difficult for me to track down a bug related to this. I guess it was tricky for ME. :) As it turns out, doing it this way makes it easier to design the logic, because you can do everything in the controller on the same clock edge. (You put SI out on the rising edge, which the SPI samples on the falling edge. The SPI puts data out on the falling edge, which you sample on the rising edge.) _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
