>> What might (should?) work in my particular case is, since I'm starting from
>> EL2:
>>
>> - Modify SPSR_EL2, setting bit 4 = 1 and bits 3:0 to some valid aarch32 mode
>> (0x3 - svc mode)
>> - set ELR_EL2 to a memory location with valid ARM code
>> - "ERET"
>
> OK it "somewhat" worked. I get to Aarch32 state, but not at the place where I
> wanted to be but at 0x10, in ABT mode.
I think you also need to set/clear the HCR.RW (bit 31) which controls the EL1
state: 32 or 64bit
In summary:
SCR_EL3.RW (bit 10) controls EL2 - register width (32/64bit)
HCR_EL2.RW (bit 31) controls EL1/EL0 register with (32/64bit)
More interestingly - HCR is 64bits in 64bit state
But - is two different 32bit registers in 32bit state
I believe EL0 - 32/64bit is controlled via the “mode-field” in the PSW
register (it’s been a while…)
Also - the SPSR register mode must match the corresponding RW bit in
the SCR or HCR register
My earlier point was this (and I want to say it again, because I think it every
important)
There are so many differences between arm32 & aarch64 - yes there are a *FEW*
things that are identical or could be reused
However - stepping back and looking at the big picture - interweaving those few
things with “mode checks” will cause more problems and crazy code flow paths
then they are worth. So much so that aarch64 - support in its entirety should
be a standalone and not rely upon the “common arm” stuff.
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