On 01.08.2018 19:13, Christopher Head wrote:
Hello!
I was wondering about how OpenOCD was meant to interoperate with CPU caches.
Right now, the Cortex M target has no cache management at all, which means
that, on devices whose debug buses connect directly to RAM, any memory access
through OpenOCD shows what’s in RAM, which may not be the same as what’s in
d-cache.
I had just always assumed that was intended behaviour until just now, when I
saw a patch posted regarding cleaning caches on Cortex-A, presumably so that
memory accesses would see what was most recently written by the CPU.
What is OpenOCD’s policy regarding cache coherence around debug accesses to
memory? If the policy is that they should be coherent, then I could probably
provide a patch making this happen for Cortex M at some point.
Hi Christopher,
If you mean Cortex-M7 DCache, please try
set CSW_HPROT3_CACHEABLE [expr 1 << 27]
samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
and MEM-AP access goes through DCache.
Of course, some fancy ui wold be nice. Might be set by default in
target.cfg or so.
The only problem on Cortex-M7 is missing ICache flush after setting a
RAM breakpoint.
Not critical as you can use hw breakpoints only.
Tom
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