On Mittwoch, 1. August 2018 19:13:58 CEST Christopher Head wrote: > Hello! > I was wondering about how OpenOCD was meant to interoperate with CPU caches. > Right now, the Cortex M target has no cache management at all, which means > that, on devices whose debug buses connect directly to RAM, any memory > access through OpenOCD shows what’s in RAM, which may not be the same as > what’s in d-cache. > > I had just always assumed that was intended behaviour until just now, when I > saw a patch posted regarding cleaning caches on Cortex-A, presumably so > that memory accesses would see what was most recently written by the CPU. > > What is OpenOCD’s policy regarding cache coherence around debug accesses to > memory? If the policy is that they should be coherent, then I could > probably provide a patch making this happen for Cortex M at some point.
The policy is "make gdb happy", which has no idea about cache coherence and cannot deal with it. Therefore, openocd must do everything required to present a coherent memory view to gdb. BR, Matthias ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list OpenOCD-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openocd-devel
