On August 1, 2018 12:15:18 PM PDT, Tomas Vanek via OpenOCD-devel <openocd-devel@lists.sourceforge.net> wrote: >and MEM-AP access goes through DCache. >Of course, some fancy ui wold be nice. Might be set by default in >target.cfg or so.
Yes, that’s perfect, thanks! I’m a little curious why it’s not the default? It looks like there was a discussion a while ago on this issue, but no resolution regarding defaults. It also looks like this is only quite recently possible, since 0.10.0 only accepted 0 or 1 as parameters to the apcsw command (at least so says the manual). Is it just that it needs to be set on a per-MCU-type basis (since the meaning of those CSW bits depends on the debug bus type) and nobody has done it yet for all the individual target config files? >The only problem on Cortex-M7 is missing ICache flush after setting a >RAM breakpoint. >Not critical as you can use hw breakpoints only. Not an issue at all for me, and probably many others, since my code is in Flash. -- Christopher Head
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