On 03.08.2018 2:28, Christopher Head wrote:
On August 1, 2018 12:15:18 PM PDT, Tomas Vanek via OpenOCD-devel
<openocd-devel@lists.sourceforge.net> wrote:
and MEM-AP access goes through DCache.
Of course, some fancy ui wold be nice. Might be set by default in
target.cfg or so.
Yes, that’s perfect, thanks! I’m a little curious why it’s not the default? It
looks like there was a discussion a while ago on this issue, but no resolution
regarding defaults. It also looks like this is only quite recently possible,
since 0.10.0 only accepted 0 or 1 as parameters to the apcsw command (at least
so says the manual). Is it just that it needs to be set on a per-MCU-type basis
(since the meaning of those CSW bits depends on the debug bus type) and nobody
has done it yet for all the individual target config files?
I fully agree the "cacheable" CSW bit should be set by default for all
Cortex-M7 based devices.
And yes, bitwise setting of CSW was merged 4 months ago (#4431).
A proper initial CSW setting using apcsw command would also need
Antonio's recent #4624 or hook examine-end event.
Or probably the simplest solution: hard-code the setting to
cortex_m_examine() after CPU type is detected?
It might be possible to set the bit for any Cortex-M CPU without making
any harm - it should be verified.
As usually feel free to propose a change.
Tom
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