Tony,
Thanks for confirming my suspicion, the only reason I mentioned FPGA
was because they were specifically mentioning that it was an FPGA design. So I
thought it could just possibly be a specific feature to that module.
Looks sweet, I can see where it could be a bit frustrating under
certain conditions but I guess the ease under other conditions balances it out.
Sincerely,
Brad Velander
Senior PCB Designer
Northern Airborne Technology
#14 - 1925 Kirschner Road,
Kelowna, BC, V1Y 4N7.
tel (250) 763-2329 ext. 225
fax (250) 762-3374
-----Original Message-----
From: Tony Karavidas [mailto:[EMAIL PROTECTED]
Sent: Wednesday, January 11, 2006 10:20 PM
To: 'Protel EDA Discussion List'
Subject: Re: [PEDA] 6.0 ? it is here
> magically a sheet input symbol with the correct symbol naming appears
That is magic. It's a new feature called "Place Sheet Entries automatically"
and when you draw a wire up to a sub sheet, a sheet entry will be added and
assume the name of the net. It also assumes the direction of the signal if
it can determine it from somewhere else such as another sheet entry when
going from sheet to sheet.
This has nothing to do with FPGAs.
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