This is a nagging problem I haven't been able to get around yet, and I'm 
sure that someone else has run into the same thing ...  I have a couple of 
nice pcb logo footprints done that go on our boards, originally built from 
one of the bmp-2-pcb programs, then manually tweaked up.  They mainly 
consist of a bunch of TINY (1 and 2mil) tracks and arcs, some judicious use 
of small keepout tracks and a keepout border around the logo.  Looks pretty 
good.

The problem is with Design Rule Check.  It always complains about the width 
and proximity of the tiny tracks that make up the logo.  There doesn't seem 
to be any way to assign them to a given net, so I could use a Design Rule 
for that specific net.  In the Library editor for a track, there's a 
pulldown for the net, but the only selection is "No Net" and I can't 
override it.

In the PCB editor you can't get to the individual tracks of the logo - it's 
just the monolithic part.  I can partly get around it ...  Create a new net 
for the logo, then explode the component to primitives  Select all the 
connected copper and assign to the new net, and use that for a width rule. 
That works, but it still hangs up on clearance constraints.  Also, worse, 
the component is now gone, and next time an update it done, the synchronizer 
wants to put the logo component back on.

I've tried creating pads for all the copper runs in the footprint.  Then use 
a schematic part with the right number of pins, and assign nets that way. 
That works - the pads have the right net, but all the tracks that make up 
the logo don't, and don't seem to want to take it.

The goes with the "using top/bottom layer tracks for a footprint" problem 
I've heard and experienced ...


-- 
Dean Carpenter
deano at areyes com
94TT :) 

 
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