The ICC_HAPR_EL1 register reported the current running priority of the CPU. However this can be easily calculated by reading the APR register, so it has been removed in the newly released A.a version of the GICv5 spec (IHI 111701).
Remove QEMU's implementation of this register. (This is OK for us to do without warning because our GICv5 support is listed as "experimental"; we anticipated that this kind of spec change might happen.) Signed-off-by: Peter Maydell <[email protected]> --- target/arm/tcg/gicv5-cpuif.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 1aa4bde799..a868adca66 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -511,15 +511,6 @@ static void gic_icc_apr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri) } } -static uint64_t gic_icc_hapr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* - * ICC_HAPR_EL1 reports the current running priority, which can be - * calculated from the APR register. - */ - return gic_running_prio(env, gicv5_current_phys_domain(env)); -} - /* ICC_CR0_EL1 is also banked */ static uint64_t gic_icc_cr0_el1_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -928,11 +919,6 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .writefn = gic_icc_pcr_el1_write, .resetfn = gic_icc_pcr_el1_reset, }, - { .name = "ICC_HAPR_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 3, - .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, - .readfn = gic_icc_hapr_el1_read, .raw_writefn = arm_cp_write_ignore, - }, }; void define_gicv5_cpuif_regs(ARMCPU *cpu) -- 2.43.0
