The GICv5 system registers are all tagged with ARM_CP_NO_RAW, because
we don't want them to use the standard mechanisms for migration or
KVM state synchronization. (GICv5 handling of both migration and KVM
support is a "will be implemented later" feature.) We missed this tag
on the ICC_PPI_PRIORITYR<n>_EL1 registers; add it.
Fixes: ef540c1d301 ("target/arm: GICv5 cpuif: Implement PPI priority registers")
Signed-off-by: Peter Maydell <[email protected]>
---
target/arm/tcg/gicv5-cpuif.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c
index 09c3fdda61..1aa4bde799 100644
--- a/target/arm/tcg/gicv5-cpuif.c
+++ b/target/arm/tcg/gicv5-cpuif.c
@@ -950,7 +950,7 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu)
.name = name, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 12,
.crm = 14 + (i >> 3), .opc2 = i & 7,
- .access = PL1_RW, .type = ARM_CP_IO,
+ .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,
.fieldoffset = offsetof(CPUARMState,
gicv5_cpuif.ppi_priority[i]),
.writefn = gic_ppi_priority_write, .raw_writefn = raw_write,
};
--
2.43.0
