On 15/6/26 12:50, Peter Maydell wrote:
The GICv5 system registers are all tagged with ARM_CP_NO_RAW, because we don't want them to use the standard mechanisms for migration or KVM state synchronization. (GICv5 handling of both migration and KVM support is a "will be implemented later" feature.) We missed this tag on the ICC_PPI_PRIORITYR<n>_EL1 registers; add it.Fixes: ef540c1d301 ("target/arm: GICv5 cpuif: Implement PPI priority registers") Signed-off-by: Peter Maydell <[email protected]> --- target/arm/tcg/gicv5-cpuif.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
