The GICv5PendingIrq struct representation of "there is no pending interrupt" sets the prio field to PRIO_IDLE, and generally to avoid confusion we also set the intid to 0. We want to return this value or initialize some variable to it in several places in the GICv5 implementation, and the support for the virtual interrupt domain introduces more.
Define a convenience macro for this special-case struct value, and use it instead of opencoding either the structure initializer or explicit assignment to the two fields. Signed-off-by: Peter Maydell <[email protected]> --- hw/intc/arm_gicv5.c | 6 ++---- include/hw/intc/arm_gicv5_types.h | 4 ++++ target/arm/tcg/gicv5-cpuif.c | 7 +++---- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 0fa3d6b601..08878193df 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -429,8 +429,7 @@ static void irs_recalc_hppi(GICv5 *s, GICv5Domain domain, uint32_t iaffid) ARMCPU *cpu = cpuidx >= 0 ? cs->cpus[cpuidx] : NULL; GICv5PendingIrq best; - best.intid = 0; - best.prio = PRIO_IDLE; + best = GICV5_PENDING_IRQ_NONE; if (!cpu) { /* Nothing happens for iaffids targeting nonexistent CPUs */ @@ -526,8 +525,7 @@ static void irs_recall_hppis(GICv5 *s, GICv5Domain domain) GICv5Common *cs = ARM_GICV5_COMMON(s); for (int i = 0; i < cs->num_cpus; i++) { - s->hppi[domain][i].intid = 0; - s->hppi[domain][i].prio = PRIO_IDLE; + s->hppi[domain][i] = GICV5_PENDING_IRQ_NONE; gicv5_forward_interrupt(cs->cpus[i], domain); } } diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_types.h index de4f78a149..851286b1b5 100644 --- a/include/hw/intc/arm_gicv5_types.h +++ b/include/hw/intc/arm_gicv5_types.h @@ -105,6 +105,10 @@ typedef struct GICv5PendingIrq { uint8_t prio; } GICv5PendingIrq; +/* A GICv5PendingIrq struct initializer for "no pending interrupt" */ +#define GICV5_PENDING_IRQ_NONE \ + ((GICv5PendingIrq) { .intid = 0, .prio = PRIO_IDLE }) + /* Fields in a generic 32-bit INTID, per R_TJPHS */ FIELD(INTID, ID, 0, 24) FIELD(INTID, TYPE, 29, 3) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index a868adca66..1cdd4103d0 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -144,7 +144,7 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5Domain domain) if (!(env->gicv5_cpuif.icc_cr0[domain] & R_ICC_CR0_EN_MASK)) { /* If cpuif is disabled there is no HPPI */ - return (GICv5PendingIrq) { .intid = 0, .prio = PRIO_IDLE }; + return GICV5_PENDING_IRQ_NONE; } irs_hppi = gicv5_get_hppi(gic, domain, env->gicv5_iaffid); @@ -168,7 +168,7 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5Domain domain) if (best.prio == PRIO_IDLE || best.prio > env->gicv5_cpuif.icc_pcr[domain] || best.prio >= gic_running_prio(env, domain)) { - return (GICv5PendingIrq) { .intid = 0, .prio = PRIO_IDLE }; + return GICV5_PENDING_IRQ_NONE; } return best; } @@ -258,8 +258,7 @@ static void gic_recalc_ppi_hppi(CPUARMState *env) * enabled, pending and not active. */ for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_hppi); i++) { - env->gicv5_cpuif.ppi_hppi[i].intid = 0; - env->gicv5_cpuif.ppi_hppi[i].prio = PRIO_IDLE; + env->gicv5_cpuif.ppi_hppi[i] = GICV5_PENDING_IRQ_NONE; }; for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_active); i++) { -- 2.43.0
