monitor_get_register at this moment has a TCG exclusive implementation for RISC-V, even though the callback is supposed to be arch independent. Until we address how KVM is going to implement it we need to filter it out in cpu.c.v
Same goes for get_phys_addr_debug - it has a TCG only implementation and KVM can't use it for now. It would also need to be filtered out, but since we're at it, let's convert it to the newer 'translate_for_debug' API too. Same restrictions apply. Suggested-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Daniel Henrique Barboza <[email protected]> --- target/riscv/cpu.c | 6 ++++-- target/riscv/cpu.h | 3 ++- target/riscv/monitor.c | 2 ++ target/riscv/tcg/cpu_helper.c | 14 ++++++++++---- 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e96bbeb60..319825882a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2669,11 +2669,13 @@ static int64_t riscv_get_arch_id(CPUState *cs) static const struct SysemuCPUOps riscv_sysemu_ops = { .has_work = riscv_cpu_has_work, - .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug, .write_elf64_note = riscv_cpu_write_elf64_note, .write_elf32_note = riscv_cpu_write_elf32_note, - .monitor_get_register = riscv_monitor_get_register_legacy, .legacy_vmsd = &vmstate_riscv_cpu, +#ifdef CONFIG_TCG + .translate_for_debug = riscv_cpu_translate_for_debug, + .monitor_get_register = riscv_monitor_get_register_legacy, +#endif }; #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f0c78c1474..70b8729bd7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -665,7 +665,8 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); -hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); +bool riscv_cpu_translate_for_debug(CPUState *cs, vaddr addr, + TranslateForDebugResult *result); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 3e89dcaf7c..7aacd1d89c 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -245,6 +245,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) mem_info_svxx(mon, env); } +#ifdef CONFIG_TCG static bool reg_is_ulong_integer(CPURISCVState *env, const char *name, target_ulong *val, bool is_gprh) { @@ -379,3 +380,4 @@ int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, return -EINVAL; } +#endif diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 59edcdd370..a893472c4e 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -1771,7 +1771,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, env->two_stage_indirect_lookup = two_stage_indirect; } -hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) +bool riscv_cpu_translate_for_debug(CPUState *cs, vaddr addr, + TranslateForDebugResult *result) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; @@ -1781,17 +1782,22 @@ hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, true, env->virt_enabled, true, false)) { - return -1; + return false; } if (env->virt_enabled) { if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 0, MMUIdx_U, false, true, true, false)) { - return -1; + return false; } } - return phys_addr; + *result = (TranslateForDebugResult) { + .physaddr = phys_addr, + .lg_page_size = TARGET_PAGE_BITS, + .attrs.debug = 1, + }; + return true; } void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, -- 2.43.0
