Hello, In this version we addressed the reviews from Phil and Richard from v1. No other changes were made.
Patches are based on alistair riscv-to-apply.next tree. It can also be fetched from this branch: https://gitlab.com/danielhb/qemu/-/tree/riscv_disabletcg_v2 Changes from v1: - patch 3: - changed pmp_needed return to "tcg_enabled() && cpu->cfg.pmp" - patch 5: - reworded commit msg; implemented translate_for_debug - patch 10: - added ifdefs around custom_csrs in cpu.h - patch 11: - inlined riscv_cpu_set_rnmi() - patch 16: - renamed riscv_set_irq() to riscv_accel_set_irq() - patch 18: - gated csr_register_qtest_callback() with qtest_enabled() - v1 link: https://lore.kernel.org/qemu-devel/[email protected]/ Daniel Henrique Barboza (22): target/riscv: move TCG only files to tcg subdir target/riscv/machine.c: do not migrate pmp state with kvm target/riscv: move pmp files to tcg subdir target/riscv: tidy up riscv_sysemu_ops target/riscv: move pmu.h to tcg subdir target/riscv: move debug.h to tcg subdir target/riscv: remove csr.h from kvm-cpu.c target/riscv: move csr.h to tcg subdir target/riscv: move custom_csrs logic to tcg-cpu.c target/riscv: move riscv_cpu_set_nmi() to tcg-cpu.c target/riscv: move valid_vm_* satp arrays to cpu.c target/riscv: move some irq helpers to cpu.c target/riscv: move riscv_cpu_claim_interrupts to cpu.c target/riscv/cpu.c: handle TCG bits of riscv_cpu_dump_state target/riscv: gate riscv_cpu_update_mip with tcg_enabled() target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold() hw/riscv/riscv_hart.c isolate tcg only bits target/riscv/gdbstub.c: isolate TCG only checks target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint target/riscv/tcg: remove unused riscv_cpu_get_geilen() target/riscv: move riscv_cpu_set_geilen() to riscv-imsic target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic Zephyr Li (2): target/riscv: Remove unused tcg/tcg.h include gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job .gitlab-ci.d/crossbuilds.yml | 8 + hw/intc/riscv_aclint.c | 8 + hw/intc/riscv_imsic.c | 24 ++ hw/riscv/fdt-common.c | 52 +++ hw/riscv/riscv_hart.c | 8 +- hw/riscv/virt.c | 1 - include/hw/riscv/fdt-common.h | 1 + target/riscv/cpu.c | 318 +++++++++++++++--- target/riscv/cpu.h | 24 +- target/riscv/gdbstub.c | 10 +- target/riscv/kvm/kvm-cpu.c | 1 - target/riscv/machine.c | 17 +- target/riscv/meson.build | 17 - target/riscv/monitor.c | 4 +- target/riscv/riscv-qmp-cmds.c | 2 +- target/riscv/{ => tcg}/bitmanip_helper.c | 0 target/riscv/{ => tcg}/cpu_helper.c | 253 +------------- target/riscv/{ => tcg}/crypto_helper.c | 0 target/riscv/{ => tcg}/csr.c | 45 +-- target/riscv/{ => tcg}/csr.h | 6 +- target/riscv/{ => tcg}/debug.c | 2 +- target/riscv/{ => tcg}/debug.h | 0 target/riscv/{ => tcg}/fpu_helper.c | 0 .../insn_trans/trans_privileged.c.inc | 0 .../{ => tcg}/insn_trans/trans_rva.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvb.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvbf16.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvd.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvf.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvh.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvi.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvk.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvm.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvv.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvvk.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvzabha.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvzacas.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvzalasr.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvzawrs.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvzce.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvzcmop.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvzfa.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvzfh.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvzicbo.c.inc | 0 .../insn_trans/trans_rvzicfiss.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvzicond.c.inc | 0 .../{ => tcg}/insn_trans/trans_rvzimop.c.inc | 0 .../{ => tcg}/insn_trans/trans_svinval.c.inc | 0 .../{ => tcg}/insn_trans/trans_xlrbr.c.inc | 0 .../{ => tcg}/insn_trans/trans_xmips.c.inc | 0 .../{ => tcg}/insn_trans/trans_xthead.c.inc | 0 .../insn_trans/trans_xventanacondops.c.inc | 0 .../{ => tcg}/insn_trans/trans_zilsd.c.inc | 0 target/riscv/{ => tcg}/m128_helper.c | 0 target/riscv/tcg/meson.build | 31 +- target/riscv/{ => tcg}/mips_csr.c | 2 +- target/riscv/{ => tcg}/op_helper.c | 2 +- target/riscv/{ => tcg}/pmp.c | 2 +- target/riscv/{ => tcg}/pmp.h | 0 target/riscv/{ => tcg}/pmu.c | 52 --- target/riscv/{ => tcg}/pmu.h | 1 - target/riscv/tcg/tcg-cpu.c | 30 +- target/riscv/{ => tcg}/th_csr.c | 2 +- target/riscv/{ => tcg}/translate.c | 0 target/riscv/{ => tcg}/vcrypto_helper.c | 0 target/riscv/{ => tcg}/vector_helper.c | 0 target/riscv/{ => tcg}/vector_internals.c | 0 target/riscv/{ => tcg}/vector_internals.h | 0 target/riscv/{ => tcg}/zce_helper.c | 0 target/riscv/time_helper.c | 33 +- 70 files changed, 515 insertions(+), 441 deletions(-) rename target/riscv/{ => tcg}/bitmanip_helper.c (100%) rename target/riscv/{ => tcg}/cpu_helper.c (91%) rename target/riscv/{ => tcg}/crypto_helper.c (100%) rename target/riscv/{ => tcg}/csr.c (99%) rename target/riscv/{ => tcg}/csr.h (96%) rename target/riscv/{ => tcg}/debug.c (99%) rename target/riscv/{ => tcg}/debug.h (100%) rename target/riscv/{ => tcg}/fpu_helper.c (100%) rename target/riscv/{ => tcg}/insn_trans/trans_privileged.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rva.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvb.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvbf16.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvd.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvf.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvh.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvi.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvk.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvm.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvv.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvvk.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzabha.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzacas.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzalasr.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzawrs.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzce.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzcmop.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzfa.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzfh.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzicbo.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzicfiss.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzicond.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_rvzimop.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_svinval.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_xlrbr.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_xmips.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_xthead.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_xventanacondops.c.inc (100%) rename target/riscv/{ => tcg}/insn_trans/trans_zilsd.c.inc (100%) rename target/riscv/{ => tcg}/m128_helper.c (100%) rename target/riscv/{ => tcg}/mips_csr.c (99%) rename target/riscv/{ => tcg}/op_helper.c (99%) rename target/riscv/{ => tcg}/pmp.c (99%) rename target/riscv/{ => tcg}/pmp.h (100%) rename target/riscv/{ => tcg}/pmu.c (86%) rename target/riscv/{ => tcg}/pmu.h (95%) rename target/riscv/{ => tcg}/th_csr.c (99%) rename target/riscv/{ => tcg}/translate.c (100%) rename target/riscv/{ => tcg}/vcrypto_helper.c (100%) rename target/riscv/{ => tcg}/vector_helper.c (100%) rename target/riscv/{ => tcg}/vector_internals.c (100%) rename target/riscv/{ => tcg}/vector_internals.h (100%) rename target/riscv/{ => tcg}/zce_helper.c (100%) -- 2.43.0
