riscv_pmu_generate_fdt_node() can be moved to fdt_common.c since it has no PMU TCG internals.
With this change we can remove pmu.h from 'virt.c', which is now becoming a tcg header since we're moving it to the tcg subdir. Signed-off-by: Daniel Henrique Barboza <[email protected]> --- hw/riscv/fdt-common.c | 52 +++++++++++++++++++++++++++++++++++ hw/riscv/virt.c | 1 - include/hw/riscv/fdt-common.h | 1 + target/riscv/tcg/pmu.c | 52 ----------------------------------- target/riscv/{ => tcg}/pmu.h | 1 - 5 files changed, 53 insertions(+), 54 deletions(-) rename target/riscv/{ => tcg}/pmu.h (95%) diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index e0e31af09b..aa143a618b 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -230,3 +230,55 @@ void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, } qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); } + +/* + * To keep it simple, any event can be mapped to any programmable counters in + * QEMU. The generic cycle & instruction count events can also be monitored + * using programmable counters. In that case, mcycle & minstret must continue + * to provide the correct value as well. Heterogeneous PMU per hart is not + * supported yet. Thus, number of counters are same across all harts. + */ +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) +{ + uint32_t fdt_event_ctr_map[15] = {}; + + /* + * The event encoding is specified in the SBI specification + * Event idx is a 20bits wide number encoded as follows: + * event_idx[19:16] = type + * event_idx[15:0] = code + * The code field in cache events are encoded as follows: + * event_idx.code[15:3] = cache_id + * event_idx.code[2:1] = op_id + * event_idx.code[0:0] = result_id + */ + + /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ + fdt_event_ctr_map[0] = cpu_to_be32(0x00000001); + fdt_event_ctr_map[1] = cpu_to_be32(0x00000001); + fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0); + + /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ + fdt_event_ctr_map[3] = cpu_to_be32(0x00000002); + fdt_event_ctr_map[4] = cpu_to_be32(0x00000002); + fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2); + + /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[6] = cpu_to_be32(0x00010019); + fdt_event_ctr_map[7] = cpu_to_be32(0x00010019); + fdt_event_ctr_map[8] = cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B); + fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B); + fdt_event_ctr_map[11] = cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[12] = cpu_to_be32(0x00010021); + fdt_event_ctr_map[13] = cpu_to_be32(0x00010021); + fdt_event_ctr_map[14] = cpu_to_be32(cmask); + + /* This a OpenSBI specific DT property documented in OpenSBI docs */ + qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", + fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 92c30a6f4c..a1cf8210be 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -30,7 +30,6 @@ #include "hw/char/serial-mm.h" #include "target/riscv/cpu.h" #include "hw/core/sysbus-fdt.h" -#include "target/riscv/pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/iommu.h" #include "hw/riscv/riscv-iommu-bits.h" diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 017278b611..1729a6abc6 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -35,4 +35,5 @@ void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, uint32_t addr_cells, uint32_t *plic_cells, uint32_t cells_size, uint32_t ndev_sources, bool numa_enabled, int socket); +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name); #endif diff --git a/target/riscv/tcg/pmu.c b/target/riscv/tcg/pmu.c index 3444400bd2..38ad2737e1 100644 --- a/target/riscv/tcg/pmu.c +++ b/target/riscv/tcg/pmu.c @@ -27,58 +27,6 @@ #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ -/* - * To keep it simple, any event can be mapped to any programmable counters in - * QEMU. The generic cycle & instruction count events can also be monitored - * using programmable counters. In that case, mcycle & minstret must continue - * to provide the correct value as well. Heterogeneous PMU per hart is not - * supported yet. Thus, number of counters are same across all harts. - */ -void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) -{ - uint32_t fdt_event_ctr_map[15] = {}; - - /* - * The event encoding is specified in the SBI specification - * Event idx is a 20bits wide number encoded as follows: - * event_idx[19:16] = type - * event_idx[15:0] = code - * The code field in cache events are encoded as follows: - * event_idx.code[15:3] = cache_id - * event_idx.code[2:1] = op_id - * event_idx.code[0:0] = result_id - */ - - /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ - fdt_event_ctr_map[0] = cpu_to_be32(0x00000001); - fdt_event_ctr_map[1] = cpu_to_be32(0x00000001); - fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0); - - /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ - fdt_event_ctr_map[3] = cpu_to_be32(0x00000002); - fdt_event_ctr_map[4] = cpu_to_be32(0x00000002); - fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2); - - /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[6] = cpu_to_be32(0x00010019); - fdt_event_ctr_map[7] = cpu_to_be32(0x00010019); - fdt_event_ctr_map[8] = cpu_to_be32(cmask); - - /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B); - fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B); - fdt_event_ctr_map[11] = cpu_to_be32(cmask); - - /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[12] = cpu_to_be32(0x00010021); - fdt_event_ctr_map[13] = cpu_to_be32(0x00010021); - fdt_event_ctr_map[14] = cpu_to_be32(cmask); - - /* This a OpenSBI specific DT property documented in OpenSBI docs */ - qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", - fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); -} - static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) { if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS || diff --git a/target/riscv/pmu.h b/target/riscv/tcg/pmu.h similarity index 95% rename from target/riscv/pmu.h rename to target/riscv/tcg/pmu.h index b4f1e469a2..de2fae1fb4 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/tcg/pmu.h @@ -31,7 +31,6 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); -void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, privilege_mode_t newpriv, -- 2.43.0
