Move riscv_new_csr_seed from csr.c to cpu.c since this function is shared with KVM. With that we can remove the csr.h from kvm-cpu.c.
Signed-off-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> --- target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++ target/riscv/cpu.h | 3 ++- target/riscv/csr.h | 3 --- target/riscv/kvm/kvm-cpu.c | 1 - target/riscv/tcg/csr.c | 29 ----------------------------- 5 files changed, 32 insertions(+), 34 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fe47ae64c9..5d44f993e4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -21,6 +21,7 @@ #include "qemu/qemu-print.h" #include "qemu/ctype.h" #include "qemu/log.h" +#include "qemu/guest-random.h" #include "cpu.h" #include "cpu_vendorid.h" #include "target/riscv/csr.h" @@ -536,6 +537,35 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list) } #endif +/* Used by csr.c and the KVM driver */ +target_ulong riscv_new_csr_seed(target_ulong new_value, + target_ulong write_mask) +{ + uint16_t random_v; + Error *random_e = NULL; + int random_r; + target_ulong rval; + + random_r = qemu_guest_getrandom(&random_v, 2, &random_e); + if (unlikely(random_r < 0)) { + /* + * Failed, for unknown reasons in the crypto subsystem. + * The best we can do is log the reason and return a + * failure indication to the guest. There is no reason + * we know to expect the failure to be transitory, so + * indicate DEAD to avoid having the guest spin on WAIT. + */ + qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", + __func__, error_get_pretty(random_e)); + error_free(random_e); + rval = SEED_OPST_DEAD; + } else { + rval = random_v | SEED_OPST_ES16; + } + + return rval; +} + static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 70b8729bd7..c0e9098728 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -972,7 +972,8 @@ bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); - +target_ulong riscv_new_csr_seed(target_ulong new_value, + target_ulong write_mask); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); const char *priv_spec_to_str(int priv_version); diff --git a/target/riscv/csr.h b/target/riscv/csr.h index c791260f83..73d874ee98 100644 --- a/target/riscv/csr.h +++ b/target/riscv/csr.h @@ -12,9 +12,6 @@ #include "exec/target_long.h" #include "cpu_bits.h" -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask); - RISCVException riscv_csrr(CPURISCVState *env, int csrno, target_ulong *ret_value); diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 39d48a9db4..dcdaf7f2b3 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -31,7 +31,6 @@ #include "system/kvm.h" #include "system/kvm_int.h" #include "cpu.h" -#include "target/riscv/csr.h" #include "trace.h" #include "accel/accel-cpu-target.h" #include "hw/pci/pci.h" diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index b460860409..d447204721 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -29,7 +29,6 @@ #include "exec/icount.h" #include "accel/tcg/cpu-loop.h" #include "accel/tcg/getpc.h" -#include "qemu/guest-random.h" #include "qapi/error.h" #include "tcg/insn-start-words.h" #include "internals.h" @@ -5577,34 +5576,6 @@ static RISCVException write_mnstatus(CPURISCVState *env, int csrno, #endif /* Crypto Extension */ -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask) -{ - uint16_t random_v; - Error *random_e = NULL; - int random_r; - target_ulong rval; - - random_r = qemu_guest_getrandom(&random_v, 2, &random_e); - if (unlikely(random_r < 0)) { - /* - * Failed, for unknown reasons in the crypto subsystem. - * The best we can do is log the reason and return a - * failure indication to the guest. There is no reason - * we know to expect the failure to be transitory, so - * indicate DEAD to avoid having the guest spin on WAIT. - */ - qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", - __func__, error_get_pretty(random_e)); - error_free(random_e); - rval = SEED_OPST_DEAD; - } else { - rval = random_v | SEED_OPST_ES16; - } - - return rval; -} - static RISCVException rmw_seed(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, -- 2.43.0
