These arrays are used internally in tcg/csr.c and in cpu.c in the satp options logic, which is common for both KVM and TCG.
Move it to cpu.c to allow KVM to keep using it in --disable-tcg builds. Signed-off-by: Daniel Henrique Barboza <[email protected]> --- target/riscv/cpu.c | 13 +++++++++++++ target/riscv/cpu.h | 2 -- target/riscv/tcg/csr.c | 12 ------------ target/riscv/tcg/csr.h | 3 +++ 4 files changed, 16 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cba7d2502e..29af0f2be8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -59,6 +59,19 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, #define BYTE(x) (x) #endif +/* SATP bits that are shared between TCG and KVM */ +const bool valid_vm_1_10_32[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV32] = true +}; + +const bool valid_vm_1_10_64[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV39] = true, + [VM_1_10_SV48] = true, + [VM_1_10_SV57] = true +}; + bool riscv_cpu_is_32bit(RISCVCPU *cpu) { return riscv_cpu_mxl(&cpu->env) == MXL_RV32; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 34c63a3628..82430ecec6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -971,8 +971,6 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); void riscv_add_satp_mode_properties(Object *obj); bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); -extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; - void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); target_ulong riscv_new_csr_seed(target_ulong new_value, target_ulong write_mask); diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 572a39d660..b17be35e56 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -1874,18 +1874,6 @@ static const uint64_t hvien_writable_mask = LOCAL_INTERRUPTS; static const uint64_t vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; -const bool valid_vm_1_10_32[16] = { - [VM_1_10_MBARE] = true, - [VM_1_10_SV32] = true -}; - -const bool valid_vm_1_10_64[16] = { - [VM_1_10_MBARE] = true, - [VM_1_10_SV39] = true, - [VM_1_10_SV48] = true, - [VM_1_10_SV57] = true -}; - /* Machine Information Registers */ static RISCVException read_zero(CPURISCVState *env, int csrno, target_ulong *val) diff --git a/target/riscv/tcg/csr.h b/target/riscv/tcg/csr.h index 73d874ee98..53ba3b4a4d 100644 --- a/target/riscv/tcg/csr.h +++ b/target/riscv/tcg/csr.h @@ -69,6 +69,9 @@ enum { CSR_TABLE_SIZE = 0x1000 }; +/* valid_vm_* arrays are shared with KVM via cpu.c */ +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; -- 2.43.0
