The following functions are TCG only and are broken, if they were ever usable in the first place, with KVM:
- riscv_gdb_(get|se)t_csr - riscv_gdb_(get|set)_virtual - riscv_gen_dynamic_csr_feature Gate everything with TCG enabled to at least get them out of the way to enable --disable-tcg. As a note for the future: other archs have distincts gdbstub files for each accelerator. There's a strong case for RISC-V to do the same. Signed-off-by: Daniel Henrique Barboza <[email protected]> --- target/riscv/gdbstub.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index f0a5e0d86f..9abbf5bcdf 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -164,6 +164,7 @@ static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n) return 0; } +#ifdef CONFIG_TCG static int riscv_gdb_get_csr(CPUState *cs, GByteArray *buf, int n) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -294,6 +295,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg) return &cpu->dyn_csr_feature; } +#endif /* CONFIG_TCG */ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg) { @@ -336,7 +338,6 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg) void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; if (env->misa_ext & RVD) { @@ -351,6 +352,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) riscv_gdb_set_vector, ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs)); } + +#ifdef CONFIG_TCG + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); + switch (mcc->def->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, @@ -371,4 +376,5 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs)); } +#endif } -- 2.43.0
