riscv_imsic.c is the only caller. Having it sitting in the TCG only cpu_helper.c gets in the way of --disable-tcg for no good reason.
Signed-off-by: Daniel Henrique Barboza <[email protected]> --- hw/intc/riscv_imsic.c | 13 +++++++++++++ target/riscv/cpu.h | 1 - target/riscv/tcg/cpu_helper.c | 13 ------------- 3 files changed, 13 insertions(+), 14 deletions(-) diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 7e5b5349ba..ebb55191c7 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -46,6 +46,19 @@ #define IMSIC_EISTATE_ENPEND (IMSIC_EISTATE_ENABLED | \ IMSIC_EISTATE_PENDING) +static void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + if (geilen > (TARGET_LONG_BITS - 1)) { + return; + } + + env->geilen = geilen; +} + static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page) { uint32_t i, max_irq, base; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7618110412..7a4d8abe07 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -646,7 +646,6 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env, bool riscv_cpu_fp_enabled(CPURISCVState *env); -void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index baf5cace2f..a5d864cd24 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -526,19 +526,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) } } -void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen) -{ - if (!riscv_has_ext(env, RVH)) { - return; - } - - if (geilen > (TARGET_LONG_BITS - 1)) { - return; - } - - env->geilen = geilen; -} - void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level) { CPURISCVState *env = &cpu->env; -- 2.43.0
