This function is related to Smrnmi and non-masked interrupts, firing up interrupts via env->rnmip from riscv_cpu_local_irq_pending().
This is all TCG only code. Signed-off-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> --- target/riscv/cpu.c | 8 -------- target/riscv/tcg/tcg-cpu.c | 7 +++++++ 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5e951ea19c..cba7d2502e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1160,11 +1160,6 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level) g_assert_not_reached(); } } - -static void riscv_cpu_set_nmi(void *opaque, int irq, int level) -{ - riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level); -} #endif /* CONFIG_USER_ONLY */ static bool riscv_cpu_is_dynamic(Object *cpu_obj) @@ -1183,9 +1178,6 @@ static void riscv_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); - qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, - "riscv.cpu.rnmi", RNMI_MAX); - if (mcc->def->num_triggers) { env->num_triggers = mcc->def->num_triggers; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index fef66557c2..4af5cd9c73 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1662,6 +1662,11 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list) } } } + +static inline void riscv_cpu_set_nmi(void *opaque, int irq, int level) +{ + riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level); +} #endif static void riscv_tcg_cpu_instance_init(CPUState *cs) @@ -1674,6 +1679,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs) if (mcc->def->custom_csrs) { riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); } + qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, + "riscv.cpu.rnmi", RNMI_MAX); #endif misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); -- 2.43.0
