riscv_trigger_* APIs are TCG only. Wrap the usages we have of them in cpu.c with CONFIG_TCG.
After that we can move the header to the tcg subdir. This will be enough to get this out of the way for the --disable-tcg build. Signed-off-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> --- target/riscv/cpu.c | 8 +++++--- target/riscv/machine.c | 2 +- target/riscv/tcg/cpu_helper.c | 2 +- target/riscv/tcg/csr.c | 2 +- target/riscv/tcg/debug.c | 2 +- target/riscv/{ => tcg}/debug.h | 0 target/riscv/tcg/tcg-cpu.c | 2 +- 7 files changed, 10 insertions(+), 8 deletions(-) rename target/riscv/{ => tcg}/debug.h (100%) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 319825882a..fe47ae64c9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -39,7 +39,7 @@ #include "kvm/kvm_riscv.h" #include "tcg/tcg-cpu.h" #if !defined(CONFIG_USER_ONLY) -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #endif /* RISC-V CPU definitions */ @@ -836,9 +836,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) env->vill = true; #ifndef CONFIG_USER_ONLY +#ifdef CONFIG_TCG if (cpu->cfg.debug) { riscv_trigger_reset_hold(env); } +#endif if (cpu->cfg.ext_smrnmi) { env->rnmip = 0; @@ -996,7 +998,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_cpu_register_gdb_regs_for_features(cs); -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) if (cpu->cfg.debug) { riscv_trigger_realize(&cpu->env); } @@ -1011,7 +1013,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) static void riscv_cpu_unrealize(DeviceState *dev) { RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) RISCVCPU *cpu = RISCV_CPU(dev); if (cpu->cfg.debug) { diff --git a/target/riscv/machine.c b/target/riscv/machine.c index e1cbcaa349..11e869a9c1 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -23,7 +23,7 @@ #include "system/tcg.h" #include "migration/cpu.h" #include "exec/icount.h" -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #include "hw/riscv/machines-qom.h" static bool pmp_needed(void *opaque) diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index a893472c4e..8c347aa1c0 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -35,7 +35,7 @@ #include "semihosting/common-semi.h" #include "exec/icount.h" #include "cpu_bits.h" -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #include "pmp.h" #include "qemu/plugin.h" diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 7fb0ad5bc1..b460860409 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -34,7 +34,7 @@ #include "tcg/insn-start-words.h" #include "internals.h" #if !defined(CONFIG_USER_ONLY) -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #endif /* CSR function table public API */ diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index ba5bc6ae13..3c0fe70101 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -28,7 +28,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "cpu.h" -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #include "trace.h" #include "exec/helper-proto.h" #include "exec/watchpoint.h" diff --git a/target/riscv/debug.h b/target/riscv/tcg/debug.h similarity index 100% rename from target/riscv/debug.h rename to target/riscv/tcg/debug.h diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b73e3e9dd4..fe6350f497 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -37,7 +37,7 @@ #include "hw/core/boards.h" #include "system/tcg.h" #include "exec/icount.h" -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #endif /* Hash that stores user set extensions */ -- 2.43.0
