We have a couple of CPUs that has a set of custom CSRs that uses TCG specific APIs. Move the related code to tcg-cpu.c and do not set .custom_csrs if we're not in a TCG build.
What we'll end up doing, sooner or later, is punting all these CPUs to tcg-cpu.c since they're all TCG specific and KVM has nothing to do with them. Another time. Signed-off-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> --- target/riscv/cpu.c | 26 +++++--------------------- target/riscv/cpu.h | 2 ++ target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++ 3 files changed, 28 insertions(+), 21 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 96c92de2ee..5e951ea19c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -524,19 +524,6 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif -#ifndef CONFIG_USER_ONLY -static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list) -{ - for (size_t i = 0; csr_list[i].csr_ops.name; i++) { - int csrno = csr_list[i].csrno; - const riscv_csr_operations *csr_ops = &csr_list[i].csr_ops; - if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)) { - riscv_set_csr_ops(csrno, csr_ops); - } - } -} -#endif - /* Used by csr.c and the KVM driver */ target_ulong riscv_new_csr_seed(target_ulong new_value, target_ulong write_mask) @@ -1244,11 +1231,6 @@ static void riscv_cpu_init(Object *obj) if (mcc->def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) { cpu->env.vext_ver = mcc->def->vext_spec; } -#ifndef CONFIG_USER_ONLY - if (mcc->def->custom_csrs) { - riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); - } -#endif accel_cpu_instance_init(CPU(obj)); } @@ -2822,10 +2804,12 @@ static void riscv_cpu_class_base_init(ObjectClass *c, const void *data) riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg); +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) if (def->custom_csrs) { assert(!mcc->def->custom_csrs); mcc->def->custom_csrs = def->custom_csrs; } +#endif } if (!object_class_is_abstract(c)) { @@ -3178,7 +3162,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.mvendorid = THEAD_VENDOR_ID, .cfg.max_satp_mode = VM_1_10_SV39, -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) .custom_csrs = th_csr_list, #endif ), @@ -3224,7 +3208,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.marchid = 0x8d143000, .cfg.mvendorid = THEAD_VENDOR_ID, -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) .custom_csrs = th_csr_list, #endif ), @@ -3429,7 +3413,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.ext_xmipscmov = true, .cfg.marchid = 0x8000000000000201, .cfg.mvendorid = MIPS_VENDOR_ID, -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) .custom_csrs = mips_csr_list, #endif ), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0e9098728..34c63a3628 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -591,7 +591,9 @@ typedef struct RISCVCPUDef { int32_t vext_spec; RISCVCPUConfig cfg; bool bare; +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) const RISCVCSR *custom_csrs; +#endif /* This is just a setter for env->num_triggers. */ uint32_t num_triggers; } RISCVCPUDef; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index fe6350f497..fef66557c2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -38,6 +38,7 @@ #include "system/tcg.h" #include "exec/icount.h" #include "target/riscv/tcg/debug.h" +#include "target/riscv/tcg/csr.h" #endif /* Hash that stores user set extensions */ @@ -1650,10 +1651,30 @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; } +#ifndef CONFIG_USER_ONLY +static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list) +{ + for (size_t i = 0; csr_list[i].csr_ops.name; i++) { + int csrno = csr_list[i].csrno; + const riscv_csr_operations *csr_ops = &csr_list[i].csr_ops; + if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)) { + riscv_set_csr_ops(csrno, csr_ops); + } + } +} +#endif + static void riscv_tcg_cpu_instance_init(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); Object *obj = OBJECT(cpu); +#ifndef CONFIG_USER_ONLY + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj); + + if (mcc->def->custom_csrs) { + riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); + } +#endif misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); -- 2.43.0
