Uses TypeInfo::is_available to determine what CPUs to register, convenience macros are modified slightly to make this conversion more ergonomic.
Signed-off-by: Anton Johansson <[email protected]> --- target/riscv/cpu.c | 156 +++++++++++++++++++++++++++++++++-------------------- 1 file changed, 97 insertions(+), 59 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8c8f08bb50..cfc80aaaf1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -23,6 +23,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "qemu/guest-random.h" +#include "qemu/target-info.h" #include "cpu.h" #include "cpu_vendorid.h" #include "target/riscv/tcg/csr.h" @@ -3259,34 +3260,76 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) } #endif -#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \ - { \ - .name = (type_name), \ - .parent = (parent_type_name), \ - .abstract = true, \ - .class_data = &(const RISCVCPUDef) { \ - .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \ - .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \ - .cfg.max_satp_mode = -1, \ - __VA_ARGS__ \ - }, \ +/* + * Returns true for targets supporting 32-bit CPUs + * (32-bit user-/system-mode or 64-bit system-mode). + */ +static bool riscv_cpu_supports_rv32(void) +{ +#ifdef CONFIG_USER_ONLY + return target_riscv32(); +#else + return true; +#endif +} + +/* + * Returns true for targets supporting 64-bit CPUs + * (64-bit user and system-mode). + */ +static bool riscv_cpu_supports_rv64(void) +{ + return target_riscv64(); +} + +/* + * Returns true for targets supporting 128-bit CPUs + * (64-bit system-mode on TCG). + */ +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +static bool riscv_cpu_supports_rv128(void) +{ + return target_riscv64(); +} +#endif + +#define DEFINE_RISCV_CPU_FULL(type_name, parent_type_name, \ + abstract_, avail_fn, ...) \ + { \ + .name = (type_name), \ + .parent = (parent_type_name), \ + .abstract = (abstract_), \ + .class_data = &(const RISCVCPUDef) { \ + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \ + .cfg.max_satp_mode = -1, \ + __VA_ARGS__ \ + }, \ + .is_available = (avail_fn), \ } +#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \ + DEFINE_RISCV_CPU_FULL(type_name, parent_type_name, true, NULL, __VA_ARGS__) + +#define DEFINE_RISCV64_PROFILE_CPU(type_name, parent_type_name, profile_) \ + DEFINE_RISCV_CPU_FULL(type_name, parent_type_name, false, \ + riscv_cpu_supports_rv64, \ + .profile = &(profile_)) + #define DEFINE_RISCV_CPU(type_name, parent_type_name, ...) \ - { \ - .name = (type_name), \ - .parent = (parent_type_name), \ - .class_data = &(const RISCVCPUDef) { \ - .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \ - .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \ - .cfg.max_satp_mode = -1, \ - __VA_ARGS__ \ - }, \ - } + DEFINE_RISCV_CPU_FULL(type_name, parent_type_name, false, NULL, __VA_ARGS__) -#define DEFINE_PROFILE_CPU(type_name, parent_type_name, profile_) \ - DEFINE_RISCV_CPU(type_name, parent_type_name, \ - .profile = &(profile_)) +#define DEFINE_RISCV32_CPU(type_name, parent_type_name, ...) \ + DEFINE_RISCV_CPU_FULL(type_name, parent_type_name, false, \ + riscv_cpu_supports_rv32, __VA_ARGS__) + +#define DEFINE_RISCV64_CPU(type_name, parent_type_name, ...) \ + DEFINE_RISCV_CPU_FULL(type_name, parent_type_name, false, \ + riscv_cpu_supports_rv64, __VA_ARGS__) + +#define DEFINE_RISCV128_CPU(type_name, parent_type_name, ...) \ + DEFINE_RISCV_CPU_FULL(type_name, parent_type_name, false, \ + riscv_cpu_supports_rv128, __VA_ARGS__) static void riscv_cpu_instance_finalize(Object *obj) { @@ -3380,9 +3423,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.pmp_regions = 8 ), -#if defined(TARGET_RISCV32) || \ - (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU, + DEFINE_RISCV32_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode = VM_1_10_SV32, .misa_mxl_max = MXL_RV32, @@ -3408,7 +3449,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.ext_svvptc = true, ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU, + DEFINE_RISCV32_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU, .misa_mxl_max = MXL_RV32, .misa_ext = RVI | RVM | RVC | RVU, .priv_spec = PRIV_VERSION_1_12_0, @@ -3425,37 +3466,35 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.ext_xlrbr = true ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E, + DEFINE_RISCV32_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E, .misa_mxl_max = MXL_RV32 ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E34, TYPE_RISCV_CPU_SIFIVE_E, + DEFINE_RISCV32_CPU(TYPE_RISCV_CPU_SIFIVE_E34, TYPE_RISCV_CPU_SIFIVE_E, .misa_mxl_max = MXL_RV32, .misa_ext = RVF, /* IMAFCU */ ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U34, TYPE_RISCV_CPU_SIFIVE_U, + DEFINE_RISCV32_CPU(TYPE_RISCV_CPU_SIFIVE_U34, TYPE_RISCV_CPU_SIFIVE_U, .misa_mxl_max = MXL_RV32, ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU, + DEFINE_RISCV32_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU, .misa_mxl_max = MXL_RV32, .misa_ext = RVI ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32E, TYPE_RISCV_BARE_CPU, + DEFINE_RISCV32_CPU(TYPE_RISCV_CPU_RV32E, TYPE_RISCV_BARE_CPU, .misa_mxl_max = MXL_RV32, .misa_ext = RVE ), -#endif -#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX32, TYPE_RISCV_DYNAMIC_CPU, +#ifndef CONFIG_USER_ONLY + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_MAX32, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode = VM_1_10_SV32, .misa_mxl_max = MXL_RV32, ), #endif -#if defined(TARGET_RISCV64) - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE64, TYPE_RISCV_DYNAMIC_CPU, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_BASE64, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode = VM_1_10_SV57, .misa_mxl_max = MXL_RV64, @@ -3481,19 +3520,19 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.ext_svvptc = true, ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E, .misa_mxl_max = MXL_RV64 ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U54, TYPE_RISCV_CPU_SIFIVE_U, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_SIFIVE_U54, TYPE_RISCV_CPU_SIFIVE_U, .misa_mxl_max = MXL_RV64, ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SHAKTI_C, TYPE_RISCV_CPU_SIFIVE_U, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_SHAKTI_C, TYPE_RISCV_CPU_SIFIVE_U, .misa_mxl_max = MXL_RV64, ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C906, TYPE_RISCV_VENDOR_CPU, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_THEAD_C906, TYPE_RISCV_VENDOR_CPU, .misa_mxl_max = MXL_RV64, .misa_ext = RVG | RVC | RVS | RVU, .priv_spec = PRIV_VERSION_1_11_0, @@ -3521,7 +3560,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { #endif ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C908, TYPE_RISCV_VENDOR_CPU, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_THEAD_C908, TYPE_RISCV_VENDOR_CPU, .misa_mxl_max = MXL_RV64, .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU, .priv_spec = PRIV_VERSION_1_12_0, @@ -3568,12 +3607,12 @@ static const TypeInfo riscv_cpu_type_infos[] = { #endif ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C908V, TYPE_RISCV_CPU_THEAD_C908, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_THEAD_C908V, TYPE_RISCV_CPU_THEAD_C908, .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV, .vext_spec = VEXT_VERSION_1_00_0, ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_TT_ASCALON, TYPE_RISCV_VENDOR_CPU, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_TT_ASCALON, TYPE_RISCV_VENDOR_CPU, .misa_mxl_max = MXL_RV64, .misa_ext = RVG | RVC | RVS | RVU | RVH | RVV, .priv_spec = PRIV_VERSION_1_13_0, @@ -3637,7 +3676,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.max_satp_mode = VM_1_10_SV57, ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU, .misa_mxl_max = MXL_RV64, .misa_ext = RVG | RVC | RVS | RVU | RVH, .priv_spec = PRIV_VERSION_1_12_0, @@ -3673,7 +3712,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.max_satp_mode = VM_1_10_SV48, ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, TYPE_RISCV_VENDOR_CPU, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, TYPE_RISCV_VENDOR_CPU, .misa_mxl_max = MXL_RV64, .misa_ext = RVG | RVC | RVB | RVS | RVU, .priv_spec = PRIV_VERSION_1_12_0, @@ -3696,7 +3735,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.max_satp_mode = VM_1_10_SV39, ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH, TYPE_RISCV_VENDOR_CPU, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH, TYPE_RISCV_VENDOR_CPU, .misa_mxl_max = MXL_RV64, .misa_ext = RVG | RVC | RVB | RVS | RVU | RVH | RVV, .priv_spec = PRIV_VERSION_1_13_0, @@ -3756,7 +3795,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { ), /* https://mips.com/products/hardware/p8700/ */ - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MIPS_P8700, TYPE_RISCV_VENDOR_CPU, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_MIPS_P8700, TYPE_RISCV_VENDOR_CPU, .misa_mxl_max = MXL_RV64, .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU, .priv_spec = PRIV_VERSION_1_12_0, @@ -3778,26 +3817,25 @@ static const TypeInfo riscv_cpu_type_infos[] = { #endif ), -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) + DEFINE_RISCV128_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode = VM_1_10_SV57, .misa_mxl_max = MXL_RV128, ), -#endif /* CONFIG_TCG */ - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU, +#endif + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU, .misa_mxl_max = MXL_RV64, .misa_ext = RVI ), - DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64E, TYPE_RISCV_BARE_CPU, + DEFINE_RISCV64_CPU(TYPE_RISCV_CPU_RV64E, TYPE_RISCV_BARE_CPU, .misa_mxl_max = MXL_RV64, .misa_ext = RVE ), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RVA22U64), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RVA22S64), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, TYPE_RISCV_CPU_RV64I, RVA23U64), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, TYPE_RISCV_CPU_RV64I, RVA23S64), -#endif /* TARGET_RISCV64 */ + DEFINE_RISCV64_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RVA22U64), + DEFINE_RISCV64_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RVA22S64), + DEFINE_RISCV64_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, TYPE_RISCV_CPU_RV64I, RVA23U64), + DEFINE_RISCV64_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, TYPE_RISCV_CPU_RV64I, RVA23S64), }; DEFINE_TYPES(riscv_cpu_type_infos) -- 2.52.0
