On 10/1/2026 8:59 AM, Anton Johansson via qemu development wrote: > Mostly mechanical change of target_ulong to uint64_t, motivated by the > fact that csr.c compiled with a 64-bit target_ulong already can handle > rv32 CPUs just fine. If there's any discrepancy between rv32 on > qemu-riscv32 and rv32 on qemu-riscv64 I've failed to take into account > please do let me know. > > Aside from minor formatting fixes, masks are sometimes replaced with > ~0ULL, such as for write_vsstatus() > > - uint64_t mask = (target_ulong)-1; > + uint64_t mask = ~0ULL; > > this assumes that the behaviour for rv32 on qemu-riscv64 is correct. > > Functions in other files containing CSR relevant behaviour are > also updated. > > Signed-off-by: Anton Johansson <[email protected]> > --- > target/riscv/tcg/csr.h | 35 +- > target/riscv/tcg/debug.h | 11 +- > target/riscv/cpu.c | 11 +- > target/riscv/gdbstub.c | 2 +- > target/riscv/monitor.c | 5 +- > target/riscv/tcg/csr.c | 736 > +++++++++++++++++++++---------------------- > target/riscv/tcg/debug.c | 10 +- > target/riscv/tcg/mips_csr.c | 12 +- > target/riscv/tcg/op_helper.c | 6 +- > target/riscv/tcg/pmp.c | 14 +- > target/riscv/tcg/pmu.c | 4 +- > target/riscv/tcg/th_csr.c | 6 +- > target/riscv/tcg/meson.build | 13 +- > 13 files changed, 434 insertions(+), 431 deletions(-) >
Reviewed-by: Pierrick Bouvier <[email protected]>
