Missing review: patches 3, 4, 10, 13, 14 Since v3: - Rebased; v3 patches 1-3 and 5 were merged - Use translator_ld*_end() with mo_endian() - Select decoders from the instruction size (Richard) - New patch 4, computing the microMIPS size up front (Richard) - Treat MIPS16e JAL/JALX as 32-bit - Add micromips32_r6.decode; LSA no longer accepted on pre-R6 microMIPS CPUs - Fix MIPS16e EXT-RI LI immediate field order - Fix nanoMIPS LI[16] register map and unsigned immediate - Fix nanoMIPS LI[48] immediate halfword order; split the NMS check into trans_LI_nnms(), reusing check_nms() - New patch 10, sharing the MIPS16e/microMIPS GPR xlat map
Prepare the build system and the per-ISA dispatchers so MIPS16e, microMIPS and nanoMIPS opcodes can be decoded with the decodetree script, then convert the first opcodes: LSA and LI. v3: https://lore.kernel.org/qemu-devel/[email protected]/ Philippe Mathieu-Daudé (14): target/mips: Call translator_ld() in translate_insn() callees target/mips: Decode LSA shift amount using decodetree function target/mips: Introduce decode tree bindings for MIPS16e ASE target/mips: Determine microMIPS insn size before delay slot check target/mips: Introduce decodetree bindings for microMIPS ISA scripts/decodetree: Add support for 48-bit instructions target/mips: Introduce decode tree bindings for nanoMIPS ISA target/mips: Convert microMIPS LSA opcode to decodetree target/mips: Convert nanoMIPS LSA opcode to decodetree target/mips: Share MIPS16e/microMIPS 3-bit GPR xlat mapping target/mips: Add gen_li() helper target/mips: Convert microMIPS LI opcode to decodetree target/mips: Convert MIPS16e LI opcodes to decodetree target/mips: Convert nanoMIPS LI opcodes to decodetree target/mips/tcg/translate.h | 11 ++ target/mips/tcg/micromips16.decode | 18 +++ target/mips/tcg/micromips32.decode | 11 ++ target/mips/tcg/micromips32_r6.decode | 19 +++ target/mips/tcg/mips16e_16.decode | 17 +++ target/mips/tcg/mips16e_32.decode | 18 +++ target/mips/tcg/msa.decode | 3 +- target/mips/tcg/nanomips16.decode | 17 +++ target/mips/tcg/nanomips32.decode | 14 ++ target/mips/tcg/nanomips48.decode | 16 +++ target/mips/tcg/rel6.decode | 5 +- target/mips/tcg/comput_translate.c | 21 +++ target/mips/tcg/micromips_translate.c | 37 ++++++ target/mips/tcg/mips16e_translate.c | 21 +++ target/mips/tcg/msa_translate.c | 4 +- target/mips/tcg/nanomips_translate.c | 46 +++++++ target/mips/tcg/rel6_translate.c | 9 +- target/mips/tcg/translate.c | 24 ++-- target/mips/tcg/micromips_translate.c.inc | 152 +++++++++++----------- target/mips/tcg/mips16e_translate.c.inc | 56 ++++---- target/mips/tcg/nanomips_translate.c.inc | 56 ++++---- scripts/decodetree.py | 4 + target/mips/tcg/meson.build | 12 ++ 23 files changed, 447 insertions(+), 144 deletions(-) create mode 100644 target/mips/tcg/micromips16.decode create mode 100644 target/mips/tcg/micromips32.decode create mode 100644 target/mips/tcg/micromips32_r6.decode create mode 100644 target/mips/tcg/mips16e_16.decode create mode 100644 target/mips/tcg/mips16e_32.decode create mode 100644 target/mips/tcg/nanomips16.decode create mode 100644 target/mips/tcg/nanomips32.decode create mode 100644 target/mips/tcg/nanomips48.decode create mode 100644 target/mips/tcg/comput_translate.c create mode 100644 target/mips/tcg/micromips_translate.c create mode 100644 target/mips/tcg/mips16e_translate.c create mode 100644 target/mips/tcg/nanomips_translate.c -- 2.55.0
