From: Philippe Mathieu-Daudé <[email protected]> Convert both the 16-bit RI and the extended EXT-RI forms. Decode the destination with xlat(); both immediates are zero-extended (8-bit and 16-bit).
The legacy decoder ignored EXT-RI bits [7:5]; the pattern requires them to be zero, as specified. Other encodings now raise a Reserved Instruction exception. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- Since v3: - Fix EXT-RI immediate field order (%ext_uimm16) - Rename @ri format as @ext_ri --- target/mips/tcg/mips16e_16.decode | 8 ++++++++ target/mips/tcg/mips16e_32.decode | 9 +++++++++ target/mips/tcg/mips16e_translate.c | 7 +++++++ target/mips/tcg/mips16e_translate.c.inc | 11 ----------- 4 files changed, 24 insertions(+), 11 deletions(-) diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode index 2f3926052b9e..67c6c1bb7362 100644 --- a/target/mips/tcg/mips16e_16.decode +++ b/target/mips/tcg/mips16e_16.decode @@ -7,3 +7,11 @@ # Reference: MIPS Architecture for Programmers, Volume IV-a # The MIPS16e Application Specific Extension # (Document Number: MD00076) + +&rd_imm rd imm + +%rx3 8:3 !function=gpr3_m16 + +@ri ..... ... imm:8 &rd_imm rd=%rx3 + +LI 01101 ... ........ @ri diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode index 1dccb554fb56..39cd8144ac03 100644 --- a/target/mips/tcg/mips16e_32.decode +++ b/target/mips/tcg/mips16e_32.decode @@ -7,3 +7,12 @@ # Reference: MIPS Architecture for Programmers, Volume IV-a # The MIPS16e Application Specific Extension # (Document Number: MD00076) + +&rd_imm rd imm !extern + +%ext_uimm16 16:5 21:6 0:5 +%rx3 8:3 !function=gpr3_m16 + +@ext_ri ..... ...... ..... ..... ... ... ..... &rd_imm rd=%rx3 imm=%ext_uimm16 + +LI 11110 ...... ..... 01101 ... 000 ..... @ext_ri diff --git a/target/mips/tcg/mips16e_translate.c b/target/mips/tcg/mips16e_translate.c index 136468c65c71..ff739a50b0cd 100644 --- a/target/mips/tcg/mips16e_translate.c +++ b/target/mips/tcg/mips16e_translate.c @@ -12,3 +12,10 @@ /* Include the auto-generated decoders. */ #include "decode-mips16e_16.c.inc" #include "decode-mips16e_32.c.inc" + +static bool trans_LI(DisasContext *ctx, arg_rd_imm *a) +{ + gen_li(ctx, a->rd, a->imm); + + return true; +} diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index ed2bbbc66be9..043baa0965ea 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -24,7 +24,6 @@ enum { M16_OPC_SLTI = 0x0a, M16_OPC_SLTIU = 0x0b, M16_OPC_I8 = 0x0c, - M16_OPC_LI = 0x0d, M16_OPC_CMPI = 0x0e, M16_OPC_SD = 0x0f, M16_OPC_LB = 0x10, @@ -575,9 +574,6 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) break; } break; - case M16_OPC_LI: - tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm); - break; case M16_OPC_CMPI: tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm); break; @@ -841,13 +837,6 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) } } break; - case M16_OPC_LI: - { - int16_t imm = (uint8_t) ctx->opcode; - - gen_arith_imm(ctx, OPC_ADDIU, rx, 0, imm); - } - break; case M16_OPC_CMPI: { int16_t imm = (uint8_t) ctx->opcode; -- 2.55.0
