The 3-bit register fields of MIPS16e and microMIPS 16-bit encodings map to the same 8 GPRs. The map is duplicated, and we want to re-use it for nanoMIPS. Rename as common gpr3_m16() helper, using the decodetree !function signature so both the legacy and the decodetree decoders can call it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/mips/tcg/translate.h | 1 + target/mips/tcg/translate.c | 11 ++++ target/mips/tcg/micromips_translate.c.inc | 61 ++++++++++------------- target/mips/tcg/mips16e_translate.c.inc | 19 +++---- 4 files changed, 45 insertions(+), 47 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index d11b2f32f009..50b62b9dfd28 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -224,6 +224,7 @@ void mxu_translate_init(void); bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); bool decode_64bit_enabled(DisasContext *ctx); +int gpr3_m16(DisasContext *ctx, int x); /* decodetree generated */ bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 69c82af046a0..74c571c1c125 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1623,6 +1623,17 @@ bool decode_64bit_enabled(DisasContext *ctx) return ctx->hflags & MIPS_HFLAG_64; } +/* + * Map the 3-bit register field of MIPS16e and microMIPS + * 16-bit encodings to a GPR index. + */ +int gpr3_m16(DisasContext *ctx, int x) +{ + static const int map[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; + + return map[x]; +} + /* * This code generates a "reserved instruction" exception if cpu is not * 64-bit or 64-bit instructions are not enabled. diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 6eb8e79ec57b..88ec1668bd8b 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -605,13 +605,6 @@ enum { ADDIUR1SP = 0x1 }; -static int mmreg(int r) -{ - static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; - - return map[r]; -} - /* Used for 16-bit store instructions. */ static int mmreg2(int r) { @@ -637,7 +630,7 @@ static int mmreg2(int r) static void gen_addiur1sp(DisasContext *ctx) { - int rd = mmreg(uMIPS_RD(ctx->opcode)); + int rd = gpr3_m16(ctx, uMIPS_RD(ctx->opcode)); gen_arith_imm(ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2); } @@ -645,8 +638,8 @@ static void gen_addiur1sp(DisasContext *ctx) static void gen_addiur2(DisasContext *ctx) { static const int decoded_imm[] = { 1, 4, 8, 12, 16, 20, 24, -1 }; - int rd = mmreg(uMIPS_RD(ctx->opcode)); - int rs = mmreg(uMIPS_RS(ctx->opcode)); + int rd = gpr3_m16(ctx, uMIPS_RD(ctx->opcode)); + int rs = gpr3_m16(ctx, uMIPS_RS(ctx->opcode)); gen_arith_imm(ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]); } @@ -681,8 +674,8 @@ static void gen_andi16(DisasContext *ctx) { static const int decoded_imm[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 }; - int rd = mmreg(uMIPS_RD(ctx->opcode)); - int rs = mmreg(uMIPS_RS(ctx->opcode)); + int rd = gpr3_m16(ctx, uMIPS_RD(ctx->opcode)); + int rs = gpr3_m16(ctx, uMIPS_RS(ctx->opcode)); int encoded = ZIMM(ctx->opcode, 0, 4); gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]); @@ -734,8 +727,8 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist, static void gen_pool16c_insn(DisasContext *ctx) { - int rd = mmreg((ctx->opcode >> 3) & 0x7); - int rs = mmreg(ctx->opcode & 0x7); + int rd = gpr3_m16(ctx, (ctx->opcode >> 3) & 0x7); + int rs = gpr3_m16(ctx, ctx->opcode & 0x7); switch (((ctx->opcode) >> 4) & 0x3f) { case NOT16 + 0: @@ -872,8 +865,8 @@ static inline void gen_movep(DisasContext *ctx, int enc_dest, int enc_rt, static void gen_pool16c_r6_insn(DisasContext *ctx) { - int rt = mmreg((ctx->opcode >> 7) & 0x7); - int rs = mmreg((ctx->opcode >> 4) & 0x7); + int rt = gpr3_m16(ctx, (ctx->opcode >> 7) & 0x7); + int rs = gpr3_m16(ctx, (ctx->opcode >> 4) & 0x7); switch (ctx->opcode & 0xf) { case R6_NOT16: @@ -2853,7 +2846,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } } else { /* ADDIUPC */ - int reg = mmreg(ZIMM(ctx->opcode, 23, 3)); + int reg = gpr3_m16(ctx, ZIMM(ctx->opcode, 23, 3)); offset = SIMM(ctx->opcode, 0, 23) << 2; gen_addiupc(ctx, reg, offset, 0, 0); @@ -3041,9 +3034,9 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) switch (op) { case POOL16A: { - int rd = mmreg(uMIPS_RD(ctx->opcode)); - int rs1 = mmreg(uMIPS_RS1(ctx->opcode)); - int rs2 = mmreg(uMIPS_RS2(ctx->opcode)); + int rd = gpr3_m16(ctx, uMIPS_RD(ctx->opcode)); + int rs1 = gpr3_m16(ctx, uMIPS_RS1(ctx->opcode)); + int rs2 = gpr3_m16(ctx, uMIPS_RS2(ctx->opcode)); uint32_t opc = 0; switch (ctx->opcode & 0x1) { @@ -3067,8 +3060,8 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) break; case POOL16B: { - int rd = mmreg(uMIPS_RD(ctx->opcode)); - int rs = mmreg(uMIPS_RS(ctx->opcode)); + int rd = gpr3_m16(ctx, uMIPS_RD(ctx->opcode)); + int rs = gpr3_m16(ctx, uMIPS_RS(ctx->opcode)); int amount = (ctx->opcode >> 1) & 0x7; uint32_t opc = 0; amount = amount == 0 ? 8 : amount; @@ -3094,7 +3087,7 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) break; case LWGP16: { - int rd = mmreg(uMIPS_RD(ctx->opcode)); + int rd = gpr3_m16(ctx, uMIPS_RD(ctx->opcode)); int rb = 28; /* GP */ int16_t offset = SIMM(ctx->opcode, 0, 7) << 2; @@ -3115,8 +3108,8 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) break; case LBU16: { - int rd = mmreg(uMIPS_RD(ctx->opcode)); - int rb = mmreg(uMIPS_RS(ctx->opcode)); + int rd = gpr3_m16(ctx, uMIPS_RD(ctx->opcode)); + int rb = gpr3_m16(ctx, uMIPS_RS(ctx->opcode)); int16_t offset = ZIMM(ctx->opcode, 0, 4); offset = (offset == 0xf ? -1 : offset); @@ -3125,8 +3118,8 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) break; case LHU16: { - int rd = mmreg(uMIPS_RD(ctx->opcode)); - int rb = mmreg(uMIPS_RS(ctx->opcode)); + int rd = gpr3_m16(ctx, uMIPS_RD(ctx->opcode)); + int rb = gpr3_m16(ctx, uMIPS_RS(ctx->opcode)); int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; gen_ld(ctx, OPC_LHU, rd, rb, offset); @@ -3143,8 +3136,8 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) break; case LW16: { - int rd = mmreg(uMIPS_RD(ctx->opcode)); - int rb = mmreg(uMIPS_RS(ctx->opcode)); + int rd = gpr3_m16(ctx, uMIPS_RD(ctx->opcode)); + int rb = gpr3_m16(ctx, uMIPS_RS(ctx->opcode)); int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; gen_ld(ctx, OPC_LW, rd, rb, offset); @@ -3153,7 +3146,7 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) case SB16: { int rd = mmreg2(uMIPS_RD(ctx->opcode)); - int rb = mmreg(uMIPS_RS(ctx->opcode)); + int rb = gpr3_m16(ctx, uMIPS_RS(ctx->opcode)); int16_t offset = ZIMM(ctx->opcode, 0, 4); gen_st(ctx, OPC_SB, rd, rb, offset); @@ -3162,7 +3155,7 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) case SH16: { int rd = mmreg2(uMIPS_RD(ctx->opcode)); - int rb = mmreg(uMIPS_RS(ctx->opcode)); + int rb = gpr3_m16(ctx, uMIPS_RS(ctx->opcode)); int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; gen_st(ctx, OPC_SH, rd, rb, offset); @@ -3180,7 +3173,7 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) case SW16: { int rd = mmreg2(uMIPS_RD(ctx->opcode)); - int rb = mmreg(uMIPS_RS(ctx->opcode)); + int rb = gpr3_m16(ctx, uMIPS_RS(ctx->opcode)); int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; gen_st(ctx, OPC_SW, rd, rb, offset); @@ -3225,14 +3218,14 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) case BNEZ16: /* BNEZC16 */ case BEQZ16: /* BEQZC16 */ gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2, - mmreg(uMIPS_RD(ctx->opcode)), + gpr3_m16(ctx, uMIPS_RD(ctx->opcode)), 0, sextract32(ctx->opcode, 0, 7) << 1, (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); break; case LI16: { - int reg = mmreg(uMIPS_RD(ctx->opcode)); + int reg = gpr3_m16(ctx, uMIPS_RD(ctx->opcode)); int imm = ZIMM(ctx->opcode, 0, 7); imm = (imm == 0x7f ? -1 : imm); diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index dfb4312f1835..ed2bbbc66be9 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -120,13 +120,6 @@ enum { RR_RY_CNVT_SEW = 0x6, }; -static int xlat(int r) -{ - static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; - - return map[r]; -} - static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0) { TCGv t1 = tcg_temp_new(); @@ -459,8 +452,8 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) op = (ctx->opcode >> 11) & 0x1f; sa = (ctx->opcode >> 22) & 0x1f; funct = (ctx->opcode >> 8) & 0x7; - rx = xlat((ctx->opcode >> 8) & 0x7); - ry = xlat((ctx->opcode >> 5) & 0x7); + rx = gpr3_m16(ctx, (ctx->opcode >> 8) & 0x7); + ry = gpr3_m16(ctx, (ctx->opcode >> 5) & 0x7); offset = imm = (int16_t) (((ctx->opcode >> 16) & 0x1f) << 11 | ((ctx->opcode >> 21) & 0x3f) << 5 | (ctx->opcode & 0x1f)); @@ -676,9 +669,9 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) sa = (ctx->opcode >> 2) & 0x7; sa = sa == 0 ? 8 : sa; - rx = xlat((ctx->opcode >> 8) & 0x7); + rx = gpr3_m16(ctx, (ctx->opcode >> 8) & 0x7); cnvt_op = (ctx->opcode >> 5) & 0x7; - ry = xlat((ctx->opcode >> 5) & 0x7); + ry = gpr3_m16(ctx, (ctx->opcode >> 5) & 0x7); op1 = offset = ctx->opcode & 0x1f; n_bytes = 2; @@ -831,7 +824,7 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) break; case I8_MOV32R: { - int rz = xlat(ctx->opcode & 0x7); + int rz = gpr3_m16(ctx, ctx->opcode & 0x7); reg32 = (((ctx->opcode >> 3) & 0x3) << 3) | ((ctx->opcode >> 5) & 0x7); @@ -910,7 +903,7 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) break; case M16_OPC_RRR: { - int rz = xlat((ctx->opcode >> 2) & 0x7); + int rz = gpr3_m16(ctx, (ctx->opcode >> 2) & 0x7); int mips32_op; switch (ctx->opcode & 0x3) { -- 2.55.0
