From: Philippe Mathieu-Daudé <[email protected]> Historically we were only calling decode_opc() from the MIPS translate_insn() handler. Then variable instruction length ISAs were added, we kept using the same pattern but call yet more translator_ld() in the callees when necessary.
This is cumbersome and bug prone, so better move all translator_ld() calls to the callees where it is more logical. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- Since v3: - Rebased on translator_ld*_end() API, passing mo_endian() --- target/mips/tcg/translate.c | 11 +++-------- target/mips/tcg/micromips_translate.c.inc | 4 ++++ target/mips/tcg/mips16e_translate.c.inc | 9 ++++++--- target/mips/tcg/nanomips_translate.c.inc | 13 ++++++++++--- 4 files changed, 23 insertions(+), 14 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 936f8c4eddc4..69c82af046a0 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15050,6 +15050,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) gen_set_label(l1); } + ctx->opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next, + mo_endian(ctx)); + /* Transition to the auto-generated decoder. */ /* Vendor specific extensions */ @@ -15175,21 +15178,13 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) is_slot = ctx->hflags & MIPS_HFLAG_BMASK; if (ctx->insn_flags & ISA_NANOMIPS32) { - ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, - mo_endian(ctx)); insn_bytes = decode_isa_nanomips(env, ctx); } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { - ctx->opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next, - mo_endian(ctx)); insn_bytes = 4; decode_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { - ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, - mo_endian(ctx)); insn_bytes = decode_isa_micromips(env, ctx); } else if (ctx->insn_flags & ASE_MIPS16) { - ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, - mo_endian(ctx)); insn_bytes = decode_ase_mips16e(env, ctx); } else { gen_reserved_instruction(ctx); diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 07172a6c7fe0..0984b8a505dd 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -2979,6 +2979,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) { + uint32_t opcode; uint32_t op; /* make sure instructions are on a halfword boundary */ @@ -2988,6 +2989,9 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) return 2; } + opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, + mo_endian(ctx)); + ctx->opcode = opcode; op = (ctx->opcode >> 10) & 0x3f; /* Enforce properly-sized instructions in a delay slot */ if (ctx->hflags & MIPS_HFLAG_BDS_STRICT) { diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index e83587971d4e..eb77326acf6b 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -453,12 +453,9 @@ static void decode_i64_mips16(DisasContext *ctx, static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { - int extend = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, - mo_endian(ctx)); int op, rx, ry, funct, sa; int16_t imm, offset; - ctx->opcode = (ctx->opcode << 16) | extend; op = (ctx->opcode >> 11) & 0x1f; sa = (ctx->opcode >> 22) & 0x1f; funct = (ctx->opcode >> 8) & 0x7; @@ -659,6 +656,8 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) int funct; int n_bytes; + ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, + mo_endian(ctx)); op = (ctx->opcode >> 11) & 0x1f; sa = (ctx->opcode >> 2) & 0x7; sa = sa == 0 ? 8 : sa; @@ -1105,6 +1104,10 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) } break; case M16_OPC_EXTEND: + ctx->opcode <<= 16; + ctx->opcode |= translator_lduw_end(env, &ctx->base, + ctx->base.pc_next + 2, + mo_endian(ctx)); decode_extended_mips16_opc(env, ctx); n_bytes = 4; break; diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 4b0b01ba37ad..421f26a192cb 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -4463,10 +4463,11 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) { + uint64_t opcode; uint32_t op; - int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode)); - int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode)); - int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode)); + int rt; + int rs; + int rd; int offset; int imm; @@ -4478,6 +4479,12 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) return 2; } + opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, + mo_endian(ctx)); + ctx->opcode = opcode; + rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode)); + rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode)); + rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode)); op = extract32(ctx->opcode, 10, 6); switch (op) { case NM_P16_MV: -- 2.55.0
