On Wed, Dec 13, 2000 at 04:39:32PM -0500, Victor Iannello wrote:
> Isn't true that when the scheduler is in periodic mode, the timer is not
> reprogrammed, but yet jitter of around 15 us can still be observed under
> some circumstances. Why is this?
Note that just _reading_ the damn thing can cause this delay.
>
> Victor Iannello
> Synchrony Inc.
>
> ----- Original Message -----
> From: <[EMAIL PROTECTED]>
> To: "Norm Dresner" <[EMAIL PROTECTED]>
> Cc: <[EMAIL PROTECTED]>; "rtlinux mailing list" <[EMAIL PROTECTED]>
> Sent: Tuesday, December 12, 2000 10:47 PM
> Subject: Re: [rtl] Interrupt Jitter
>
>
> > On Tue, Dec 12, 2000 at 07:29:23PM -0500, Norm Dresner wrote:
> > > Can you be more specific about the source of the jitter on the
> motherboard?
> >
> > Our measurements show it to be the ISA interface and the use of the 8253/4
> > timer on the other side of the interface. There is a simple experiment
> that
> > we should include in the RTL distribution that does
> >
> >
> > read cycle timer
> > read 8253 register
> > read cycle timer
> > compute difference
> >
> > The computed difference was up to 15 microseconds or so when I last did
> the
> > experiment on a fast x86.
> > Our Elan420 boards do much much better.
> >
> > >
> > > Norman Dresner
> > > Fellow Systems Engineer
> > > Radar Systems Engineering Department
> > > Electronic Systems and Sensors Segment
> > > Northrop Grumman Corporation
> > > MS 520
> > > Box 746
> > > Baltimore MD 21203
> > >
> > > Voice: (410) 993 - 2096 Mornings; all-day voice-mail
> > > (410) 969 - 8068 Afternoons with answering machine
> > > FAX: (410) 993 - 8084 On-site
> > > (410) 969 - 8068 Afternoons; call first to arrange
> > > E-Mail:Mornings: [EMAIL PROTECTED]
> > > Afternoons: [EMAIL PROTECTED]
> > >
> > >
> > > At 03:58 PM 12/12/00 -0700, [EMAIL PROTECTED] wrote:
> > > >It's the motherboard design, not the chip. We get amazing performance
> > > >on some more integrated chips.
> > > >
> > > >On Tue, Dec 12, 2000 at 03:39:12PM -0500, [EMAIL PROTECTED]
> wrote:
> > > >>
> > > >> I've heard from many of you that x86 architecture is fundamentally
> limited
> > > >> to no better than a worst case interrupt latency of ~20us. Victor
> even
> > > >> alludes to this in his RTLinux White Paper. Does anyone know of a
> source I
> > > >> can reference that spells this out in detail with an explanation?
> > > >>
> > > >> -Chuck
> > > >>
> > > >> -- [rtl] ---
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> > > >> ---
> > > >> For more information on Real-Time Linux see:
> > > >> http://www.rtlinux.org/rtlinux/
> > > >
> > > >--
> > > >---------------------------------------------------------
> > > >Victor Yodaiken
> > > >Finite State Machine Labs: The RTLinux Company.
> > > > www.fsmlabs.com www.rtlinux.com
> > > >
> > > >-- [rtl] ---
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> > > >---
> > > >For more information on Real-Time Linux see:
> > > >http://www.rtlinux.org/rtlinux/
> > > >
> > > >
> >
> > --
> > ---------------------------------------------------------
> > Victor Yodaiken
> > Finite State Machine Labs: The RTLinux Company.
> > www.fsmlabs.com www.rtlinux.com
> >
> > -- [rtl] ---
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--
---------------------------------------------------------
Victor Yodaiken
Finite State Machine Labs: The RTLinux Company.
www.fsmlabs.com www.rtlinux.com
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---
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