[EMAIL PROTECTED] wrote:
>
> On Thu, Dec 14, 2000 at 10:50:33AM -0500, Victor Iannello wrote:
> > Paolo,
> >
> > Paolo,
> >
> > You are confirming what we suspected--the variation in time required to
> > access the timer is a symptom rather than the cause of the jitter. You
> > mention three possible causes at the hardware level--bus contention, DMA
> > steals, and cache disruption. We have done some experiments with the cache
> > turned off that have not improved jitter. So, we are probably at the
> > hardware limits of x86 board architecture. It never was designed for
> > cycle-by-cycle determinism.
>
> You might want to try, for example, the AMD SC520 board. The combination
> of board design and chip design makes all the difference sub 20us.
>
Does anyone know what the time cost is for a cache miss on a given
executable. I realize that this will vary greatly depending on
processor etc. What interests me is that a lot of the jitter problems
are associate with ISA/PCI bus etc, but I'd like to know what the worst
case contribution for a cache miss on an x86/ppc is.
Regards, Stuart
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