On Mon, Jan 15, 2001 at 08:05:56PM +0100, David Olofson wrote:
> Mon, 15 Jan 2001 [EMAIL PROTECTED] wrote:
> > On Mon, Jan 15, 2001 at 11:52:11AM +0100, David Olofson wrote:
> > > After all, the average Intel CPU these days has some 300,000+ cycles to fit
> > > each jiffy IRQ in at 1000 Hz, so it's not exactly as if you'd have to hand code
> > > the ISR in asm to get away with it! :-)
> >
> > Sadly enough, the interrupt hardware does not run at core speed!
>
> Still ISA speed legacy stuff... (Why? Who needs it on high end PCs these days
> anyway, especially considering that people are moving to entirey different
> platforms?)
Here's a cool fact: interrupt latencies on the 133MHz AMD ElanSC420 are
almost 2 times better than on my 700Mhz dual PIII.
I've come to the conclusion that people who design motherboards are
angry that they don't get to design the glamorous processor micro-architectures
etc. and so they try to sabotage the performance of processor cores.
Something like "let's see what happens when
your fancy out-of-order VLIW predictive scoreboard needs memory
and has to wait for me to route it through a emulation of a
Babbage Machine constructed from old cardboard during a rainstorm!"
>
> Anyway how much impact does this actually have on the number of CPU cycles
> wasted in a case such as the one we're discussing; a periodic interrupt? There
> are some port accesses, of course, and there will be some extra latency, but is
> there more to it?
There are two real problems: very slow I/O and off chip devices on critical
paths (e.g. why, why, why is there an 8259 emulator in a southbridge ?)
and an emphasis on getting throughput by predicting and pipelining
(e.g. we've filled the 90 stage pipeline by guessing through 4 branches and
have filled 80 prefetch buffers by predicting loads
and you want to have the processor now save all that and get around to
servicing an interrupt - referencing uncached data ?).
>
>
> //David
>
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