Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-13 Thread bharat gohil 
On Tue, Feb 13, 2018 at 3:53 PM, Jan Kiszka  wrote:

> On 2018-02-13 10:23, bharat gohil wrote:
> > >  Yes. In addition to that I had also observed in OrangePi PC2,
> > when
> > > jailhouse hit address which is belong to secure world then
> jailhouse
> > > hang and no output on console. After adjusting AFT address(in cell
> > > configuration), OrangePi PC2 start working well.
> >
> > How could jailhouse hit such an address?
> >
> >Many hardware has Trustzone address space controller or like hardware
> > which hide some portion of RAM or device from Normal world access.
> >
>
> Sure. But I was wondering which actual access Jailhouse should perform
> on that memory - except when you accidentally put its code right into
> that region.
>
   Yes.Only if you have not created proper hole in root cell.

>
> Jan
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
>



-- 
Regards,
Bharat Gohil
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bharat.go...@harman.com
+919427054633

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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-13 Thread Jan Kiszka 
On 2018-02-13 10:23, bharat gohil wrote:
> >  Yes. In addition to that I had also observed in OrangePi PC2,
> when
> > jailhouse hit address which is belong to secure world then jailhouse
> > hang and no output on console. After adjusting AFT address(in cell
> > configuration), OrangePi PC2 start working well.
> 
> How could jailhouse hit such an address?
> 
>    Many hardware has Trustzone address space controller or like hardware
> which hide some portion of RAM or device from Normal world access.
> 

Sure. But I was wondering which actual access Jailhouse should perform
on that memory - except when you accidentally put its code right into
that region.

Jan
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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-13 Thread bharat gohil 
On Tue, Feb 13, 2018 at 2:42 PM, Jan Kiszka  wrote:

> On 2018-02-13 10:05, bharat gohil wrote:
> >
> >
> > On Tue, Feb 13, 2018 at 2:11 PM, Jan Kiszka  > > wrote:
> >
> > On 2018-02-13 08:59, bharat gohil wrote:
> > >
> > >
> > > On Tue, Feb 13, 2018 at 12:58 PM, Jan Kiszka <
> jan.kis...@siemens.com 
> > > >>
> > wrote:
> > >
> > > On 2018-02-13 08:19, bharat gohil wrote:
> > > > Hi Jan,
> > > >
> > > > I tried your second method to bringdown core and check but
> > result are same,
> > > >
> > > > #cat /proc/cpuinfo
> > > > processor   : 0
> > > > BogoMIPS: 26.00
> > > > Features: fp asimd evtstrm aes pmull sha1 sha2 crc32
> > > > CPU implementer : 0x41
> > > > CPU architecture: 8
> > > > CPU variant : 0x0
> > > > CPU part: 0xd04
> > > > CPU revision: 1
> > > >
> > > > #jailhouse enable X.cell
> > > >
> > > > Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on
> > CPU 0
> > > > Code location: 0xc0200060
> > > > Page pool usage after early setup: mem 57/16356, remap
> 16/131072
> > > > Initializing processors:
> > > >  CPU 0... OK
> > > > Adding virtual PCI device 00:00.0 to cell "X"
> > > > Page pool usage after late setup: mem 62/16356, remap
> 21/131072
> > > > Activating hypervisor
> > >
> > > A lock-up, no more invalid access reports?
> > >
> > >There is no output and system hangs after "Activating
> hypervisor"
> > >
> > >
> > > What is core 0? What are cores 1 and 2? What happens when you
> > use those
> > > cores only?
> > >
> > >   Core 0 = A35
> > >   Core 1 = A35
> > >   Core 2 = A72
> > >   In above output i had bringdown Core 1(A35) and Core 2(A72) and
> Core
> > > 0(A35) is online and i have modified root cell config to  .cpus = {
> > > 0x1,} which Core 0(A35),
> > >
> >
> > I see. I suppose the A72 will not behave differently, but I would
> > quickly check that as well.
> >
> > >
> > > Make sure to analyze the issue systematically. We see a
> problem now that
> > > has a non-obvious cause.
> > >
> > >Yes.agree.
> > >To bringup Xen on this platform, I had done some modification
> in Xen.
> > > Let me debug issue in this context as well.
> > >
> >
> > Good to know, then there is hope.
> >
> > My current understanding of the situation is:
> > - we get an IABT on executing the first guest instruction after
> enabling
> >   Jailhouse
> > - that IABT means "page fault during stage-2 translation"
> > - the page table is created to contain 1:1 mapping for the faulting
> >   address to RAM with read/write/execute permissions
> >
> > And that may mean:
> > - the CPU does not like the page table entry for some reason
> > - the CPU has a problem with the page table hierarchy format in
> general
> > - the root pointer is not correct when entering EL1
> > - there are other reasons that stage-2 faults that could cause this
> >   abort (would contradict the ARM manual in my eyes)
> >
> >  Yes. In addition to that I had also observed in OrangePi PC2, when
> > jailhouse hit address which is belong to secure world then jailhouse
> > hang and no output on console. After adjusting AFT address(in cell
> > configuration), OrangePi PC2 start working well.
>
> How could jailhouse hit such an address?
>
   Many hardware has Trustzone address space controller or like hardware
which hide some portion of RAM or device from Normal world access.

>
> EL3 will likely get some fault then, and if that is not reflected back
> into the EL2, we will see such an effect.

   Yes.


> If the secure world is OSS,
> you could check the reaction on such faults.
>
   I think we can check in ATF.

>
> >  Let me debug/analyze problem more deeply and then I will get back.
> >
>
> OK.
>
> Jan
>
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
>



-- 
Regards,
Bharat Gohil
Sr.Software Engineer
bharat.go...@harman.com
+919427054633

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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-13 Thread Jan Kiszka 
On 2018-02-13 10:05, bharat gohil wrote:
> 
> 
> On Tue, Feb 13, 2018 at 2:11 PM, Jan Kiszka  > wrote:
> 
> On 2018-02-13 08:59, bharat gohil wrote:
> >
> >
> > On Tue, Feb 13, 2018 at 12:58 PM, Jan Kiszka  
> > >>
> wrote:
> >
> >     On 2018-02-13 08:19, bharat gohil wrote:
> >     > Hi Jan,
> >     >
> >     > I tried your second method to bringdown core and check but
> result are same,
> >     >
> >     > #cat /proc/cpuinfo
> >     > processor   : 0
> >     > BogoMIPS    : 26.00
> >     > Features    : fp asimd evtstrm aes pmull sha1 sha2 crc32
> >     > CPU implementer : 0x41
> >     > CPU architecture: 8
> >     > CPU variant : 0x0
> >     > CPU part    : 0xd04
> >     > CPU revision    : 1
> >     >
> >     > #jailhouse enable X.cell
> >     >
> >     > Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on
> CPU 0
> >     > Code location: 0xc0200060
> >     > Page pool usage after early setup: mem 57/16356, remap 16/131072
> >     > Initializing processors:
> >     >  CPU 0... OK
> >     > Adding virtual PCI device 00:00.0 to cell "X"
> >     > Page pool usage after late setup: mem 62/16356, remap 21/131072
> >     > Activating hypervisor
> >
> >     A lock-up, no more invalid access reports?
> >
> >    There is no output and system hangs after "Activating hypervisor"
> >
> >
> >     What is core 0? What are cores 1 and 2? What happens when you
> use those
> >     cores only?
> >
> >   Core 0 = A35
> >   Core 1 = A35
> >   Core 2 = A72
> >   In above output i had bringdown Core 1(A35) and Core 2(A72) and Core
> > 0(A35) is online and i have modified root cell config to  .cpus = {
> > 0x1,} which Core 0(A35),
> >
> 
> I see. I suppose the A72 will not behave differently, but I would
> quickly check that as well.
> 
> >
> >     Make sure to analyze the issue systematically. We see a problem now 
> that
> >     has a non-obvious cause.
> >
> >    Yes.agree.
> >    To bringup Xen on this platform, I had done some modification in Xen.
> > Let me debug issue in this context as well.
> >
> 
> Good to know, then there is hope.
> 
> My current understanding of the situation is:
> - we get an IABT on executing the first guest instruction after enabling
>   Jailhouse
> - that IABT means "page fault during stage-2 translation"
> - the page table is created to contain 1:1 mapping for the faulting
>   address to RAM with read/write/execute permissions
> 
> And that may mean:
> - the CPU does not like the page table entry for some reason
> - the CPU has a problem with the page table hierarchy format in general
> - the root pointer is not correct when entering EL1
> - there are other reasons that stage-2 faults that could cause this
>   abort (would contradict the ARM manual in my eyes)
> 
>  Yes. In addition to that I had also observed in OrangePi PC2, when
> jailhouse hit address which is belong to secure world then jailhouse
> hang and no output on console. After adjusting AFT address(in cell
> configuration), OrangePi PC2 start working well.

How could jailhouse hit such an address?

EL3 will likely get some fault then, and if that is not reflected back
into the EL2, we will see such an effect. If the secure world is OSS,
you could check the reaction on such faults.

>  Let me debug/analyze problem more deeply and then I will get back.
>  

OK.

Jan

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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-13 Thread Jan Kiszka 
On 2018-02-13 08:59, bharat gohil wrote:
> 
> 
> On Tue, Feb 13, 2018 at 12:58 PM, Jan Kiszka  > wrote:
> 
> On 2018-02-13 08:19, bharat gohil wrote:
> > Hi Jan,
> >
> > I tried your second method to bringdown core and check but result are 
> same,
> >
> > #cat /proc/cpuinfo
> > processor   : 0
> > BogoMIPS    : 26.00
> > Features    : fp asimd evtstrm aes pmull sha1 sha2 crc32
> > CPU implementer : 0x41
> > CPU architecture: 8
> > CPU variant : 0x0
> > CPU part    : 0xd04
> > CPU revision    : 1
> >
> > #jailhouse enable X.cell
> >
> > Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 0
> > Code location: 0xc0200060
> > Page pool usage after early setup: mem 57/16356, remap 16/131072
> > Initializing processors:
> >  CPU 0... OK
> > Adding virtual PCI device 00:00.0 to cell "X"
> > Page pool usage after late setup: mem 62/16356, remap 21/131072
> > Activating hypervisor
> 
> A lock-up, no more invalid access reports?
> 
>    There is no output and system hangs after "Activating hypervisor"
> 
> 
> What is core 0? What are cores 1 and 2? What happens when you use those
> cores only?
> 
>   Core 0 = A35
>   Core 1 = A35
>   Core 2 = A72
>   In above output i had bringdown Core 1(A35) and Core 2(A72) and Core
> 0(A35) is online and i have modified root cell config to  .cpus = {
> 0x1,} which Core 0(A35),
> 

I see. I suppose the A72 will not behave differently, but I would
quickly check that as well.

> 
> Make sure to analyze the issue systematically. We see a problem now that
> has a non-obvious cause.
> 
>    Yes.agree.
>    To bringup Xen on this platform, I had done some modification in Xen.
> Let me debug issue in this context as well.
> 

Good to know, then there is hope.

My current understanding of the situation is:
- we get an IABT on executing the first guest instruction after enabling
  Jailhouse
- that IABT means "page fault during stage-2 translation"
- the page table is created to contain 1:1 mapping for the faulting
  address to RAM with read/write/execute permissions

And that may mean:
- the CPU does not like the page table entry for some reason
- the CPU has a problem with the page table hierarchy format in general
- the root pointer is not correct when entering EL1
- there are other reasons that stage-2 faults that could cause this
  abort (would contradict the ARM manual in my eyes)

Jan

-- 
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Corporate Competence Center Embedded Linux

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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread bharat gohil 
On Tue, Feb 13, 2018 at 12:58 PM, Jan Kiszka  wrote:

> On 2018-02-13 08:19, bharat gohil wrote:
> > Hi Jan,
> >
> > I tried your second method to bringdown core and check but result are
> same,
> >
> > #cat /proc/cpuinfo
> > processor   : 0
> > BogoMIPS: 26.00
> > Features: fp asimd evtstrm aes pmull sha1 sha2 crc32
> > CPU implementer : 0x41
> > CPU architecture: 8
> > CPU variant : 0x0
> > CPU part: 0xd04
> > CPU revision: 1
> >
> > #jailhouse enable X.cell
> >
> > Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 0
> > Code location: 0xc0200060
> > Page pool usage after early setup: mem 57/16356, remap 16/131072
> > Initializing processors:
> >  CPU 0... OK
> > Adding virtual PCI device 00:00.0 to cell "X"
> > Page pool usage after late setup: mem 62/16356, remap 21/131072
> > Activating hypervisor
>
> A lock-up, no more invalid access reports?
>
   There is no output and system hangs after "Activating hypervisor"

>
> What is core 0? What are cores 1 and 2? What happens when you use those
> cores only?
>
  Core 0 = A35
  Core 1 = A35
  Core 2 = A72
  In above output i had bringdown Core 1(A35) and Core 2(A72) and Core
0(A35) is online and i have modified root cell config to  .cpus = { 0x1,}
which Core 0(A35),

>
> Make sure to analyze the issue systematically. We see a problem now that
> has a non-obvious cause.
>
   Yes.agree.
   To bringup Xen on this platform, I had done some modification in Xen.
Let me debug issue in this context as well.

>
> >
> > Can you please explain your first opinion ?/
> > You may filter out some uninteresting reports by adding "if (phys !=
> > 0x7c017000)" as
> > condition (that address is - in your build - the zero page where the
> > hypervisor regions gets mapped to for the root cell).
> >
>
> diff --git a/hypervisor/paging.c b/hypervisor/paging.c
> index b950a816..4149510f 100644
> --- a/hypervisor/paging.c
> +++ b/hypervisor/paging.c
> @@ -286,6 +286,8 @@ int paging_create(const struct paging_structures
> *pg_structs,
> virt &= PAGE_MASK;
> size = PAGE_ALIGN(size);
>
> +   if (phys != 0x7c017000)
> +   printk("%s: %p phys %lx size %lx virt %lx flags %lx\n",
> __func__, pg_structs, phys, size, virt, flags);
> while (size > 0) {
> const struct paging *paging = pg_structs->root_paging;
> page_table_t pt = pg_structs->root_table;
>
> Jan
>
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
>


-- 
Thanks,
Bharat Gohil
Sr.Software Engineer
bharat.go...@harman.com
+919427054633

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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread Jan Kiszka 
On 2018-02-13 08:19, bharat gohil wrote:
> Hi Jan,
> 
> I tried your second method to bringdown core and check but result are same,
> 
> #cat /proc/cpuinfo
> processor   : 0
> BogoMIPS    : 26.00
> Features    : fp asimd evtstrm aes pmull sha1 sha2 crc32
> CPU implementer : 0x41
> CPU architecture: 8
> CPU variant : 0x0
> CPU part    : 0xd04
> CPU revision    : 1
> 
> #jailhouse enable X.cell
> 
> Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 0
> Code location: 0xc0200060
> Page pool usage after early setup: mem 57/16356, remap 16/131072
> Initializing processors:
>  CPU 0... OK
> Adding virtual PCI device 00:00.0 to cell "X"
> Page pool usage after late setup: mem 62/16356, remap 21/131072
> Activating hypervisor

A lock-up, no more invalid access reports?

What is core 0? What are cores 1 and 2? What happens when you use those
cores only?

Make sure to analyze the issue systematically. We see a problem now that
has a non-obvious cause.

> 
> Can you please explain your first opinion ?/
> You may filter out some uninteresting reports by adding "if (phys !=
> 0x7c017000)" as
> condition (that address is - in your build - the zero page where the
> hypervisor regions gets mapped to for the root cell).
> 

diff --git a/hypervisor/paging.c b/hypervisor/paging.c
index b950a816..4149510f 100644
--- a/hypervisor/paging.c
+++ b/hypervisor/paging.c
@@ -286,6 +286,8 @@ int paging_create(const struct paging_structures 
*pg_structs,
virt &= PAGE_MASK;
size = PAGE_ALIGN(size);
 
+   if (phys != 0x7c017000)
+   printk("%s: %p phys %lx size %lx virt %lx flags %lx\n", 
__func__, pg_structs, phys, size, virt, flags);
while (size > 0) {
const struct paging *paging = pg_structs->root_paging;
page_table_t pt = pg_structs->root_table;

Jan

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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread bharat gohil 
Hi Jan,

I tried your second method to bringdown core and check but result are same,

#cat /proc/cpuinfo
processor   : 0
BogoMIPS: 26.00
Features: fp asimd evtstrm aes pmull sha1 sha2 crc32
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part: 0xd04
CPU revision: 1

#jailhouse enable X.cell

Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 0
Code location: 0xc0200060
Page pool usage after early setup: mem 57/16356, remap 16/131072
Initializing processors:
 CPU 0... OK
Adding virtual PCI device 00:00.0 to cell "X"
Page pool usage after late setup: mem 62/16356, remap 21/131072
Activating hypervisor

Can you please explain your first opinion ?




*You may filter out some uninteresting reports by adding "if (phys !=
0x7c017000)" as condition (that address is - in your build - the zero page
where the hypervisor regions gets mapped to for the root cell).*

Thanks,
Bharat


On Tue, Feb 13, 2018 at 12:29 PM, Jan Kiszka  wrote:

> On 2018-02-13 07:33, bharat gohil wrote:
> > Hi Jan,
> >
> > I took dump. pl. find attachment.
> > I don't know the side effect of printk, it not crashing but hangs after
> > "Activating hypervisor". I had try 4-5 time but it hangs everytime after
> > "Activating hypervisor"
>
> That output looks good and consistent now. I suppose the lock-up is
> related to the long delay that the printing implies. You may filter out
> some uninteresting reports by adding "if (phys != 0x7c017000)" as
> condition (that address is - in your build - the zero page where the
> hypervisor regions gets mapped to for the root cell).
>
> Maybe there is some subtle issue related to the cores. You have a board
> with 2 A35 and 1 A72 cores, right? How about confining the startup tests
> on one of each core types for now? You could bring the cores of the
> other type offline (echo 0 > /sys/devices/system/cpu/cpuX/online),
> adjust the config to only contain the online cores, and retry.
>
> Jan
>
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
>



-- 
Regards,
Bharat Gohil
Sr.Software Engineer
bharat.go...@harman.com
+919427054633

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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread bharat gohil 
I will check and provide you complete log

Thanks,
Bharat

On 12-Feb-2018 7:43 PM, "Jan Kiszka"  wrote:

> On 2018-02-12 14:31, bharat gohil wrote:
> > Jan,
> >
> > Please find attached log.
>
> Log doesn't look complete.
>
> Also, I bet my patch didn't hit the right line but rather went inside
> the while-loop in paging_create...
>
> Jan
>
> >
> > Thanks,
> > Bharat
> >
> > On Mon, Feb 12, 2018 at 4:53 PM, Jan Kiszka  > > wrote:
> >
> > On 2018-02-12 11:32, bharat gohil wrote:
> > > Hi Jan,
> > >
> > > Already tried this configuration(pl check attached config file)
> and I
> > > had also removed shared memory and PCI device but result are same,
> > > Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 2
> > > Code location: 0xc0200060
> > > Page pool usage after early setup: mem 61/16356, remap 48/131072
> > > Initializing processors:
> > >  CPU 2... OK
> > >  CPU 0... OK
> > >  CPU 1... OK
> > > Adding virtual PCI device 00:00.0 to cell "X"
> > > Page pool usage after late setup: mem 66/16356, remap 53/131072
> > > FATAL: instruction abort at 0x40f44ee8
> > >
> > > FATAL: unhandled trap (exception class 0x20)
> > > Cell state before exception:
> > >  pc: ff8000940ee8   lr: ff8000940ee8 spsr: 61c5 EL1
> > >  sp: ffc03be75f90  esr: 20 1 084
> > >  x0:    x1:    x2: 
> > >  x3:    x4:    x5: 
> > >  x6:    x7:    x8: 
> > >  x9:   x10:   x11: 
> > > x12:   x13:   x14: 
> > > x15:   x16:   x17: 
> > > x18:   x19: ff8000944910  x20: ff801000
> > > x21:   x22: 0001  x23: 0001
> > > x24: 0004  x25: ffc03be720a0  x26: ffc03be76090
> > > x27: ff8008d97000  x28: ffc0031e  x29: ffc03be75f90
> >
> > OK, let's try to debug this differently: Could you catch the output
> > during startup when this patch is applied?
> >
> > diff --git a/hypervisor/paging.c b/hypervisor/paging.c
> > index b950a816..80aa15a9 100644
> > --- a/hypervisor/paging.c
> > +++ b/hypervisor/paging.c
> > @@ -286,6 +286,7 @@ int paging_create(const struct paging_structures
> > *pg_structs,
> > virt &= PAGE_MASK;
> > size = PAGE_ALIGN(size);
> >
> > +   printk("%s: %p phys %lx size %lx virt %lx flags %lx\n",
> > __func__, pg_structs, phys, size, virt, flags);
> > while (size > 0) {
> > const struct paging *paging =
> pg_structs->root_paging;
> > page_table_t pt = pg_structs->root_table;
> >
> > Jan
> >
> > --
> > Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> > Corporate Competence Center Embedded Linux
> >
> >
> >
> >
> > --
> > Regards,
> > Bharat Gohil
> > Sr.Software Engineer
> > bharat.go...@harman.com 
> > +919427054633
>
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
>

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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread Jan Kiszka 
On 2018-02-12 14:31, bharat gohil wrote:
> Jan,
> 
> Please find attached log.

Log doesn't look complete.

Also, I bet my patch didn't hit the right line but rather went inside
the while-loop in paging_create...

Jan

> 
> Thanks,
> Bharat
> 
> On Mon, Feb 12, 2018 at 4:53 PM, Jan Kiszka  > wrote:
> 
> On 2018-02-12 11:32, bharat gohil wrote:
> > Hi Jan,
> >
> > Already tried this configuration(pl check attached config file) and I
> > had also removed shared memory and PCI device but result are same,
> > Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 2
> > Code location: 0xc0200060
> > Page pool usage after early setup: mem 61/16356, remap 48/131072
> > Initializing processors:
> >  CPU 2... OK
> >  CPU 0... OK
> >  CPU 1... OK
> > Adding virtual PCI device 00:00.0 to cell "X"
> > Page pool usage after late setup: mem 66/16356, remap 53/131072
> > FATAL: instruction abort at 0x40f44ee8
> >
> > FATAL: unhandled trap (exception class 0x20)
> > Cell state before exception:
> >  pc: ff8000940ee8   lr: ff8000940ee8 spsr: 61c5     EL1
> >  sp: ffc03be75f90  esr: 20 1 084
> >  x0:    x1:    x2: 
> >  x3:    x4:    x5: 
> >  x6:    x7:    x8: 
> >  x9:   x10:   x11: 
> > x12:   x13:   x14: 
> > x15:   x16:   x17: 
> > x18:   x19: ff8000944910  x20: ff801000
> > x21:   x22: 0001  x23: 0001
> > x24: 0004  x25: ffc03be720a0  x26: ffc03be76090
> > x27: ff8008d97000  x28: ffc0031e  x29: ffc03be75f90
> 
> OK, let's try to debug this differently: Could you catch the output
> during startup when this patch is applied?
> 
> diff --git a/hypervisor/paging.c b/hypervisor/paging.c
> index b950a816..80aa15a9 100644
> --- a/hypervisor/paging.c
> +++ b/hypervisor/paging.c
> @@ -286,6 +286,7 @@ int paging_create(const struct paging_structures
> *pg_structs,
>         virt &= PAGE_MASK;
>         size = PAGE_ALIGN(size);
> 
> +       printk("%s: %p phys %lx size %lx virt %lx flags %lx\n",
> __func__, pg_structs, phys, size, virt, flags);
>         while (size > 0) {
>                 const struct paging *paging = pg_structs->root_paging;
>                 page_table_t pt = pg_structs->root_table;
> 
> Jan
> 
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
> 
> 
> 
> 
> -- 
> Regards,
> Bharat Gohil
> Sr.Software Engineer
> bharat.go...@harman.com 
> +919427054633

-- 
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Corporate Competence Center Embedded Linux

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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread bharat gohil 
Jan,

Please find attached log.

Thanks,
Bharat

On Mon, Feb 12, 2018 at 4:53 PM, Jan Kiszka  wrote:

> On 2018-02-12 11:32, bharat gohil wrote:
> > Hi Jan,
> >
> > Already tried this configuration(pl check attached config file) and I
> > had also removed shared memory and PCI device but result are same,
> > Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 2
> > Code location: 0xc0200060
> > Page pool usage after early setup: mem 61/16356, remap 48/131072
> > Initializing processors:
> >  CPU 2... OK
> >  CPU 0... OK
> >  CPU 1... OK
> > Adding virtual PCI device 00:00.0 to cell "X"
> > Page pool usage after late setup: mem 66/16356, remap 53/131072
> > FATAL: instruction abort at 0x40f44ee8
> >
> > FATAL: unhandled trap (exception class 0x20)
> > Cell state before exception:
> >  pc: ff8000940ee8   lr: ff8000940ee8 spsr: 61c5 EL1
> >  sp: ffc03be75f90  esr: 20 1 084
> >  x0:    x1:    x2: 
> >  x3:    x4:    x5: 
> >  x6:    x7:    x8: 
> >  x9:   x10:   x11: 
> > x12:   x13:   x14: 
> > x15:   x16:   x17: 
> > x18:   x19: ff8000944910  x20: ff801000
> > x21:   x22: 0001  x23: 0001
> > x24: 0004  x25: ffc03be720a0  x26: ffc03be76090
> > x27: ff8008d97000  x28: ffc0031e  x29: ffc03be75f90
>
> OK, let's try to debug this differently: Could you catch the output
> during startup when this patch is applied?
>
> diff --git a/hypervisor/paging.c b/hypervisor/paging.c
> index b950a816..80aa15a9 100644
> --- a/hypervisor/paging.c
> +++ b/hypervisor/paging.c
> @@ -286,6 +286,7 @@ int paging_create(const struct paging_structures
> *pg_structs,
> virt &= PAGE_MASK;
> size = PAGE_ALIGN(size);
>
> +   printk("%s: %p phys %lx size %lx virt %lx flags %lx\n", __func__,
> pg_structs, phys, size, virt, flags);
> while (size > 0) {
> const struct paging *paging = pg_structs->root_paging;
> page_table_t pt = pg_structs->root_table;
>
> Jan
>
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
>



-- 
Regards,
Bharat Gohil
Sr.Software Engineer
bharat.go...@harman.com
+919427054633

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...
...
...
paging_create: 0xc021a000 phys 4000 size 300 virt 4000 
flags 4fd
paging_create: 0xc021a000 phys 4020 size 2e0 virt 4020 
flags 4fd
paging_create: 0xc021a000 phys 4040 size 2c0 virt 4040 
flags 4fd
paging_create: 0xc021a000 phys 4060 size 2a0 virt 4060 
flags 4fd
paging_create: 0xc021a000 phys 4080 size 280 virt 4080 
flags 4fd
paging_create: 0xc021a000 phys 40a0 size 260 virt 40a0 
flags 4fd
paging_create: 0xc021a000 phys 40c0 size 240 virt 40c0 
flags 4fd
paging_create: 0xc021a000 phys 40e0 size 220 virt 40e0 
flags 4fd
paging_create: 0xc021a000 phys 4100 size 200 virt 4100 
flags 4fd
paging_create: 0xc021a000 phys 4120 size 1e0 virt 4120 
flags 4fd
paging_create: 0xc021a000 phys 4140 size 1c0 virt 4140 
flags 4fd
paging_create: 0xc021a000 phys 4160 size 1a0 virt 4160 
flags 4fd
paging_create: 0xc021a000 phys 4180 size 180 virt 4180 
flags 4fd
paging_create: 0xc021a000 phys 41a0 size 160 virt 41a0 
flags 4fd
paging_create: 0xc021a000 phys 41c0 size 140 virt 41c0 
flags 4fd
paging_create: 0xc021a000 phys 41e0 size 120 virt 41e0 
flags 4fd
paging_create: 0xc021a000 phys 4200 size 100 virt 4200 
flags 4fd
paging_create: 0xc021a000 phys 4220 size e0 virt 4220 flags 
4fd
paging_create: 0xc021a000 phys 4240 size c0 virt 4240 flags 
4fd
paging_create: 0xc021a000 phys 4260 size a0 virt 4260 flags 
4fd
paging_create: 0xc021a000 phys 4280 size 80 virt 4280 flags 
4fd
paging_create: 0xc021a000 phys 42a0 size 60 virt 42a0 flags 
4fd
paging_create: 0xc021a000 phys 42c0 size 40 virt 42c0 flags 
4fd
paging_create: 0xc021a000 phys 42e0 size 20 virt 42e0 flags 
4fd
paging_create:

Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread Jan Kiszka 
On 2018-02-12 11:32, bharat gohil wrote:
> Hi Jan,
> 
> Already tried this configuration(pl check attached config file) and I
> had also removed shared memory and PCI device but result are same,
> Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 2
> Code location: 0xc0200060
> Page pool usage after early setup: mem 61/16356, remap 48/131072
> Initializing processors:
>  CPU 2... OK
>  CPU 0... OK
>  CPU 1... OK
> Adding virtual PCI device 00:00.0 to cell "X"
> Page pool usage after late setup: mem 66/16356, remap 53/131072
> FATAL: instruction abort at 0x40f44ee8
> 
> FATAL: unhandled trap (exception class 0x20)
> Cell state before exception:
>  pc: ff8000940ee8   lr: ff8000940ee8 spsr: 61c5     EL1
>  sp: ffc03be75f90  esr: 20 1 084
>  x0:    x1:    x2: 
>  x3:    x4:    x5: 
>  x6:    x7:    x8: 
>  x9:   x10:   x11: 
> x12:   x13:   x14: 
> x15:   x16:   x17: 
> x18:   x19: ff8000944910  x20: ff801000
> x21:   x22: 0001  x23: 0001
> x24: 0004  x25: ffc03be720a0  x26: ffc03be76090
> x27: ff8008d97000  x28: ffc0031e  x29: ffc03be75f90

OK, let's try to debug this differently: Could you catch the output
during startup when this patch is applied?

diff --git a/hypervisor/paging.c b/hypervisor/paging.c
index b950a816..80aa15a9 100644
--- a/hypervisor/paging.c
+++ b/hypervisor/paging.c
@@ -286,6 +286,7 @@ int paging_create(const struct paging_structures 
*pg_structs,
virt &= PAGE_MASK;
size = PAGE_ALIGN(size);
 
+   printk("%s: %p phys %lx size %lx virt %lx flags %lx\n", __func__, 
pg_structs, phys, size, virt, flags);
while (size > 0) {
const struct paging *paging = pg_structs->root_paging;
page_table_t pt = pg_structs->root_table;

Jan

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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread bharat gohil 
Hi Jan,

Already tried this configuration(pl check attached config file) and I had
also removed shared memory and PCI device but result are same,
Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 2
Code location: 0xc0200060
Page pool usage after early setup: mem 61/16356, remap 48/131072
Initializing processors:
 CPU 2... OK
 CPU 0... OK
 CPU 1... OK
Adding virtual PCI device 00:00.0 to cell "X"
Page pool usage after late setup: mem 66/16356, remap 53/131072
FATAL: instruction abort at 0x40f44ee8

FATAL: unhandled trap (exception class 0x20)
Cell state before exception:
 pc: ff8000940ee8   lr: ff8000940ee8 spsr: 61c5 EL1
 sp: ffc03be75f90  esr: 20 1 084
 x0:    x1:    x2: 
 x3:    x4:    x5: 
 x6:    x7:    x8: 
 x9:   x10:   x11: 
x12:   x13:   x14: 
x15:   x16:   x17: 
x18:   x19: ff8000944910  x20: ff801000
x21:   x22: 0001  x23: 0001
x24: 0004  x25: ffc03be720a0  x26: ffc03be76090
x27: ff8008d97000  x28: ffc0031e  x29: ffc03be75f90


On Mon, Feb 12, 2018 at 3:28 PM, Jan Kiszka  wrote:

> On 2018-02-12 10:18, Henning Schild wrote:
> > Am Mon, 12 Feb 2018 14:38:29 +0530
> > schrieb bharat gohil :
> >
> >> Hi Jan,
> >>
> >> I had modified root cell configuration as per your suggestion.
> >> I got following error,
> >>
> >> Adding virtual PCI device 00:00.0 to cell "X"
> >> /media/bgohil/data_ssd/virtualization/jailhouse/
> hypervisor/ivshmem.c:330:
> >> returning error -EINVAL
> >> JAILHOUSE_ENABLE: Invalid argument
> >
> > You specified 7 memory regions and the array just has 6 entries, you
>
> One is commented out, 6 is correct.
>
> shmem_region is wrong: 5 is the last index in mem-regions.
>
> Jan
>
> > most likely even got a compiler warning about that.
> > Now your index 6 is out of the array, have a look at
> > hypervisor/ivshmem.c:330.
> >
> > Henning
> >
> >> Please find attached cell configuration file
> >> Thanks,
> >> Bharat
> >>
> >> On Mon, Feb 12, 2018 at 12:35 PM, Jan Kiszka 
> >> wrote:
> >>
> >>> On 2018-02-12 05:53, bharat gohil wrote:
>  Hello Jan,
> 
>  Please find attached root cell config file.
> >>>
>  /*
>   * Jailhouse, a Linux-based partitioning hypervisor
>   *
>   * Test configuration for X (2-Cortex-A72, 4-Cortex-A35, 2GB
>  RAM) *
>   * Copyright (c) Siemens AG, 2014-2016
>   *
>   * Authors:
>   *  Jan Kiszka 
>   *
>   * This work is licensed under the terms of the GNU GPL, version
>  2.  See
>   * the COPYING file in the top-level directory.
>   */
> 
>  #include 
>  #include 
> 
>  #define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
> 
>  struct {
>    struct jailhouse_system header;
>    __u64 cpus[1];
>    struct jailhouse_memory mem_regions[8];
> >>>
> >>> You are preparing for 8 regions here, but only 6 are initialized
> >>> below. First thing to fix.
> >>>
>    struct jailhouse_irqchip irqchips[1];
>    struct jailhouse_pci_device pci_devices[1];
>  } __attribute__((packed)) config = {
>    .header = {
>    .signature = JAILHOUSE_SYSTEM_SIGNATURE,
>    .revision = JAILHOUSE_CONFIG_REVISION,
>    .hypervisor_memory = {
>    .phys_start = 0x7C00,
>    .size = 0x400,
>    },
>    .debug_console = {
>    .address = 0x11002000,
>    .size = 0x1000,
>    .flags = JAILHOUSE_CON1_TYPE_8250 |
> JAILHOUSE_CON1_ACCESS_MMIO |
> JAILHOUSE_CON1_REGDIST_4 |
> JAILHOUSE_CON2_TYPE_ROOTPAGE,
>    },
>    .platform_info = {
>    .pci_mmconfig_base = 0x200,
>    .pci_mmconfig_end_bus = 0,
>    .pci_is_virtual = 1,
>    .arm = {
>    .gic_version = 2,
>    .gicd_base = 0x1051,
>    .gicc_base = 0x1052,
>    .gich_base = 0x1054,
>    .gicv_base = 0x1056,
>    .maintenance_irq = 25,
>    },
>    },
>    .root_cell = {
>

Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread Jan Kiszka 
On 2018-02-12 10:18, Henning Schild wrote:
> Am Mon, 12 Feb 2018 14:38:29 +0530
> schrieb bharat gohil :
> 
>> Hi Jan,
>>
>> I had modified root cell configuration as per your suggestion.
>> I got following error,
>>
>> Adding virtual PCI device 00:00.0 to cell "X"
>> /media/bgohil/data_ssd/virtualization/jailhouse/hypervisor/ivshmem.c:330:
>> returning error -EINVAL
>> JAILHOUSE_ENABLE: Invalid argument
> 
> You specified 7 memory regions and the array just has 6 entries, you

One is commented out, 6 is correct.

shmem_region is wrong: 5 is the last index in mem-regions.

Jan

> most likely even got a compiler warning about that.
> Now your index 6 is out of the array, have a look at 
> hypervisor/ivshmem.c:330.
> 
> Henning
> 
>> Please find attached cell configuration file
>> Thanks,
>> Bharat
>>
>> On Mon, Feb 12, 2018 at 12:35 PM, Jan Kiszka 
>> wrote:
>>
>>> On 2018-02-12 05:53, bharat gohil wrote:  
 Hello Jan,

 Please find attached root cell config file.  
>>>  
 /*
  * Jailhouse, a Linux-based partitioning hypervisor
  *
  * Test configuration for X (2-Cortex-A72, 4-Cortex-A35, 2GB
 RAM) *
  * Copyright (c) Siemens AG, 2014-2016
  *
  * Authors:
  *  Jan Kiszka 
  *
  * This work is licensed under the terms of the GNU GPL, version
 2.  See
  * the COPYING file in the top-level directory.
  */

 #include 
 #include 

 #define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])

 struct {
   struct jailhouse_system header;
   __u64 cpus[1];
   struct jailhouse_memory mem_regions[8];  
>>>
>>> You are preparing for 8 regions here, but only 6 are initialized
>>> below. First thing to fix.
>>>  
   struct jailhouse_irqchip irqchips[1];
   struct jailhouse_pci_device pci_devices[1];
 } __attribute__((packed)) config = {
   .header = {
   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
   .revision = JAILHOUSE_CONFIG_REVISION,
   .hypervisor_memory = {
   .phys_start = 0x7C00,
   .size = 0x400,
   },
   .debug_console = {
   .address = 0x11002000,
   .size = 0x1000,
   .flags = JAILHOUSE_CON1_TYPE_8250 |
JAILHOUSE_CON1_ACCESS_MMIO |
JAILHOUSE_CON1_REGDIST_4 |
JAILHOUSE_CON2_TYPE_ROOTPAGE,
   },
   .platform_info = {
   .pci_mmconfig_base = 0x200,
   .pci_mmconfig_end_bus = 0,
   .pci_is_virtual = 1,
   .arm = {
   .gic_version = 2,
   .gicd_base = 0x1051,
   .gicc_base = 0x1052,
   .gich_base = 0x1054,
   .gicv_base = 0x1056,
   .maintenance_irq = 25,
   },
   },
   .root_cell = {
   .name = "X",

   .cpu_set_size = sizeof(config.cpus),
   .num_memory_regions =  
>>> ARRAY_SIZE(config.mem_regions),  
   .num_irqchips = ARRAY_SIZE(config.irqchips),
   .num_pci_devices =
 ARRAY_SIZE(config.pci_devices),

   .vpci_irq_base = 108,
   },
   },

   .cpus = {
   0x3F,
   },

   .mem_regions = {
   /* CCU */ {
 .phys_start = 0x1000,
 .virt_start = 0x1000,
 .size = 0x200,
 .flags = JAILHOUSE_MEM_READ |  
>>> JAILHOUSE_MEM_WRITE |  
 JAILHOUSE_MEM_IO |
 JAILHOUSE_MEM_IO_32, },
   /* MMIO 1 (permissive) */ {
   .phys_start = 0x1300,
   .virt_start = 0x1300,
   .size =  0x400,
   .flags = JAILHOUSE_MEM_READ |
 JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
   },
   /* pinctrl PA */ {
   .phys_start = 0x1800,
   .virt_start = 0x1800,
   .size = 0x200,
   .flags = JAILHOUSE_MEM_READ |
 JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
   },
   /* RAM */ {
   .phys_start =

Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread bharat gohil 
Hi Schild,

I have tried 7 region and it gave me same type of exception as it was
giving but address of exception change after size increase by 1(as
suggested by Jan)  like,

FATAL: instruction abort at 0x40f44ee8

FATAL: unhandled trap (exception class 0x20)
Cell state before exception:
 pc: ff8000940ee8   lr: ff8000940ee8 spsr: 61c5 EL1
 sp: ffc03be5ff90  esr: 20 1 084
 x0:    x1:    x2: 
 x3:    x4:    x5: 
 x6:    x7:    x8: 
 x9:   x10:   x11: 
x12:   x13:   x14: 
x15:   x16:   x17: 
x18:   x19: ff8000944910  x20: ff801000
x21:   x22: 0001  x23: 
x24: 0004  x25: ffc03be5c0a0  x26: ffc03be60090
x27: ff8008d97000  x28: ff8008d9  x29: ffc03be5ff90

Parking CPU 0 (Cell: "X")
FATAL: instruction abort at 0x0

FATAL: unhandled trap (exception class 0x20)
Cell state before exception:
 pc:    lr:  spsr: 03c5 EL1
 sp:   esr: 20 1 004
 x0:    x1:    x2: 
 x3:    x4:    x5: 
 x6:    x7:    x8: 
 x9:   x10:   x11: 
x12:   x13:   x14: 
x15:   x16:   x17: 
x18:   x19:   x20: 
x21:   x22:   x23: 
x24:   x25:   x26: 
x27:   x28:   x29: 

.
.(continues print)


Thanks,
Bharat


On Mon, Feb 12, 2018 at 2:48 PM, Henning Schild 
wrote:

> Am Mon, 12 Feb 2018 14:38:29 +0530
> schrieb bharat gohil :
>
> > Hi Jan,
> >
> > I had modified root cell configuration as per your suggestion.
> > I got following error,
> >
> > Adding virtual PCI device 00:00.0 to cell "X"
> > /media/bgohil/data_ssd/virtualization/jailhouse/
> hypervisor/ivshmem.c:330:
> > returning error -EINVAL
> > JAILHOUSE_ENABLE: Invalid argument
>
> You specified 7 memory regions and the array just has 6 entries, you
> most likely even got a compiler warning about that.
> Now your index 6 is out of the array, have a look at
> hypervisor/ivshmem.c:330.
>
> Henning
>
> > Please find attached cell configuration file
> > Thanks,
> > Bharat
> >
> > On Mon, Feb 12, 2018 at 12:35 PM, Jan Kiszka 
> > wrote:
> >
> > > On 2018-02-12 05:53, bharat gohil wrote:
> > > > Hello Jan,
> > > >
> > > > Please find attached root cell config file.
> > >
> > > > /*
> > > >  * Jailhouse, a Linux-based partitioning hypervisor
> > > >  *
> > > >  * Test configuration for X (2-Cortex-A72, 4-Cortex-A35, 2GB
> > > > RAM) *
> > > >  * Copyright (c) Siemens AG, 2014-2016
> > > >  *
> > > >  * Authors:
> > > >  *  Jan Kiszka 
> > > >  *
> > > >  * This work is licensed under the terms of the GNU GPL, version
> > > > 2.  See
> > > >  * the COPYING file in the top-level directory.
> > > >  */
> > > >
> > > > #include 
> > > > #include 
> > > >
> > > > #define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
> > > >
> > > > struct {
> > > >   struct jailhouse_system header;
> > > >   __u64 cpus[1];
> > > >   struct jailhouse_memory mem_regions[8];
> > >
> > > You are preparing for 8 regions here, but only 6 are initialized
> > > below. First thing to fix.
> > >
> > > >   struct jailhouse_irqchip irqchips[1];
> > > >   struct jailhouse_pci_device pci_devices[1];
> > > > } __attribute__((packed)) config = {
> > > >   .header = {
> > > >   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
> > > >   .revision = JAILHOUSE_CONFIG_REVISION,
> > > >   .hypervisor_memory = {
> > > >   .phys_start = 0x7C00,
> > > >   .size = 0x400,
> > > >   },
> > > >   .debug_console = {
> > > >   .address = 0x11002000,
> > > >   .size = 0x1000,
> > > >   .flags = JAILHOUSE_CON1_TYPE_8250 |
> > > >JAILHOUSE_CON1_ACCESS_MMIO |
> > > >JAILHOUSE_CON1_REGDIST_4 |
> > > >JAILHOUSE_CON2_TYPE_ROOTPAGE,
> > > >   },
> > > >   .platform_info = {
> > > >   .pci_mmconfig_base = 0x200,
> > > >   .pci_mmconfig_end_bus = 0,
> > > >

Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread Henning Schild 
Am Mon, 12 Feb 2018 14:38:29 +0530
schrieb bharat gohil :

> Hi Jan,
> 
> I had modified root cell configuration as per your suggestion.
> I got following error,
> 
> Adding virtual PCI device 00:00.0 to cell "X"
> /media/bgohil/data_ssd/virtualization/jailhouse/hypervisor/ivshmem.c:330:
> returning error -EINVAL
> JAILHOUSE_ENABLE: Invalid argument

You specified 7 memory regions and the array just has 6 entries, you
most likely even got a compiler warning about that.
Now your index 6 is out of the array, have a look at 
hypervisor/ivshmem.c:330.

Henning

> Please find attached cell configuration file
> Thanks,
> Bharat
> 
> On Mon, Feb 12, 2018 at 12:35 PM, Jan Kiszka 
> wrote:
> 
> > On 2018-02-12 05:53, bharat gohil wrote:  
> > > Hello Jan,
> > >
> > > Please find attached root cell config file.  
> >  
> > > /*
> > >  * Jailhouse, a Linux-based partitioning hypervisor
> > >  *
> > >  * Test configuration for X (2-Cortex-A72, 4-Cortex-A35, 2GB
> > > RAM) *
> > >  * Copyright (c) Siemens AG, 2014-2016
> > >  *
> > >  * Authors:
> > >  *  Jan Kiszka 
> > >  *
> > >  * This work is licensed under the terms of the GNU GPL, version
> > > 2.  See
> > >  * the COPYING file in the top-level directory.
> > >  */
> > >
> > > #include 
> > > #include 
> > >
> > > #define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
> > >
> > > struct {
> > >   struct jailhouse_system header;
> > >   __u64 cpus[1];
> > >   struct jailhouse_memory mem_regions[8];  
> >
> > You are preparing for 8 regions here, but only 6 are initialized
> > below. First thing to fix.
> >  
> > >   struct jailhouse_irqchip irqchips[1];
> > >   struct jailhouse_pci_device pci_devices[1];
> > > } __attribute__((packed)) config = {
> > >   .header = {
> > >   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
> > >   .revision = JAILHOUSE_CONFIG_REVISION,
> > >   .hypervisor_memory = {
> > >   .phys_start = 0x7C00,
> > >   .size = 0x400,
> > >   },
> > >   .debug_console = {
> > >   .address = 0x11002000,
> > >   .size = 0x1000,
> > >   .flags = JAILHOUSE_CON1_TYPE_8250 |
> > >JAILHOUSE_CON1_ACCESS_MMIO |
> > >JAILHOUSE_CON1_REGDIST_4 |
> > >JAILHOUSE_CON2_TYPE_ROOTPAGE,
> > >   },
> > >   .platform_info = {
> > >   .pci_mmconfig_base = 0x200,
> > >   .pci_mmconfig_end_bus = 0,
> > >   .pci_is_virtual = 1,
> > >   .arm = {
> > >   .gic_version = 2,
> > >   .gicd_base = 0x1051,
> > >   .gicc_base = 0x1052,
> > >   .gich_base = 0x1054,
> > >   .gicv_base = 0x1056,
> > >   .maintenance_irq = 25,
> > >   },
> > >   },
> > >   .root_cell = {
> > >   .name = "X",
> > >
> > >   .cpu_set_size = sizeof(config.cpus),
> > >   .num_memory_regions =  
> > ARRAY_SIZE(config.mem_regions),  
> > >   .num_irqchips = ARRAY_SIZE(config.irqchips),
> > >   .num_pci_devices =
> > > ARRAY_SIZE(config.pci_devices),
> > >
> > >   .vpci_irq_base = 108,
> > >   },
> > >   },
> > >
> > >   .cpus = {
> > >   0x3F,
> > >   },
> > >
> > >   .mem_regions = {
> > >   /* CCU */ {
> > > .phys_start = 0x1000,
> > > .virt_start = 0x1000,
> > > .size = 0x200,
> > > .flags = JAILHOUSE_MEM_READ |  
> > JAILHOUSE_MEM_WRITE |  
> > > JAILHOUSE_MEM_IO |
> > > JAILHOUSE_MEM_IO_32, },
> > >   /* MMIO 1 (permissive) */ {
> > >   .phys_start = 0x1300,
> > >   .virt_start = 0x1300,
> > >   .size =  0x400,
> > >   .flags = JAILHOUSE_MEM_READ |
> > > JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
> > >   },
> > >   /* pinctrl PA */ {
> > >   .phys_start = 0x1800,
> > >   .virt_start = 0x1800,
> > >   .size = 0x200,
> > >   .flags = JAILHOUSE_MEM_READ |
> > > JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
> > >   },
> > >   /* RAM */ {
> > >   .phys_start = 0x4000,
> > >   .virt_start = 0x4000,
> > >

Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-12 Thread bharat gohil 
Hi Jan,

I had modified root cell configuration as per your suggestion.
I got following error,

Adding virtual PCI device 00:00.0 to cell "X"
/media/bgohil/data_ssd/virtualization/jailhouse/hypervisor/ivshmem.c:330:
returning error -EINVAL
JAILHOUSE_ENABLE: Invalid argument

Please find attached cell configuration file
Thanks,
Bharat

On Mon, Feb 12, 2018 at 12:35 PM, Jan Kiszka  wrote:

> On 2018-02-12 05:53, bharat gohil wrote:
> > Hello Jan,
> >
> > Please find attached root cell config file.
>
> > /*
> >  * Jailhouse, a Linux-based partitioning hypervisor
> >  *
> >  * Test configuration for X (2-Cortex-A72, 4-Cortex-A35, 2GB RAM)
> >  *
> >  * Copyright (c) Siemens AG, 2014-2016
> >  *
> >  * Authors:
> >  *  Jan Kiszka 
> >  *
> >  * This work is licensed under the terms of the GNU GPL, version 2.  See
> >  * the COPYING file in the top-level directory.
> >  */
> >
> > #include 
> > #include 
> >
> > #define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
> >
> > struct {
> >   struct jailhouse_system header;
> >   __u64 cpus[1];
> >   struct jailhouse_memory mem_regions[8];
>
> You are preparing for 8 regions here, but only 6 are initialized below.
> First thing to fix.
>
> >   struct jailhouse_irqchip irqchips[1];
> >   struct jailhouse_pci_device pci_devices[1];
> > } __attribute__((packed)) config = {
> >   .header = {
> >   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
> >   .revision = JAILHOUSE_CONFIG_REVISION,
> >   .hypervisor_memory = {
> >   .phys_start = 0x7C00,
> >   .size = 0x400,
> >   },
> >   .debug_console = {
> >   .address = 0x11002000,
> >   .size = 0x1000,
> >   .flags = JAILHOUSE_CON1_TYPE_8250 |
> >JAILHOUSE_CON1_ACCESS_MMIO |
> >JAILHOUSE_CON1_REGDIST_4 |
> >JAILHOUSE_CON2_TYPE_ROOTPAGE,
> >   },
> >   .platform_info = {
> >   .pci_mmconfig_base = 0x200,
> >   .pci_mmconfig_end_bus = 0,
> >   .pci_is_virtual = 1,
> >   .arm = {
> >   .gic_version = 2,
> >   .gicd_base = 0x1051,
> >   .gicc_base = 0x1052,
> >   .gich_base = 0x1054,
> >   .gicv_base = 0x1056,
> >   .maintenance_irq = 25,
> >   },
> >   },
> >   .root_cell = {
> >   .name = "X",
> >
> >   .cpu_set_size = sizeof(config.cpus),
> >   .num_memory_regions =
> ARRAY_SIZE(config.mem_regions),
> >   .num_irqchips = ARRAY_SIZE(config.irqchips),
> >   .num_pci_devices = ARRAY_SIZE(config.pci_devices),
> >
> >   .vpci_irq_base = 108,
> >   },
> >   },
> >
> >   .cpus = {
> >   0x3F,
> >   },
> >
> >   .mem_regions = {
> >   /* CCU */ {
> > .phys_start = 0x1000,
> > .virt_start = 0x1000,
> > .size = 0x200,
> > .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE |
> > JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
> > },
> >   /* MMIO 1 (permissive) */ {
> >   .phys_start = 0x1300,
> >   .virt_start = 0x1300,
> >   .size =  0x400,
> >   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
> >   JAILHOUSE_MEM_IO,
> >   },
> >   /* pinctrl PA */ {
> >   .phys_start = 0x1800,
> >   .virt_start = 0x1800,
> >   .size = 0x200,
> >   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
> >   JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
> >   },
> >   /* RAM */ {
> >   .phys_start = 0x4000,
> >   .virt_start = 0x4000,
> >   .size =0x02FF,
>
> This switches the region in to sub-page mode, and that may cause this
> surprising behavior. Just do size + 1, as it is correct.
>
> >   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE
> | JAILHOUSE_MEM_EXECUTE,
> >   },
> >/* RAM*/  /*{
> > .phys_start = 0x40EC,
> > .virt_start = 0x40EC,
> > .size =

Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-11 Thread Jan Kiszka 
On 2018-02-12 05:53, bharat gohil wrote:
> Hello Jan,
> 
> Please find attached root cell config file.

> /*
>  * Jailhouse, a Linux-based partitioning hypervisor
>  *
>  * Test configuration for X (2-Cortex-A72, 4-Cortex-A35, 2GB RAM)
>  *
>  * Copyright (c) Siemens AG, 2014-2016
>  *
>  * Authors:
>  *  Jan Kiszka 
>  *
>  * This work is licensed under the terms of the GNU GPL, version 2.  See
>  * the COPYING file in the top-level directory.
>  */
> 
> #include 
> #include 
> 
> #define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
> 
> struct {
>   struct jailhouse_system header;
>   __u64 cpus[1];
>   struct jailhouse_memory mem_regions[8];

You are preparing for 8 regions here, but only 6 are initialized below.
First thing to fix.

>   struct jailhouse_irqchip irqchips[1];
>   struct jailhouse_pci_device pci_devices[1];
> } __attribute__((packed)) config = {
>   .header = {
>   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
>   .revision = JAILHOUSE_CONFIG_REVISION,
>   .hypervisor_memory = {
>   .phys_start = 0x7C00,
>   .size = 0x400,
>   },
>   .debug_console = {
>   .address = 0x11002000,
>   .size = 0x1000,
>   .flags = JAILHOUSE_CON1_TYPE_8250 |
>JAILHOUSE_CON1_ACCESS_MMIO |
>JAILHOUSE_CON1_REGDIST_4 |
>JAILHOUSE_CON2_TYPE_ROOTPAGE,
>   },
>   .platform_info = {
>   .pci_mmconfig_base = 0x200,
>   .pci_mmconfig_end_bus = 0,
>   .pci_is_virtual = 1,
>   .arm = {
>   .gic_version = 2,
>   .gicd_base = 0x1051,
>   .gicc_base = 0x1052,
>   .gich_base = 0x1054,
>   .gicv_base = 0x1056,
>   .maintenance_irq = 25,
>   },
>   },
>   .root_cell = {
>   .name = "X",
> 
>   .cpu_set_size = sizeof(config.cpus),
>   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
>   .num_irqchips = ARRAY_SIZE(config.irqchips),
>   .num_pci_devices = ARRAY_SIZE(config.pci_devices),
> 
>   .vpci_irq_base = 108,
>   },
>   },
> 
>   .cpus = {
>   0x3F,
>   },
> 
>   .mem_regions = {
>   /* CCU */ {
> .phys_start = 0x1000,
> .virt_start = 0x1000,
> .size = 0x200,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
> JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
> },
>   /* MMIO 1 (permissive) */ {
>   .phys_start = 0x1300,
>   .virt_start = 0x1300,
>   .size =  0x400,
>   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
>   JAILHOUSE_MEM_IO,
>   },
>   /* pinctrl PA */ {
>   .phys_start = 0x1800,
>   .virt_start = 0x1800,
>   .size = 0x200,
>   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
>   JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
>   },
>   /* RAM */ {
>   .phys_start = 0x4000,
>   .virt_start = 0x4000,
>   .size =0x02FF,

This switches the region in to sub-page mode, and that may cause this
surprising behavior. Just do size + 1, as it is correct.

>   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | 
> JAILHOUSE_MEM_EXECUTE,
>   },
>/* RAM*/  /*{
> .phys_start = 0x40EC,
> .virt_start = 0x40EC,
> .size =0x0213,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | 
> JAILHOUSE_MEM_EXECUTE,
> },*/
>   /**THIS HOLE FOR ARM TRUSTED FIRMWARE**/
> 
>/* RAM*/  {
> .phys_start = 0x4304,
> .virt_start = 0x4304,
> .size =0x38EC,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | 
> JAILHOUSE_MEM_EXECUTE,
> },
> 
>   /* IVSHMEM shared memory region */ {
>   .phys_start = 0x7BF0,
>

Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-11 Thread bharat gohil 
Hello Jan,

Please find attached root cell config file.

Thanks,
Bharat

On Sat, Feb 10, 2018 at 2:23 PM, Jan Kiszka  wrote:

> On 2018-02-10 08:46, bharat gohil wrote:
> >
> > Yes, that is correct.
> > When starting root cell,
> > jailhouse enable .cell
>
> Could you share your config file?
>
> Also, you have local modifications on your tree. What are they changing,
> just configuration files?
>
> Jan
>
> > Thanks,
> > Bharat
> >
> >
> > On 07-Feb-2018 5:39 PM, "Jan Kiszka"  > > wrote:
> >
> > On 2018-02-07 10:27, bharat gohil wrote:
> > > Hi
> > >
> > > I was trying to Run jailhouse on two board i.e OrangePi PC2 and
> > Quad core A35/A72 based SoC.
> > >
> > > I am able run Jailhouse on OrangePI PC2 and ran simple application
> > on single core which blinks the LED which works fine on OrangePI PC2
> > board.
> > >
> > > But I have problem running Jailhouse on other board which has A35
> > and A72.
> > >
> > > I got following crash when enable Jailhouse on this board,
> > >
> > > Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 0
> > > Code location: 0xc0200060
> > > Page pool usage after early setup: mem 61/16356, remap 48/131072
> > > Initializing processors:
> > >  CPU 0... OK
> > >  CPU 1... OK
> > >  CPU 2... OK
> > > Adding virtual PCI device 00:00.0 to cell "Dione"
> > > Page pool usage after late setup: mem 66/16356, remap 53/131072
> > > FATAL: instruction abort at 0x40ebdee8
> > >
> > > FATAL: unhandled trap (exception class 0x20)
> > > Cell state before exception:
> > >  pc: ff80008f0ee8   lr: ff80008f0ee8 spsr: 61c5 EL1
> > >  sp: ffc02f003bb0  esr: 20 1 086
> > >  x0:    x1:    x2: 
> > >  x3:    x4:    x5: 
> > >  x6:    x7:    x8: 
> > >  x9:   x10:   x11: 
> > > x12:   x13:   x14: 
> > > x15:   x16:   x17: 
> > > x18:   x19: ff80008f4910  x20: ff801000
> > > x21: ff801000  x22:   x23: 0140
> > > x24: ff80008f4600  x25: ff8008d26de0  x26: ff801000
> > > x27: 02c4  x28: ffc02f00  x29: ffc02f003bb0
> > >
> > > Parking CPU 2 (Cell: "X")
> > >
> > > It generate exception at 0x40ebdee8 which is DDR address.
> > >
> > > I have mentioned DDR range including above address in to the
> > root-cell configuration like this,
> > >  /* RAM */ {
> > > .phys_start = 0x4000,
> > > .virt_start = 0x4000,
> > > .size =0x02FF,
> > > .flags = JAILHOUSE_MEM_READ |
> > JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE,
> > > },
> > >
> > > Can anyone help me to figure out what is the problem or how to
> > debug and resolve this issue?
> >
> > Only the root cell is running at this point, right? There is no
> overlap
> > of other regions or the hypervisor region itself?
> >
> > Jan
> >
> > --
> > Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> > Corporate Competence Center Embedded Linux
> >
> >
> > --
> > You received this message because you are subscribed to the Google
> > Groups "Jailhouse" group.
> > To unsubscribe from this group and stop receiving emails from it, send
> > an email to jailhouse-dev+unsubscr...@googlegroups.com
> > .
> > For more options, visit https://groups.google.com/d/optout.
>
>


-- 
Regards,
Bharat Gohil
Sr.Software Engineer
bharat.go...@harman.com
+919427054633

-- 
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/*
 * Jailhouse, a Linux-based partitioning hypervisor
 *
 * Test configuration for X (2-Cortex-A72, 4-Cortex-A35, 2GB RAM)
 *
 * Copyright (c) Siemens AG, 2014-2016
 *
 * Authors:
 *  Jan Kiszka 
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 */

#include 
#include 

#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])

struct {
	struct jailhouse_system header;
	__u64 cpus[1];
	struct jailhouse_memory mem_regions[8];
	struct jailhouse_irqchip irqchips[1];
	struct jailhouse_pci_device pci_devices[1];
}

Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-10 Thread Jan Kiszka 
On 2018-02-10 08:46, bharat gohil wrote:
> 
> Yes, that is correct. 
> When starting root cell,
> jailhouse enable .cell

Could you share your config file?

Also, you have local modifications on your tree. What are they changing,
just configuration files?

Jan

> Thanks,
> Bharat
> 
> 
> On 07-Feb-2018 5:39 PM, "Jan Kiszka"  > wrote:
> 
> On 2018-02-07 10:27, bharat gohil wrote:
> > Hi
> >
> > I was trying to Run jailhouse on two board i.e OrangePi PC2 and
> Quad core A35/A72 based SoC.
> >
> > I am able run Jailhouse on OrangePI PC2 and ran simple application
> on single core which blinks the LED which works fine on OrangePI PC2
> board.
> >
> > But I have problem running Jailhouse on other board which has A35
> and A72.
> >
> > I got following crash when enable Jailhouse on this board,
> >
> > Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 0
> > Code location: 0xc0200060
> > Page pool usage after early setup: mem 61/16356, remap 48/131072
> > Initializing processors:
> >  CPU 0... OK
> >  CPU 1... OK
> >  CPU 2... OK
> > Adding virtual PCI device 00:00.0 to cell "Dione"
> > Page pool usage after late setup: mem 66/16356, remap 53/131072
> > FATAL: instruction abort at 0x40ebdee8
> >
> > FATAL: unhandled trap (exception class 0x20)
> > Cell state before exception:
> >  pc: ff80008f0ee8   lr: ff80008f0ee8 spsr: 61c5     EL1
> >  sp: ffc02f003bb0  esr: 20 1 086
> >  x0:    x1:    x2: 
> >  x3:    x4:    x5: 
> >  x6:    x7:    x8: 
> >  x9:   x10:   x11: 
> > x12:   x13:   x14: 
> > x15:   x16:   x17: 
> > x18:   x19: ff80008f4910  x20: ff801000
> > x21: ff801000  x22:   x23: 0140
> > x24: ff80008f4600  x25: ff8008d26de0  x26: ff801000
> > x27: 02c4  x28: ffc02f00  x29: ffc02f003bb0
> >
> > Parking CPU 2 (Cell: "X")
> >
> > It generate exception at 0x40ebdee8 which is DDR address.
> >
> > I have mentioned DDR range including above address in to the
> root-cell configuration like this,
> >      /* RAM */ {
> >                         .phys_start = 0x4000,
> >                         .virt_start = 0x4000,
> >                         .size =        0x02FF,
> >                         .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE,
> >                 },
> >
> > Can anyone help me to figure out what is the problem or how to
> debug and resolve this issue?
> 
> Only the root cell is running at this point, right? There is no overlap
> of other regions or the hypervisor region itself?
> 
> Jan
> 
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
> 
> 
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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-09 Thread bharat gohil 
Yes, that is correct.
When starting root cell,
jailhouse enable .cell
Thanks,
Bharat


On 07-Feb-2018 5:39 PM, "Jan Kiszka"  wrote:

On 2018-02-07 10:27, bharat gohil wrote:
> Hi
>
> I was trying to Run jailhouse on two board i.e OrangePi PC2 and Quad core
A35/A72 based SoC.
>
> I am able run Jailhouse on OrangePI PC2 and ran simple application on
single core which blinks the LED which works fine on OrangePI PC2 board.
>
> But I have problem running Jailhouse on other board which has A35 and A72.
>
> I got following crash when enable Jailhouse on this board,
>
> Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 0
> Code location: 0xc0200060
> Page pool usage after early setup: mem 61/16356, remap 48/131072
> Initializing processors:
>  CPU 0... OK
>  CPU 1... OK
>  CPU 2... OK
> Adding virtual PCI device 00:00.0 to cell "Dione"
> Page pool usage after late setup: mem 66/16356, remap 53/131072
> FATAL: instruction abort at 0x40ebdee8
>
> FATAL: unhandled trap (exception class 0x20)
> Cell state before exception:
>  pc: ff80008f0ee8   lr: ff80008f0ee8 spsr: 61c5 EL1
>  sp: ffc02f003bb0  esr: 20 1 086
>  x0:    x1:    x2: 
>  x3:    x4:    x5: 
>  x6:    x7:    x8: 
>  x9:   x10:   x11: 
> x12:   x13:   x14: 
> x15:   x16:   x17: 
> x18:   x19: ff80008f4910  x20: ff801000
> x21: ff801000  x22:   x23: 0140
> x24: ff80008f4600  x25: ff8008d26de0  x26: ff801000
> x27: 02c4  x28: ffc02f00  x29: ffc02f003bb0
>
> Parking CPU 2 (Cell: "X")
>
> It generate exception at 0x40ebdee8 which is DDR address.
>
> I have mentioned DDR range including above address in to the root-cell
configuration like this,
>  /* RAM */ {
> .phys_start = 0x4000,
> .virt_start = 0x4000,
> .size =0x02FF,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE
| JAILHOUSE_MEM_EXECUTE,
> },
>
> Can anyone help me to figure out what is the problem or how to debug and
resolve this issue?

Only the root cell is running at this point, right? There is no overlap
of other regions or the hypervisor region itself?

Jan

--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

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Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-07 Thread Jan Kiszka 
On 2018-02-07 10:27, bharat gohil wrote:
> Hi
> 
> I was trying to Run jailhouse on two board i.e OrangePi PC2 and Quad core 
> A35/A72 based SoC.
> 
> I am able run Jailhouse on OrangePI PC2 and ran simple application on single 
> core which blinks the LED which works fine on OrangePI PC2 board.
> 
> But I have problem running Jailhouse on other board which has A35 and A72.
> 
> I got following crash when enable Jailhouse on this board,
> 
> Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 0
> Code location: 0xc0200060
> Page pool usage after early setup: mem 61/16356, remap 48/131072
> Initializing processors:
>  CPU 0... OK
>  CPU 1... OK
>  CPU 2... OK
> Adding virtual PCI device 00:00.0 to cell "Dione"
> Page pool usage after late setup: mem 66/16356, remap 53/131072
> FATAL: instruction abort at 0x40ebdee8
> 
> FATAL: unhandled trap (exception class 0x20)
> Cell state before exception:
>  pc: ff80008f0ee8   lr: ff80008f0ee8 spsr: 61c5 EL1
>  sp: ffc02f003bb0  esr: 20 1 086
>  x0:    x1:    x2: 
>  x3:    x4:    x5: 
>  x6:    x7:    x8: 
>  x9:   x10:   x11: 
> x12:   x13:   x14: 
> x15:   x16:   x17: 
> x18:   x19: ff80008f4910  x20: ff801000
> x21: ff801000  x22:   x23: 0140
> x24: ff80008f4600  x25: ff8008d26de0  x26: ff801000
> x27: 02c4  x28: ffc02f00  x29: ffc02f003bb0
> 
> Parking CPU 2 (Cell: "X")
> 
> It generate exception at 0x40ebdee8 which is DDR address.
> 
> I have mentioned DDR range including above address in to the root-cell 
> configuration like this,
>  /* RAM */ {
> .phys_start = 0x4000,
> .virt_start = 0x4000,
> .size =0x02FF,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | 
> JAILHOUSE_MEM_EXECUTE,
> },
> 
> Can anyone help me to figure out what is the problem or how to debug and 
> resolve this issue?

Only the root cell is running at this point, right? There is no overlap
of other regions or the hypervisor region itself?

Jan

-- 
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

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