Re: Does gbm_bo_map() implicitly synchronise?

map (e.g. using PresentPixmap). So far, we've only tested Intel GPUs, but we are setting up Nvidia and AMD GPUs at the moment. It will be interesting to see if the issue remains on those or not. Regards, Chema Casanova

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/3] glsl: TCS outputs can not be transform feedback candidates on GLES

On 13/3/19 23:17, Emil Velikov wrote: > Hi Jose, > > On Wed, 21 Nov 2018 at 18:45, Jose Maria Casanova Crespo > wrote: >> >> Fixes: >> KHR-GLES*.core.tessellation_shader.single.xfb_captures_data_from_correct_stage >> > This and the follow-up patch "glsl: fix recording of variables for XFB > in T

Re: [Mesa-dev] [PATCH 1/3] glsl: XFB TSC per-vertex output varyings match as not declared as arrays

V2 of this series that address the fix for KHR-GL*.tessellation_shader.single.xfb_captures_data_from_correct_stage regressions is available at Gitlab MR!300 https://gitlab.freedesktop.org/mesa/mesa/merge_requests/300 On 21/11/18 19:45, Jose Maria Casanova Crespo wrote: > Recent change on OpenGL C

Re: [Mesa-dev] [PATCH] intel/compiler: Add a file-level description of brw_eu_validate.c

Acked-by: Jose Maria Casanova Crespo Matt, I'll include in my TODO list creating tests for sends using grf127 as destination restriction and the one about byte_raw_moves and execution size and stride once I receive your feedback. Chema El 24/1/19 a las 20:53, Matt Turner escribió: > --- > src/

Re: [Mesa-dev] [PATCH 5/9] intel/compiler: relax brw_eu_validate for byte raw movs

El 23/1/19 a las 7:26, Matt Turner escribió: > On Sun, Jul 8, 2018 at 5:27 PM, Jose Maria Casanova Crespo > wrote: >> When the destination is a BYTE type allow raw movs >> even if the stride is not exact multiple of destination >> type and exec type, execution type is Word and its size is 2. >> >>

Re: [Mesa-dev] [PATCH] intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode

If Matt concerns about the validation rule are solved this is. Reviewed-by: Jose Maria Casanova Crespo El 15/1/19 a las 17:58, Jason Ekstrand escribió: > Previously, we only applied the fix to shaders with a dispatch mode of > SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD1

Re: [Mesa-dev] [PATCH] intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode

El 16/1/19 a las 0:55, Matt Turner escribió: > On Tue, Jan 15, 2019 at 8:58 AM Jason Ekstrand wrote: >> >> Previously, we only applied the fix to shaders with a dispatch mode of >> SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16 >> instructions. If you have a SIMD8 instruct

Re: [Mesa-dev] [PATCH 1/3] glsl: XFB TSC per-vertex output varyings match as not declared as arrays

Ping. El 22/11/18 a las 0:28, Chema Casanova escribió: > > > On 21/11/18 20:04, Ilia Mirkin wrote: >> On Wed, Nov 21, 2018 at 1:45 PM Jose Maria Casanova Crespo >> wrote: >>> >>> Recent change on OpenGL CTS ("Use non-arrayed

Re: [Mesa-dev] [PATCH 41/59] intel/compiler: split is_partial_write() into two variants

El 13/12/18 a las 11:49, Pohjolainen, Topi escribió: > On Thu, Dec 13, 2018 at 09:10:24AM +0100, Iago Toral wrote: >> On Wed, 2018-12-12 at 14:15 +0200, Pohjolainen, Topi wrote: >>> On Wed, Dec 12, 2018 at 09:48:20AM +0100, Iago Toral wrote: On Tue, 2018-12-11 at 18:59 +0200, Pohjolainen, To

Re: [Mesa-dev] [PATCH 3/3] glsl: fix typos in comments "transfor" -> "transform"

On 21/11/18 20:07, Ilia Mirkin wrote: > Oh, yay, you fixed the typos here. I just had to keep reading. > > This patch is obviously > > Reviewed-by: Ilia Mirkin Thanks. > > For the others ... have you run these through intel's CI? > I'm interested in verifying that dEQP, CTS, and piglit all r

Re: [Mesa-dev] [PATCH 1/3] glsl: XFB TSC per-vertex output varyings match as not declared as arrays

On 21/11/18 20:04, Ilia Mirkin wrote: > On Wed, Nov 21, 2018 at 1:45 PM Jose Maria Casanova Crespo > wrote: >> >> Recent change on OpenGL CTS ("Use non-arrayed varying name for TCS blocks") >> on KHR-GL*.tessellation_shader.single.xfb_captures_data_from_correct_stage >> tests changed how to name

Re: [Mesa-dev] [PATCH 1/2] intel/fs: New method for register_byte_use_pattern for fs_inst

El 29/07/18 a las 19:47, Chema Casanova escribió: > El 28/07/18 a las 01:45, Francisco Jerez escribió: >> Chema Casanova writes: [...] >>>>> If we have a partial write/read: >>>>> >>>>> I understood that you my initial patter proposal

Re: [Mesa-dev] [PATCH 1/2] intel/fs: New method for register_byte_use_pattern for fs_inst

El 28/07/18 a las 01:45, Francisco Jerez escribió: > Chema Casanova writes: > >> El 27/07/18 a las 02:44, Francisco Jerez escribió: >>> Chema Casanova writes: >>> >>>> El 26/07/18 a las 20:02, Francisco Jerez escribió: >>>>> Che

[Mesa-dev] [PATCH 1/2] intel/fs: New method for register_byte_use_pattern for fs_inst

El 27/07/18 a las 02:44, Francisco Jerez escribió: > Chema Casanova writes: > >> El 26/07/18 a las 20:02, Francisco Jerez escribió: >>> Chema Casanova writes: >>> >>>> El 20/07/18 a las 22:10, Francisco Jerez escribió: >>>>> Che

Re: [Mesa-dev] [PATCH 1/2] intel/fs: New method for register_byte_use_pattern for fs_inst

El 26/07/18 a las 20:02, Francisco Jerez escribió: > Chema Casanova writes: > >> El 20/07/18 a las 22:10, Francisco Jerez escribió: >>> Chema Casanova writes: >>> >>>> El 20/07/18 a las 00:34, Francisco Jerez escribió: >>>>> Che

Re: [Mesa-dev] [PATCH] intel/compiler: fix lower conversions to account for predication

Please include: Fixes: 5a12bdac09496e00 "i965/compiler: handle conversion to smaller type in the lowering pass for that" Reviewed-by: Jose Maria Casanova Crespo El 17/07/18 a las 11:10, Iago Toral Quiroga escribió: > The pass can create a temporary result for the instru

Re: [Mesa-dev] [PATCH mesa] anv: don't crash on vkDestroyDevice(NULL)

Reviewed-by: Jose Maria Casanova Crespo El 25/07/18 a las 21:25, Eric Engestrom escribió: > On Wednesday, 2018-07-25 19:45:56 +0100, Eric Engestrom wrote: >> CovID: 1438132 >> Signed-off-by: Eric Engestrom > > Forgot to check before sending: > > Fixes: a99c9e63a07477634ab73 "anv: finish the bi

Re: [Mesa-dev] [PATCH 1/2] intel/fs: New method for register_byte_use_pattern for fs_inst

El 20/07/18 a las 22:10, Francisco Jerez escribió: > Chema Casanova writes: > >> El 20/07/18 a las 00:34, Francisco Jerez escribió: >>> Chema Casanova writes: >>> >>>> El 14/07/18 a las 00:14, Francisco Jerez escribió: >>>>> Jose Maria Ca

Re: [Mesa-dev] [PATCH 1/2] intel/fs: New method for register_byte_use_pattern for fs_inst

El 20/07/18 a las 00:34, Francisco Jerez escribió: > Chema Casanova writes: > >> El 14/07/18 a las 00:14, Francisco Jerez escribió: >>> Jose Maria Casanova Crespo writes: >>> >>>> For a register source/destination of an instruction the function return

[Mesa-dev] [PATCH 1/2] intel/fs: New method for register_byte_use_pattern for fs_inst

El 14/07/18 a las 00:14, Francisco Jerez escribió: > Jose Maria Casanova Crespo writes: > >> For a register source/destination of an instruction the function returns >> the read/write byte pattern of a 32-byte registers as a unsigned int. >> >> The returned pattern takes into account the exec_siz

Re: [Mesa-dev] [PATCH] i965/fs: unspills shoudn't use grf127 as dest since Gen8+

El 12/07/18 a las 03:23, Caio Marcelo de Oliveira Filho escribió: > On Wed, Jul 11, 2018 at 06:03:05PM +0200, Jose Maria Casanova Crespo wrote: >> At 232ed8980217dd65ab0925df28156f565b94b2e5 "i965/fs: Register allocator >> shoudn't use grf127 for sends dest" we didn't take into account the case >>

Re: [Mesa-dev] [RFC] i965/fs: Generalize grf127 hack to dispatch_width > 8

El 11/07/18 a las 03:50, Caio Marcelo de Oliveira Filho escribió: > Change the hack to always apply, adjusting the register number > according to the dispatch_width. > > The original change assumed that given for dispatch_width > 8 we > already prevent the overlap of source and destination for sen

Re: [Mesa-dev] [PATCH 2/9] i965/fs: Register allocator shoudn't use grf127 for sends dest

Including mesa-dev in my previous reply. El 11/07/18 a las 01:08, Caio Marcelo de Oliveira Filho escribió: >> Since Gen8+ Intel PRM states that "r127 must not be used for return >> address when there is a src and dest overlap in send instruction." > > The previous patch, that verifies the conditi

Re: [Mesa-dev] [PATCH 01/14] intel/fs: general 8/16/32/64-bit shuffle_src_to_dst function (v2)

On 15/06/18 06:50, Jason Ekstrand wrote: > On Thu, Jun 14, 2018 at 6:06 PM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > This new function takes care of shuffle/unshuffle components of a > particular bit-size in components with a different bit-size. > > If so

Re: [Mesa-dev] [PATCH 09/14] intel/compiler: Use shuffle_from_32bit_read at VS load_input

I've forgot to Cc: the mailing list. On 15/06/18 01:54, Chema Casanova wrote: > On 14/06/18 03:36, Jason Ekstrand wrote: >> On Sat, Jun 9, 2018 at 4:13 AM, Jose Maria Casanova Crespo >> mailto:jmcasan...@igalia.com>> wrote: >> >> shuffle_from_32b

Re: [Mesa-dev] [PATCH 13/14] intel/compiler: use new shuffle_32bit_write for all 64-bit storage writes

On 14/06/18 03:44, Jason Ekstrand wrote: > On Sat, Jun 9, 2018 at 4:13 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > --- >  src/intel/compiler/brw_fs_nir.cpp | 13 ++--- >  1 file changed, 6 insertions(+), 7 deletions(-) > > diff --git a/src/int

Re: [Mesa-dev] [PATCH 07/14] intel/compiler: shuffle_from_32bit_read for 64-bit do_untyped_vector_read

On 14/06/18 03:26, Jason Ekstrand wrote: > On Sat, Jun 9, 2018 at 4:13 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > do_untyped_vector_read is used at load_ssbo and load_shared. > > The previous MOVs are removed because shuffle_from_32bit_read > can hand

Re: [Mesa-dev] [PATCH 02/14] intel/compiler: new shuffle_for_32bit_write and shuffle_from_32bit_read

On 14/06/18 03:02, Jason Ekstrand wrote: > On Sat, Jun 9, 2018 at 4:13 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > These new shuffle functions deal with the shuffle/unshuffle operations > needed for read/write operations using 32-bit components when the >

Re: [Mesa-dev] [PATCH 01/14] intel/compiler: general 8/16/32/64-bit shuffle_src_to_dst function

El 14/06/18 a las 02:46, Jason Ekstrand escribió: > On Wed, Jun 13, 2018 at 5:07 PM, Chema Casanova <mailto:jmcasan...@igalia.com>> wrote: > > On 13/06/18 22:46, Jason Ekstrand wrote: > > On Sat, Jun 9, 2018 at 4:13 AM, Jose Maria Casanova Crespo > >

Re: [Mesa-dev] [PATCH 01/14] intel/compiler: general 8/16/32/64-bit shuffle_src_to_dst function

On 13/06/18 22:46, Jason Ekstrand wrote: > On Sat, Jun 9, 2018 at 4:13 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > This new function takes care of shuffle/unshuffle components of a > particular bit-size in components with a different bit-size. > > If sou

Re: [Mesa-dev] [PATCH v2] nir/print: fix printing of 8/16 bit constant variables

El 29/05/18 a las 02:14, Karol Herbst escribió: > v2 (Chema Casanova ): add float16 support > > Signed-off-by: Karol Herbst > --- > src/compiler/nir/nir_print.c | 31 +++ > 1 file changed, 31 insertions(+) > > diff --git a/src/compil

Re: [Mesa-dev] [PATCH] nir/print: fix printing of 8/16 bit constant variables

As GLSL_TYPE_FLOAT16 type support is not implemented in this patch, we would need to change commit summary to ".. 8/16 bit integer constant.." or just implement half float support with something like. + case GLSL_TYPE_FLOAT16: + for (i = 0; i < cols; i++) { + for (j = 0; j < rows; j

Re: [Mesa-dev] [PATCH] intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0

Thanks for fixing the full overwrite of the Control Register. Reviewed-by: Jose Maria Casanova Crespo El 19/05/18 a las 05:09, Jason Ekstrand escribió: > Fixes: d6cd14f2131a5b "i965/fs: Define new shader opcode to..." > --- > src/intel/compiler/brw_eu_emit.c | 2 ++ > 1 file changed, 2 insertio

Re: [Mesa-dev] [PATCH 1/3] intel/compiler: make brw_reg_type_from_bit_size usable from other places

El 15/05/18 a las 13:05, Iago Toral Quiroga escribió: > This was private to brw_fs_nir.cpp but we are going to need it soon in > brw_fs.cpp, so move it there and make it available to other files as we > do for other utility functions. > --- > src/intel/compiler/brw_fs.cpp | 59 > +++

Re: [Mesa-dev] [PATCH 2/2] i965/fs: Register allocator shoudn't use grf127 for sends dest (v2)

This patch is still pending of review. Adding also Cc: to stable as if fixes some cts issues. Chema El 19/04/18 a las 02:38, Jose Maria Casanova Crespo escribió: > Since Gen8+ Intel PRM states that "r127 must not be used for return > address when there is a src and dest overlap in send instruct

Re: [Mesa-dev] [PATCH v2 07/18] intel/compiler: fix brw_negate_immediate for 16-bit types

El 30/04/18 a las 23:14, Jason Ekstrand escribió: > > > On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga > wrote: > > From: Jose Maria Casanova Crespo > > > From Intel Skylake PRM, vol 07, "Immediate" section (page 768):

Re: [Mesa-dev] [PATCH v2 06/18] intel/compiler: fix brw_imm_w for negative 16-bit integers

El 01/05/18 a las 01:22, Jason Ekstrand escribió: > On Mon, Apr 30, 2018 at 3:53 PM, Chema Casanova <mailto:jmcasan...@igalia.com>> wrote: > > > > On 30/04/18 23:12, Jason Ekstrand wrote: > > On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quir

Re: [Mesa-dev] [PATCH v2 06/18] intel/compiler: fix brw_imm_w for negative 16-bit integers

On 30/04/18 23:12, Jason Ekstrand wrote: > On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga > wrote: > > From: Jose Maria Casanova Crespo > > > 16-bit immediates need to replicate the 16-bit immediate value > in both w

Re: [Mesa-dev] [PATCH 08/11] intel/compiler: fix brw_negate_immediate for 16-bit types

El 24/04/18 a las 23:55, Jason Ekstrand escribió: > On Wed, Apr 11, 2018 at 12:20 AM, Iago Toral Quiroga > wrote: > > From: Jose Maria Casanova Crespo > > > 16-bit immediates are replicated in each word of a 32-bit value >

Re: [Mesa-dev] [PATCH 06/11] nir/constant_folding: support 16-bit constants

El 24/04/18 a las 23:52, Jason Ekstrand escribió: > On Wed, Apr 11, 2018 at 12:20 AM, Iago Toral Quiroga > wrote: > > From: Jose Maria Casanova Crespo > > > --- >  src/compiler/nir/nir_opt_constant_folding.c | 2 ++ >  1

Re: [Mesa-dev] [PATCH 3/3] nir/opt_constant_folding: fix folding of 8 and 16 bit ints

I've already got to the same code addressing Jason feedback about "[PATCH 06/11] nir/constant_folding: support 16-bit constants." So this is: Reviewed-by: Jose Maria Casanova Crespo El 25/04/18 a las 11:14, Karol Herbst escribió: > Signed-off-by: Karol Herbst > --- > src/compiler/nir/nir_opt_

Re: [Mesa-dev] [PATCH 1/3] nir: support converting to 8-bit integers in nir_type_conversion_op

Reviewed-by: Jose Maria Casanova Crespo El 25/04/18 a las 11:14, Karol Herbst escribió: > Signed-off-by: Karol Herbst > --- > src/compiler/nir/nir_opcodes_c.py | 7 ++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/src/compiler/nir/nir_opcodes_c.py > b/src/compiler/nir

Re: [Mesa-dev] [PATCH] i965/fs: retype offset_reg to UD at load_ssbo

On 19/04/18 19:50, Ian Romanick wrote: > On 04/18/2018 01:57 PM, Jose Maria Casanova Crespo wrote: >> All operations with offset_reg at do_vector_read are done >> with UD type. So copy propagation was not working through >> the generated MOVs: >> >> mov(8) vgrf9:UD, vgrf7:D > > I have noticed othe

Re: [Mesa-dev] [PATCH 1/2] intel/compiler: grf127 can not be dest when src and dest overlap in send

On 15/04/18 08:55, Matt Turner wrote: > On Wed, Apr 11, 2018 at 7:30 PM, Jose Maria Casanova Crespo > wrote: >> Implement at brw_eu_validate the restriction from Intel Broadwell PRM, vol >> 07, >> section "Instruction Set Reference", subsection "EUISA Instructions", Send >> Message (page 990): >>

Re: [Mesa-dev] [PATCH 1/6] i965: Add negative_equals methods

On 23/03/18 19:27, Matt Turner wrote: > On Wed, Mar 21, 2018 at 5:58 PM, Ian Romanick wrote: >> From: Ian Romanick >> >> This method is similar to the existing ::equals methods. Instead of >> testing that two src_regs are equal to each other, it tests that one is >> the negation of the other.

Re: [Mesa-dev] [PATCH] nir/search: Support 8 and 16-bit constants

I've been checking the whole nir_search.c and there is another pending 16-bit support in construct_value function. I'm sending a patch so feel free to squash it to your if it makes sense. In any case this is. Reviewed-by: Jose Maria Casanova Crespo El 28/02/18 a las 22:18, Jason Ekstrand escrib

Re: [Mesa-dev] [PATCH v2 0/8] anv: VK_KHR_16bit_storage enabling SSBO/UBO/PushConstant

On 28/02/18 18:02, Jason Ekstrand wrote: > I think all the interesting patches are reviewed now.  All the boring > "turn stuff on" patches are > > Reviewed-by: Jason Ekstrand > Thanks a lot for the quick review of the series. One step less to enable the VK_KHR_16bit_

Re: [Mesa-dev] [PATCH v2 2/8] i965/fs: shuffle_32bit_load_result_to_16bit_data now skips components

On 27/02/18 20:00, Jason Ekstrand wrote: > On Tue, Feb 27, 2018 at 5:27 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > This helper used to load 16bit components from 32-bits read now allows > skipping components with the new parameter first_component. The >

Re: [Mesa-dev] [PATCH v2 1/8] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit

On 27/02/18 19:53, Jason Ekstrand wrote: > On Tue, Feb 27, 2018 at 5:27 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > The surfaces that backup the GPU buffers have a boundary check that > considers that access to partial dwords are considered out-of-bounds. >

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

ble VK_KHR_16bit_storage for PushConstant I'll resend this series when [2/7] is ready. Chema > --Jason > > > On February 26, 2018 09:08:01 Chema Casanova wrote: > >> On 26/02/18 16:54, Jason Ekstrand wrote: >>> On Mon, Feb 26, 2018 at 6:14 AM, Jose Mar

Re: [Mesa-dev] [PATCH 3/7] i965/fs: Support 16-bit store_ssbo with VK_KHR_relaxed_block_layout

On 23/02/18 21:23, Jason Ekstrand wrote: > On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > Restrict the use of untyped_surface_write with 16-bit pairs in > ssbo to the cases where we can guarantee that offset is multiple > of 4. >

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

On 26/02/18 16:54, Jason Ekstrand wrote: > On Mon, Feb 26, 2018 at 6:14 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > The surfaces that backup the GPU buffers have a boundary check that > considers that access to partial dwords are considered out-of-bounds. >

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

On 26/02/18 15:40, Ilia Mirkin wrote: > On Mon, Feb 26, 2018 at 9:14 AM, Jose Maria Casanova Crespo > wrote: >> The surfaces that backup the GPU buffers have a boundary check that >> considers that access to partial dwords are considered out-of-bounds. >> For example, buffers with 1/3 16-bit elemn

Re: [Mesa-dev] [PATCH 1/7] anv/spirv: SSBO/UBO buffers needs padding size is not multiple of 32-bits

El 23/02/18 a las 22:31, Jason Ekstrand escribió: > On Fri, Feb 23, 2018 at 12:28 PM, Chema Casanova <mailto:jmcasan...@igalia.com>> wrote: > > > > El 23/02/18 a las 17:26, Jason Ekstrand escribió: > > On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova

Re: [Mesa-dev] [PATCH 6/7] spirv/i965/anv: Relax push constant offset assertions being 32-bit aligned

El 23/02/18 a las 22:36, Jason Ekstrand escribió: > Assuming the CTS is still happy with it after those changes, CTS was happy, but piglit has complained a lot. > > Reviewed-by: Jason Ekstrand <mailto:ja...@jlekstrand.net>> > > On Fri, Feb 23, 2018 at 1:16 PM, Chema C

Re: [Mesa-dev] [PATCH 6/7] spirv/i965/anv: Relax push constant offset assertions being 32-bit aligned

On 23/02/18 20:09, Jason Ekstrand wrote: > On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > The introduction of 16-bit types with VK_KHR_16bit_storages implies that > push constant offsets could be multiple of 2-bytes. Some assertions

Re: [Mesa-dev] [PATCH 1/7] anv/spirv: SSBO/UBO buffers needs padding size is not multiple of 32-bits

El 23/02/18 a las 17:26, Jason Ekstrand escribió: > On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > The surfaces that backup the GPU buffers have a boundary check that > considers that access to partial dwords are considered out-of-

Re: [Mesa-dev] [PATCH v4 00/44] anv: SPV_KHR_16bit_storage/VK_KHR_16bit_storage for gen8+

y to have it enabled. Chema > > On Wed, Dec 6, 2017 at 12:09 AM, Alejandro Piñeiro > mailto:apinhe...@igalia.com>> wrote: > > On 06/12/17 01:19, Chema Casanova wrote: > > On 05/12/17 18:31, Chema Casanova wrote: > >> El 05/12/17 a las 06:16, Jason

Re: [Mesa-dev] [PATCH 1/2] i965/fs: Rewrite assign_constant_locations

I've tested this patch against the VK-CTS push constant 16-bit tests, and enabled storagePushConstant16 at VK_KHR_16bit_storage. All test pass without any extra modification. dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant.* dEQP-VK.spirv_assembly.instruction.graphics.16bit_

Re: [Mesa-dev] [PATCH v4 00/44] anv: SPV_KHR_16bit_storage/VK_KHR_16bit_storage for gen8+

On 05/12/17 18:31, Chema Casanova wrote: > El 05/12/17 a las 06:16, Jason Ekstrand escribió: >> A couple of notes: >> >>  1) I *think* I gave you enough reviews to land the UBO/SSBO part and >> the optimizations in 26-28.  If reviews are still missing anywhere, >

Re: [Mesa-dev] [PATCH v4 23/44] i965/fs: Enables 16-bit load_ubo with sampler

On 05/12/17 22:25, Chema Casanova wrote: > On 05/12/17 19:53, Jason Ekstrand wrote: >> On Tue, Dec 5, 2017 at 9:08 AM, Chema Casanova > <mailto:jmcasan...@igalia.com>> wrote: >> >> El 30/11/17 a las 23:58, Jason Ekstrand escribió: >> > On Wed, No

Re: [Mesa-dev] [PATCH v4 28/44] i965/fs: Use untyped_surface_read for 16-bit load_ssbo (v2)

on sources (Jason Ekstrand) >     Rework optimization using unshuffle 16 reads (Chema Casanova) > v3: Use W and D types insead of HF and F in shuffle to avoid rounding >     erros (Jason Ekstrand) >     Use untyped_surface_read for 16-bit vec3. (Jason Ekstrand) > >

Re: [Mesa-dev] [PATCH v4 23/44] i965/fs: Enables 16-bit load_ubo with sampler

On 05/12/17 19:53, Jason Ekstrand wrote: > On Tue, Dec 5, 2017 at 9:08 AM, Chema Casanova <mailto:jmcasan...@igalia.com>> wrote: > > El 30/11/17 a las 23:58, Jason Ekstrand escribió: > > On Wed, Nov 29, 2017 at 6:50 PM, Jose Maria Casanova Crespo > >

Re: [Mesa-dev] [PATCH v4 00/44] anv: SPV_KHR_16bit_storage/VK_KHR_16bit_storage for gen8+

El 05/12/17 a las 06:16, Jason Ekstrand escribió: > A couple of notes: > >  1) I *think* I gave you enough reviews to land the UBO/SSBO part and > the optimizations in 26-28.  If reviews are still missing anywhere, > please let me know.  If not, let's try and get that part landed. The series is al

Re: [Mesa-dev] [PATCH v4 23/44] i965/fs: Enables 16-bit load_ubo with sampler

El 30/11/17 a las 23:58, Jason Ekstrand escribió: > On Wed, Nov 29, 2017 at 6:50 PM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > load_ubo is using 32-bit loads as uniforms surfaces have a 32-bit > surface format defined. So when reading 16-bit components with the

Re: [Mesa-dev] [PATCH v4 20/44] i965/fs: Add byte scattered read message and fs support

On 30/11/17 21:45, Jason Ekstrand wrote: > On Wed, Nov 29, 2017 at 6:50 PM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > v2: Fix alignment style (Topi Pohjolainen) >     (Jason Ekstrand) >     - Enable bit_size parameter to scattered messages to enable > d

Re: [Mesa-dev] [PATCH v4 15/44] i965/fs: Define new shader opcode to set rounding modes

El 01/12/17 a las 09:06, Pohjolainen, Topi escribió: > On Thu, Nov 30, 2017 at 03:07:59AM +0100, Jose Maria Casanova Crespo wrote: >> From: Alejandro Piñeiro >> >> Although it is possible to emit them directly as AND/OR on brw_fs_nir, >> having a specific opcode makes it easier to remove duplicate

Re: [Mesa-dev] [PATCH v4 11/44] i965: Support for 16-bit base types in helper functions

El 01/12/17 a las 09:03, Pohjolainen, Topi escribió: > On Thu, Nov 30, 2017 at 03:07:55AM +0100, Jose Maria Casanova Crespo wrote: >> v2: Fixed calculation of scalar size for 16-bit types. (Jason Ekstrand) >> >> Signed-off-by: Jose Maria Casanova Crespo >> Signed-off-by: Eduardo Lima >> Reviewed-

Re: [Mesa-dev] [PATCH v4 01/44] glsl: Add 16-bit types

El 30/11/17 a las 10:25, Pohjolainen, Topi escribió: > On Thu, Nov 30, 2017 at 03:07:45AM +0100, Jose Maria Casanova Crespo wrote: >> From: Eduardo Lima Mitev > Just a few style nits, see below. > >> Adds new INT16, UINT16 and FLOAT16 base types. >> >> The corresponding GL types for half floats w

Re: [Mesa-dev] [PATCH v4 18/44] i965/fs: Add byte scattered write message and fs support

On 30/11/17 21:42, Jason Ekstrand wrote: > On Wed, Nov 29, 2017 at 6:08 PM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > v2: (Jason Ekstrand) >     - Enable bit_size parameter to scattered messages to enable > different >       bitsizes byte/word/dword. >

Re: [Mesa-dev] [PATCH v4 07/44] spirv/nir: Handle 16-bit types

.com>> wrote: > > From: Eduardo Lima Mitev mailto:el...@igalia.com>> > > v2: Added more missing implementations of 16-bit types. (Jason Ekstrand) > > v3: Store values in values[0].u16[i] (Jason Ekstrand) >     Include switches based on bitsize for 16

Re: [Mesa-dev] [PATCH v4 28/44] i965/fs: Use untyped_surface_read for 16-bit load_ssbo

to do if we can assume to write random data at the 4th component. >   > > v2: Removed use of stride = 2 on sources (Jason Ekstrand) >     Rework optimization using unshuffle 16 reads (Chema Casanova) > --- >  src/intel/compiler/brw_fs_nir.cpp | 43 > +++

Re: [Mesa-dev] [PATCH v4 19/44] i965/fs: Use byte_scattered_write on 16-bit store_ssbo

On 01/12/17 11:12, Jason Ekstrand wrote: > I've left some comments below that I think clean things up and make this > better, but I believe it is correct as-is. > > Reviewed-by: Jason Ekstrand > > > On Wed, Nov 29, 2017 at 6:42 PM, Jose Maria Casanova Crespo > mailto

Re: [Mesa-dev] [PATCH v4 22/44] i965/fs: Helpers for un/shuffle 16-bit pairs in 32-bit components

On 30/11/17 23:21, Jason Ekstrand wrote: > On Wed, Nov 29, 2017 at 6:50 PM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > This helpers are used to load/store 16-bit types from/to 32-bit > components. > > The functions shuffle_32bit_load_result_to_16bit_data

Re: [Mesa-dev] i965: Kicking off fp16 glsl support

age series. So better have a look to the new one. Chema Casanova ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v3 20/43] i965/fs: Add byte scattered write message and fs support

On 31/10/17 01:02, Jason Ekstrand wrote: > On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > Signed-off-by: Jose Maria Casanova Crespo > > Signed-off-by: Alejandro Piñeiro

Re: [Mesa-dev] [PATCH v3 17/43] i965/fs: Enable rounding mode on f2f16 ops

On 30/10/17 23:40, Jason Ekstrand wrote: > On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > From: Alejandro Piñeiro > > > By default we don't set the rounding mode. We only set > round-to-near-ev

Re: [Mesa-dev] [PATCH v3] compiler: Mark when input/ouput attribute at VS uses 16-bit (v2)

El 02/11/17 a las 19:25, Jason Ekstrand escribió: > On Thu, Nov 2, 2017 at 11:17 AM, Chema Casanova <mailto:jmcasan...@igalia.com>> wrote: > > > > El 01/11/17 a las 22:07, Jason Ekstrand escribió: > > On Tue, Oct 17, 2017 at 10:05 AM, Jose Maria Casanova

Re: [Mesa-dev] [PATCH v3] compiler: Mark when input/ouput attribute at VS uses 16-bit (v2)

El 01/11/17 a las 22:07, Jason Ekstrand escribió: > On Tue, Oct 17, 2017 at 10:05 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > New shader attribute to mark when a location has 16-bit > value. This patch includes support on mesa glsl and nir. > > v2: Remov

Re: [Mesa-dev] [PATCH v3 00/43] anv: SPV_KHR_16bit_storage/VK_KHR_16bit_storage for gen8+

El 02/11/17 a las 01:43, Jason Ekstrand escribió: > I'm done reading for the day.  As you're working on incorporating > feedback, I'd  like you to re-arrange things a bit so that we do > everything required to enable VK_KHR_16bit_storage (including > advertising the Vulkan extension string) for SSB

Re: [Mesa-dev] [PATCH v3 17/43] i965/fs: Enable rounding mode on f2f16 ops

El 30/10/17 a las 23:40, Jason Ekstrand escribió: > On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > From: Alejandro Piñeiro > > > By default we don't set the rounding mode. We only set > round-t

Re: [Mesa-dev] [PATCH v3 12/43] i965/fs: Add brw_reg_type_from_bit_size utility method

El 30/10/17 a las 23:15, Jason Ekstrand escribió: > > On Mon, Oct 30, 2017 at 3:08 PM, Jason Ekstrand > wrote: > > On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > From: Alejandro Piñeiro

Re: [Mesa-dev] [PATCH v3 06/43] nir: Handle fp16 rounding modes at nir_type_conversion_op

El 30/10/17 a las 22:26, Jason Ekstrand escribió: > On Thu, Oct 12, 2017 at 11:37 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > nir_type_conversion enables new operations to handle rounding modes to > convert to fp16 values. Two new opcodes are enabled nir_op_

Re: [Mesa-dev] [PATCH v3 19/43] i965/fs: Support push constants of 16-bit types

El 30/10/17 a las 07:44, Pohjolainen, Topi escribió: > On Sun, Oct 29, 2017 at 11:17:11PM +0100, Chema Casanova wrote: >> On 29/10/17 19:55, Pohjolainen, Topi wrote: >>> On Thu, Oct 12, 2017 at 08:38:08PM +0200, Jose Maria Casanova Crespo wrote: >>>> We enable th

Re: [Mesa-dev] [PATCH v3 19/43] i965/fs: Support push constants of 16-bit types

On 29/10/17 19:55, Pohjolainen, Topi wrote: > On Thu, Oct 12, 2017 at 08:38:08PM +0200, Jose Maria Casanova Crespo wrote: >> We enable the use of 16-bit values in push constants >> modifying the assign_constant_locations function to work >> with 16-bit types. >> >> The API to access buffers in Vulk

Re: [Mesa-dev] [PATCH v3 38/43] i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit reg

>> v2: Removed use of stride = 2 on sources (Jason Ekstrand) >> Rework optimization using shuffle 16 write and enable writes >> of 16bit vec4 with only one message of 32-bits. (Chema Casanova) >> >> Signed-off-by: Jose Maria Casanova Crespo >> Signed-of

Re: [Mesa-dev] [PATCH v3 27/43] anv/pipeline: Use 32-bit surface formats for 16-bit formats

El 16/10/17 a las 08:57, Alejandro Piñeiro escribió: > On 15/10/17 12:14, Pohjolainen, Topi wrote: >> On Thu, Oct 12, 2017 at 08:38:16PM +0200, Jose Maria Casanova Crespo wrote: >>> From: Alejandro Piñeiro >>> >>> From Vulkan 1.0.50 spec, Section 3.30.1. Format Definition: >>> VK_FORMAT_R16G16

Re: [Mesa-dev] [PATCH v3 29/43] i965/fs: Unpack 16-bit from 32-bit components in VS load_input

El 15/10/17 a las 12:59, Pohjolainen, Topi escribió: > On Thu, Oct 12, 2017 at 08:38:18PM +0200, Jose Maria Casanova Crespo wrote: >> The VS load input for 16-bit values receives pairs of 16-bit values >> packed in 32-bit values. Because of the adjusted format used at: >> >> anv/pipeline: Use 32-b

Re: [Mesa-dev] [PATCH v3 05/43] nir: Populate conversion opcodes to/from 16-bit types

El 21/10/17 a las 11:44, Pohjolainen, Topi escribió: > On Sat, Oct 21, 2017 at 11:22:45AM +0300, Pohjolainen, Topi wrote: >> On Thu, Oct 12, 2017 at 08:37:54PM +0200, Jose Maria Casanova Crespo wrote: >>> From: Eduardo Lima Mitev >>> >>> This will include the following NIR ALU opcodes: >>> * nir_

Re: [Mesa-dev] [PATCH v3 25/43] compiler: Mark when input/ouput attribute at VS uses 16-bit

On 15/10/17 12:00, Pohjolainen, Topi wrote: > On Thu, Oct 12, 2017 at 08:38:14PM +0200, Jose Maria Casanova Crespo wrote: >> New shader attribute to mark when a location has 16-bit >> value. This patch includes support on mesa glsl and nir. >> --- >> src/compiler/glsl_types.h | 24 +++

Re: [Mesa-dev] [PATCH v3 23/43] i965/fs: Add byte scattered read message and fs support

On 15/10/17 11:47, Pohjolainen, Topi wrote: > On Thu, Oct 12, 2017 at 08:38:12PM +0200, Jose Maria Casanova Crespo wrote: >> --- >> src/intel/compiler/brw_eu.h| 7 + >> src/intel/compiler/brw_eu_defines.h| 2 ++ >> src/intel/compiler/brw_eu_emit.c

Re: [Mesa-dev] [PATCH v3 19/43] i965/fs: Support push constants of 16-bit types

On 14/10/17 10:02, Pohjolainen, Topi wrote: > On Thu, Oct 12, 2017 at 08:38:08PM +0200, Jose Maria Casanova Crespo wrote: >> We enable the use of 16-bit values in push constants >> modifying the assign_constant_locations function to work >> with 16-bit types. >> >> The API to access buffers in Vu

Re: [Mesa-dev] [PATCH v3 14/43] i965/fs: Handle 32-bit to 16-bit conversions

On 14/10/17 09:55, Pohjolainen, Topi wrote: > On Thu, Oct 12, 2017 at 08:38:03PM +0200, Jose Maria Casanova Crespo wrote: >> From: Alejandro Piñeiro >> >> Conversions to 16-bit need having aligment between the 16-bit >> and 32-bit types. So the conversion operations unpack 16-bit types >> to wit

Re: [Mesa-dev] [PATCH v3 16/43] i965/fs: Define new shader opcode to set rounding modes

On 14/10/17 09:49, Pohjolainen, Topi wrote: > On Thu, Oct 12, 2017 at 08:38:05PM +0200, Jose Maria Casanova Crespo wrote: >> From: Alejandro Piñeiro >> >> Although it is possible to emit them directly as AND/OR on brw_fs_nir, >> having a specific opcode makes it easier to remove duplicate settin

Re: [Mesa-dev] [PATCH] i965/fs: Extend the live ranges of VGRFs which leave loops

With this patch applied I can not reproduce anymore the regression related to cross-channel variable interference in non-uniformly executed loops exposed at dEQP-VK.glsl.return.return_in_dynamic_loop_dynamic_vertex when applying Curro's liveness patch Tested-by: Jose Maria Casanova Crespo On 05/

Re: [Mesa-dev] [PATCH] intel/fs: Restrict live intervals to the subset possibly reachable from any definition.

El 08/09/17 a las 11:06, Alejandro Piñeiro escribió: > On 08/09/17 02:50, Francisco Jerez wrote: >> Currently the liveness analysis pass would extend a live interval up >> to the top of the program when no unconditional and complete >> definition of the variable is found that dominates all of its u

Re: [Mesa-dev] [PATCH 41/47] i965/fs: Add reuse_16bit_conversions_register optimization

Hi Connor and Curro, On 28/08/17 12:24, Alejandro Piñeiro wrote: > On 27/08/17 20:24, Connor Abbott wrote: >> Hi, >> >> On Aug 25, 2017 9:28 AM, "Alejandro Piñeiro" > > wrote: >> >> On 24/08/17 21:07, Connor Abbott wrote: >> > >> > Hi Alejandro, >> >> H

Re: [Mesa-dev] [PATCH v2] i965/fs: Define new shader opcode to set rounding modes

On 05/09/17 23:41, Francisco Jerez wrote: > Alejandro Piñeiro writes: > >> Although it is possible to emit them directly as AND/OR on brw_fs_nir, >> having a specific opcode makes it easier to remove duplicate settings >> later. >> >> v2: (Curro) >> - Set thread control to 'switch' when using

Re: [Mesa-dev] [PATCH 20/47] i965/fs: Define new shader opcodes to set rounding modes

On 29/08/17 21:18, Francisco Jerez wrote: > Chema Casanova writes: > >> El 25/08/17 a las 20:09, Francisco Jerez escribió: >>> Alejandro Piñeiro writes: >>> >>>> Although it is possible to emit them directly as AND/OR on brw_fs_nir, >>>

Re: [Mesa-dev] [PATCH 20/47] i965/fs: Define new shader opcodes to set rounding modes

El 25/08/17 a las 20:09, Francisco Jerez escribió: > Alejandro Piñeiro writes: > >> Although it is possible to emit them directly as AND/OR on brw_fs_nir, >> having specific opcodes makes it easier to remove duplicate settings >> later. >> >> Signed-off-by: Alejandro Piñeiro >> Signed-off-by: J

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