from:"Raffaele Recalcati"

What happen normally in runtime pm implementation is that every devices
are switched off and are enabled only when needed.
In our case instead we have a completely functional embedded system and,
when an asyncrhonous event appear, we have only some tens milliseconds
before the actual power failure takes place.
This patchset add a support in order to switch off not vital part of the system,
in order to allow the board to survive longer.
This allow the possibility to save important data.

The implementation has been written by Davide Ciminaghi.
My work instead was about analyzing different previuos implementation,
a first completely custom one, a second using runtime pm, arriving
finally to that one.

I have tested PM loss in our DaVinci dm365 basi board and I write here below a
piece of code showing a possible usage.

---

static int powerfail_status;

static irqreturn_t basi_powerfail_stop(int irq, void *dev_id);

static irqreturn_t basi_powerfail_quick_check_start(int irq, void *dev_id)
{
basi_mask_irq_gpio0(IRQ_DM365_GPIO0_2);
basi_unmask_irq_gpio0(IRQ_DM365_GPIO0_0);

/* PowerFail situation - START: power is going away */
return IRQ_WAKE_THREAD;
}

static irqreturn_t basi_powerfail_start(int irq, void *dev_id)
{
if (powerfail_status)
return IRQ_HANDLED;
powerfail_status = 1;
pm_loss_power_changed(SYS_PWR_FAILING);
return IRQ_HANDLED;
}


static irqreturn_t basi_powerfail_quick_check_stop(int irq, void *dev_id)
{
basi_mask_irq_gpio0(IRQ_DM365_GPIO0_0);
basi_unmask_irq_gpio0(IRQ_DM365_GPIO0_2);

/* PowerFail situation - STOP: power is coming back */
return IRQ_WAKE_THREAD;
}

static irqreturn_t basi_powerfail_stop(int irq, void *dev_id)
{
if (!powerfail_status)
return IRQ_HANDLED;
powerfail_status = 0;
pm_loss_power_changed(SYS_PWR_GOOD);
return IRQ_HANDLED;
}

enum basi_pwrfail_prio {
BASI_PWR_FAIL_PRIO_0,
BASI_PWR_FAIL_MIN_PRIO = BASI_PWR_FAIL_PRIO_0,
BASI_PWR_FAIL_PRIO_1,
BASI_PWR_FAIL_PRIO_2,
BASI_PWR_FAIL_PRIO_3,
BASI_PWR_FAIL_MAX_PRIO = BASI_PWR_FAIL_PRIO_3,
};

struct pm_loss_default_policy_item basi_pm_loss_policy_items[] = {
{
.bus_name = mmc,
.bus_priority = BASI_PWR_FAIL_PRIO_1,
},
{
.bus_name = platform,
.bus_priority = BASI_PWR_FAIL_PRIO_2,
},
};

#define BASI_POLICY_NAME basi-default

struct pm_loss_default_policy_table basi_pm_loss_policy_table = {
.name = BASI_POLICY_NAME,
.items = basi_pm_loss_policy_items,
.nitems = ARRAY_SIZE(basi_pm_loss_policy_items),
};

static void basi_powerfail_configure(void)
{
int stat;
struct pm_loss_policy *p;
stat = request_threaded_irq(IRQ_DM365_GPIO0_2,
basi_powerfail_quick_check_start,
basi_powerfail_start,
0,
pwrfail-on, NULL);
if (stat  0)
printk(KERN_ERR request_threaded_irq for IRQ%d (pwrfail-on) 
   failed\n, IRQ_DM365_GPIO0_2);
stat = request_threaded_irq(IRQ_DM365_GPIO0_0,
basi_powerfail_quick_check_stop,
basi_powerfail_stop, 0,
pwrfail-off, NULL);
if (stat  0)
printk(KERN_ERR request_threaded_irq for IRQ%d (pwrfail-off) 
   failed\n, IRQ_DM365_GPIO0_0);
basi_mask_irq_gpio0(IRQ_DM365_GPIO0_0);
p = pm_loss_setup_default_policy(basi_pm_loss_policy_table);

if (!p)
printk(KERN_ERR Could not register pwr change policy\n);

if (pm_loss_set_policy(BASI_POLICY_NAME)  0)
printk(KERN_ERR Could not set %s power loss policy\n,
   BASI_POLICY_NAME);
}

int platform_pm_loss_power_changed(struct device *dev,
   enum sys_power_state s)
{
int ret = 0;

/* Calling platform bus pm_loss functions */
pr_debug_pm_loss(platform_pm_loss_power_changed(%d)\n, s);

if (dev-driver  dev-driver-pm 
dev-driver-pm-power_changed)
ret = dev-driver-pm-power_changed(dev, s);
return ret;
}




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[PATCH 1/4] export bus_kset

From: Davide Ciminaghi cimina...@gnudd.com

Signed-off-by: Davide Ciminaghi cimina...@gnudd.com
---
 drivers/base/bus.c  |3 ++-
 include/linux/kobject.h |2 ++
 2 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/base/bus.c b/drivers/base/bus.c
index 000e7b2..2134248 100644
--- a/drivers/base/bus.c
+++ b/drivers/base/bus.c
@@ -158,7 +158,8 @@ static const struct kset_uevent_ops bus_uevent_ops = {
.filter = bus_uevent_filter,
 };
 
-static struct kset *bus_kset;
+struct kset *bus_kset;
+EXPORT_SYMBOL(bus_kset);
 
 
 #ifdef CONFIG_HOTPLUG
diff --git a/include/linux/kobject.h b/include/linux/kobject.h
index 8f6d121..456b20d 100644
--- a/include/linux/kobject.h
+++ b/include/linux/kobject.h
@@ -205,6 +205,8 @@ extern struct kobject *power_kobj;
 /* The global /sys/firmware/ kobject for people to chain off of */
 extern struct kobject *firmware_kobj;
 
+extern struct kset *bus_kset ;
+
 #if defined(CONFIG_HOTPLUG)
 int kobject_uevent(struct kobject *kobj, enum kobject_action action);
 int kobject_uevent_env(struct kobject *kobj, enum kobject_action action,
-- 
1.7.0.4

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[PATCH 3/4] mmc: bus and block device drivers: support for pm_loss

From: Davide Ciminaghi cimina...@gnudd.com

Signed-off-by: Davide Ciminaghi cimina...@gnudd.com
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 drivers/mmc/card/block.c |   48 +++-
 drivers/mmc/core/bus.c   |   49 +
 2 files changed, 90 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index bfc8a8a..c88afef 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -37,6 +37,9 @@
 #include linux/mmc/mmc.h
 #include linux/mmc/sd.h
 
+#include linux/pm.h
+#include linux/pm_loss.h
+
 #include asm/system.h
 #include asm/uaccess.h
 
@@ -755,14 +758,55 @@ static int mmc_blk_resume(struct mmc_card *card)
}
return 0;
 }
-#else
+
+#ifdef CONFIG_PM_LOSS
+
+#define dev_to_mmc_card(d) container_of(d, struct mmc_card, dev)
+
+static int mmc_blk_power_changed(struct device *dev,
+enum sys_power_state s)
+{
+   struct mmc_card *card = dev_to_mmc_card(dev);
+   struct mmc_blk_data *md = mmc_get_drvdata(card);
+
+   switch (s) {
+   case SYS_PWR_GOOD:
+   pr_debug_pm_loss(mmc_blk_power_changed(%d)\n, s);
+   mmc_blk_set_blksize(md, card);
+   mmc_queue_resume(md-queue);
+   break;
+   case SYS_PWR_FAILING:
+   pr_debug_pm_loss(mmc_blk_power_changed(%d)\n, s);
+   mmc_queue_suspend(md-queue);
+   break;
+   default:
+   BUG();
+   }
+   return 0;
+}
+
+static const struct dev_pm_ops mmc_blk_pm_ops = {
+   .power_changed = mmc_blk_power_changed,
+};
+
+#define MMC_BLK_DEV_PM_OPS_PTR (mmc_blk_pm_ops)
+
+#else /* !CONFIG_PM_LOSS */
+
+#define MMC_BLK_DEV_PM_OPS_PTR NULL
+
+#endif /* !CONFIG_PM_LOSS */
+
+#else /* !CONFIG_PM */
 #definemmc_blk_suspend NULL
 #define mmc_blk_resume NULL
-#endif
+#define MMC_BLK_DEV_PM_OPS_PTR NULL
+#endif /* !CONFIG_PM */
 
 static struct mmc_driver mmc_driver = {
.drv= {
.name   = mmcblk,
+   .pm = MMC_BLK_DEV_PM_OPS_PTR,
},
.probe  = mmc_blk_probe,
.remove = mmc_blk_remove,
diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c
index 63667a8..548d3a9 100644
--- a/drivers/mmc/core/bus.c
+++ b/drivers/mmc/core/bus.c
@@ -19,6 +19,8 @@
 #include linux/mmc/card.h
 #include linux/mmc/host.h
 
+#include linux/pm_loss.h
+
 #include core.h
 #include sdio_cis.h
 #include bus.h
@@ -163,19 +165,56 @@ static int mmc_runtime_idle(struct device *dev)
return pm_runtime_suspend(dev);
 }
 
+#define MMC_PM_RUNTIME_OPS_INIT \
+.runtime_suspend = mmc_runtime_suspend, \
+.runtime_resume= mmc_runtime_resume, \
+.runtime_idle  = mmc_runtime_idle,
+
+#else /* !CONFIG_PM_RUNTIME */
+
+#define MMC_PM_RUNTIME_OPS_INIT
+
+#endif /* !CONFIG_PM_RUNTIME */
+
+#ifdef CONFIG_PM_LOSS
+
+static int mmc_bus_power_changed(struct device *dev,
+enum sys_power_state s)
+{
+   int ret = 0;
+
+   pr_debug_pm_loss(mmc_bus_power_changed()\n);
+
+   if (dev-driver  dev-driver-pm 
+   dev-driver-pm-power_changed)
+   ret = dev-driver-pm-power_changed(dev, s);
+
+   return ret;
+}
+
+#define MMC_PM_LOSS_OPS_INIT \
+.power_changed =  mmc_bus_power_changed,
+
+#else  /* !CONFIG_PM_LOSS */
+
+#define MMC_PM_LOSS_OPS_INIT
+
+#endif /* !CONFIG_PM_LOSS */
+
+#if defined CONFIG_PM_RUNTIME || defined CONFIG_PM_LOSS
+
 static const struct dev_pm_ops mmc_bus_pm_ops = {
-   .runtime_suspend= mmc_runtime_suspend,
-   .runtime_resume = mmc_runtime_resume,
-   .runtime_idle   = mmc_runtime_idle,
+   MMC_PM_RUNTIME_OPS_INIT
+   MMC_PM_LOSS_OPS_INIT
 };
 
 #define MMC_PM_OPS_PTR (mmc_bus_pm_ops)
 
-#else /* !CONFIG_PM_RUNTIME */
+#else /* !(CONFIG_PM_RUNTIME || CONFIG_PM_LOSS) */
 
 #define MMC_PM_OPS_PTR NULL
 
-#endif /* !CONFIG_PM_RUNTIME */
+#endif /* !(CONFIG_PM_RUNTIME || CONFIG_PM_LOSS) */
 
 static struct bus_type mmc_bus_type = {
.name   = mmc,
-- 
1.7.0.4

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[PATCH 4/4] DaVinci: vpfe: support for pm_loss

From: Raffaele Recalcati raffaele.recalc...@bticino.it

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 drivers/media/video/davinci/vpfe_capture.c |   45 
 1 files changed, 45 insertions(+), 0 deletions(-)

diff --git a/drivers/media/video/davinci/vpfe_capture.c 
b/drivers/media/video/davinci/vpfe_capture.c
index 353eada..21fa9bf 100644
--- a/drivers/media/video/davinci/vpfe_capture.c
+++ b/drivers/media/video/davinci/vpfe_capture.c
@@ -74,6 +74,8 @@
 #include media/v4l2-common.h
 #include linux/io.h
 #include media/davinci/vpfe_capture.h
+#include linux/pm.h
+#include linux/pm_loss.h
 #include ccdc_hw_device.h
 
 static int debug;
@@ -2051,6 +2053,46 @@ static int __devexit vpfe_remove(struct platform_device 
*pdev)
return 0;
 }
 
+#ifdef CONFIG_PM_LOSS
+static int vpfe_capture_power_changed(struct device *dev,
+ enum sys_power_state s)
+{
+   int ret;
+   struct vpfe_device *vpfe_dev = dev_get_drvdata(dev);
+   struct vpfe_subdev_info *sdinfo = vpfe_dev-current_subdev;
+
+   if (!sdinfo)
+   return -EINVAL;
+
+   if (!vpfe_dev-started) {
+   pr_debug_pm_loss(vpfe_capture_power_changed(%d) 
+BUT NOTHING TO DO\n, s);
+   return 0;
+   }
+
+   sdinfo = vpfe_dev-current_subdev;
+
+   switch (s) {
+   case SYS_PWR_GOOD:
+   pr_debug_pm_loss(vpfe_capture_power_changed(%d)\n, s);
+   ret = v4l2_device_call_until_err(vpfe_dev-v4l2_dev,
+sdinfo-grp_id,
+video, s_stream, 1);
+   break;
+   case SYS_PWR_FAILING:
+   pr_debug_pm_loss(vpfe_capture_power_changed(%d)\n, s);
+   ret = v4l2_device_call_until_err(vpfe_dev-v4l2_dev,
+sdinfo-grp_id,
+video, s_stream, 0);
+   break;
+   default:
+   BUG();
+   ret = -ENODEV;
+   }
+   return ret;
+}
+#endif /* CONFIG_PM_LOSS */
+
 static int vpfe_suspend(struct device *dev)
 {
return 0;
@@ -2064,6 +2106,9 @@ static int vpfe_resume(struct device *dev)
 static const struct dev_pm_ops vpfe_dev_pm_ops = {
.suspend = vpfe_suspend,
.resume = vpfe_resume,
+#ifdef CONFIG_PM_LOSS
+   .power_changed = vpfe_capture_power_changed,
+#endif
 };
 
 static struct platform_driver vpfe_driver = {
-- 
1.7.0.4

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[PATCH 2/4] PM / Loss: power loss management

From: Davide Ciminaghi cimina...@gnudd.com

On some embedded systems, an asynchronous power failure notification event is
available some tens to hundreds milliseconds before the actual power failure
takes place.
Such an event can be used to trigger some actions, typically shutting down
all non-vital power sinks, thus allowing the board to survive longer to
temporary power losses.

Signed-off-by: Davide Ciminaghi cimina...@gnudd.com
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 Documentation/power/loss.txt |  191 +
 drivers/base/bus.c   |6 +
 drivers/base/init.c  |1 +
 drivers/base/platform.c  |   14 +
 drivers/base/power/Makefile  |2 +
 drivers/base/power/loss.c|  648 ++
 drivers/base/power/power.h   |   14 +
 include/linux/pm.h   |   16 +
 include/linux/pm_loss.h  |  109 +++
 kernel/power/Kconfig |   27 ++
 10 files changed, 1028 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/power/loss.txt
 create mode 100644 drivers/base/power/loss.c
 create mode 100644 include/linux/pm_loss.h

diff --git a/Documentation/power/loss.txt b/Documentation/power/loss.txt
new file mode 100644
index 000..10da89c
--- /dev/null
+++ b/Documentation/power/loss.txt
@@ -0,0 +1,191 @@
+ POWER LOSS MANAGEMENT 
+
+Davide Ciminaghi cimina...@gnudd.com 2011
+
+1. Overview
+
+On some embedded systems, an asynchronous power failure notification event is
+available some tens to hundreds milliseconds before the actual power failure
+takes place.
+Such an event can be used to trigger some actions, typically shutting down
+all non-vital power sinks, thus allowing the board to survive longer to
+temporary power losses. Sometimes, also flash-based block devices can be
+stopped after a power loss event notification has been received. This should
+be useful for mmc devices, for which a sudden power failure while a write
+command is being executed can threaten file system integrity even in case a
+journalling fs is in use.
+Generally speaking, one can expect the course of action taken when a power
+failure warning is received to be deeply system specific. Similarly, the
+mechanism used for power failure notifications can equally be board/platform
+specific. For these reasons, support for power loss management has been split
+into three parts:
+
+   + Generic code (board and driver independent).
+   + Board dependent code.
+   + Power loss policy definition.
+
+The generic part of the code is located under drivers/base/power/loss.c .
+On the other hand, board dependent code and power loss policies definitions
+should live somewhere in the platform/board specific files.
+The header file include/linux/pm_loss.h contains all the pm_loss function
+prototypes, together with definitions of data structures.
+For what concerns power loss policies, the framework already contains a couple
+of predefined policies: nop and default (see later paragraphs for more
+details).
+
+1.1 Sysfs interface.
+
+It can be useful (for instance during tests), to be able to quickly switch
+from one power loss policy to another, or to simulate power fail and resume
+events. To this end, a sysfs interface of the following form has been devised:
+
+/sys/power/loss +
+   |
+   +-- active_policy
+   |
+   +-- policies -+
+   | |
+   | +-- nop
+   | |
+   | +-- default +
+   | |   |
+   | |   +-- bus_table
+   | |
+   | +-- 
+   |
+   +-- pwrfail_sim
+
+2. Details
+
+2.1 Sending events to the power loss management core.
+
+The board specific code shall trigger a power failure event notification by
+calling pm_loss_power_changed(SYS_PWR_FAILING).
+In case of a temporary power loss, the same function shall be called with
+SYS_PWR_GOOD argument on power resume. pm_loss_power_changed() can sleep, so
+it shall not be called from interrupt context.
+
+2.3 Effects on bus and device drivers.
+
+One more entry has been added to the device PM callbacks:
+
+   int (*power_changed)(struct device *, enum sys_power_state);
+
+This function can be optionally invoked by power loss policies in case of
+system power changes (loss and/or resume). Of course every bus or device driver
+can react to such events in some specific way. For instance the mmc block
+driver will probably block its request queue during a temporary power loss.
+
+2.3.1 The platform bus.
+
+For what concerns platform bus drivers, platform specific code can override
+the power_changed() callback :
+
+platform_pm_loss_power_changed(struct device *dev, enum sys_power_state s)
+
+whose default (empty) version is defined as a __weak symbol in
+drivers/base/platform.c.
+
+2.4 Power

being a maintainer inside a company

2011-04-19 Thread Raffaele Recalcati

I'm being involved in u-boot and kernel responsability inside my
company from many years.
I write code and there are other developers writing code that I need
to coordinate.
By now I have managed all patches incoming using a separated devel
branch, validating those patches and after applying on master branch.
The reason to do that was given by my company e-mail account (or
probably the mail router) that is not able to send cleanly the body.
How can I specify the router/? specifications in order to work in a human way?
It is 'mutt' a good advice to select some patches incoming and apply
automatically to the devel branch?
Anybody else has faced and solved this kind of issue?

Hoping in some good ideas,
Raffaele

-- 
www.opensurf.it
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mmc and Davinci

2011-03-15 Thread Raffaele Recalcati

I have Toshiba v4.3 running with arago kernel and some problems on
other v4.4 and v4.4.1 (Sandisk).
Instead with latest 2.6.38-rc8 davinci-opensource kernel v4.4.1
Sandisk works nice.
Looking at linux-mmc ml I see a lot of work on eMMC and I'm afraid
that I should switch from 2.6.32 arago to davinci-opensource kernel
for better eMMC compatibility, even if I need time to do that and I
need also video codecs working.
Maybe it is a question for e2e, but I'd like some comments about this issue.

Regards,
Raffaele
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named gpio for DaVinci

2011-03-07 Thread Raffaele Recalcati

It looks nice the https://patchwork.kernel.org/patch/1578/ discussion
and the possible implementation in
drivers/gpio/pca953x.c.
But, in DaVinci situation, it would require to modify
davinci_gpio_setup getting gpio names
from a new gpio platform_device.
At the moment I will use gpio number to manage the gpios from user-space.
But I really prefer to go to named gpios.
Any idea?
If a gpio platform device seems a good idea I'll move to this
direction implementing it.

Regards,
Raffaele
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Re: Recent kernel for DM365 and status of the staging tree

2011-02-22 Thread Raffaele Recalcati

My need for a recent kernel involves mmc management and a clean way to sync
and suspend it quikly while the power is going away (an irq advise me 100ms
before powerdown).
Regarding video capability I need yuv422 to yuv420 conversion for pal and
h264 encoding for pal and 720p formats.

Thx,
Raffaele
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Re: Kernel Memory Leak

2011-02-20 Thread Raffaele Recalcati

Hi Steve,

 OOM killer may (and often does) affect system stability and cause
 unexpected behavior.

We should have a daemon that re-stabilize the system in any case,
re-launching processes killed. But, obvioulsy, that daemon has not be
killed by oom_killer.

 I have create a small and easy memory mapper tool using a list of pointer.
 When you press '+' on the cmdline 1MB are malloc'ed and filled of data.
 The opposite when you press '-'.
 So you are sure that the memory can be used.

 I'm still searching instead a way to know how much memory can be used
 without using it.

 I suspect some combination of  parameters in /proc/meminfo and
 /proc/buddyinfo will give you that information.

I don't think so.
After startup the free memory decreases.
Even if you do some free call it doesn't increase, because of VFS
caching (nice for performance, not for know how much memory is really
free).
Maybe latest kernels are more sincer.

Due to rapidly declining price
 of memory, the savings in memory may not justify the engineering cost.

You are absolutely right, but to know how much memory is really free I
think it is important.
At least I'd like to find any memory leakage, that can make our system
unstable even if with a lot of ram.

 Yes, thank you for sharing your insights.

nice,
Raffaele
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Re: Kernel Memory Leak

2011-02-19 Thread Raffaele Recalcati

Hi Steve,

 In general, the Linux kernel tries to cache as much data in memory as
 possible in order to improve performance.  Therefore, it is quite
 normal to see decreasing free memory over time.  As long as the kernel
 is able to free memory cache when needed, there are no issues.

I saw many times free memory reducing in many arm systems.
Normally, for example when 3MB remain and I tried a malloc of 4MB
(writing also data in it .. because I don't trust 'disabling over
commit') the kernel frees tha pages needed and goes on.
If the ram is really finishing, the kernel kills, launching a function
called oom_killer (http://linux-mm.org/OOM_Killer), at least one
process, and then goes on.

I have create a small and easy memory mapper tool using a list of pointer.
When you press '+' on the cmdline 1MB are malloc'ed and filled of data.
The opposite when you press '-'.
So you are sure that the memory can be used.

I'm still searching instead a way to know how much memory can be used
without using it.
I'd like to work on a system with not enough ram to make every process
working simultaneously.

Hoping it helps,
Raffaele
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Re: TI DaVinci support under new maintainer: Sekhar Nori

2011-02-12 Thread Raffaele Recalcati

Hi Kevin,

On Tue, Feb 8, 2011 at 10:54 PM, Kevin Hilman khil...@ti.com wrote:
 Hello,

 I will be stepping aside as maintainer of the TI DaVinci family of
 SoCs and Sekhar Nori from TI will be taking over these responsibilities.

 Sekhar has long been an active developer, primary contributor and
 reviewer so taking over the maintainer role is a logical next step for
 him.

 I will aid in the transition for a couple merge windows to help make a
 smooth transition, but will be fading away from an active role in
 davinci.

Your help has been very useful in the past to guide me to achieve a
small community role..
I can understand that you have new interests.
I think that Nori Sekhar has a deep experience and I'm happy for this decision.
See you in some other ml.

bye,
Raffaele
Raffaele
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dm365 and eMMC

2011-01-11 Thread Raffaele Recalcati

I'm looking at using dm365 with eMMC storage.
There is a strong limitation in respect of SD card, because, mmc dm365
peripheral can use only one bit of data and a max clock of 20Mhz.
Is there any possibility to overcome this limit?

Thanks,
Raffaele
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Thx for mmc in u-boot

2010-12-10 Thread Raffaele Recalcati

I was thinking to get crazy for having a v4.4 mmc working with dm365,
instead with latest u-boot in ti tree mmc works out of the box.
Thank you!
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Re: dm365 ccdc and newer isif

2010-12-10 Thread Raffaele Recalcati

On Sat, Dec 11, 2010 at 7:48 AM, Raffaele Recalcati
lamiapost...@gmail.com wrote:
 Differently from 2.6.32, the isif.c is setting pinmux in platform_device.
 This is very nice, because YIN4 pinmux setting was overwriting mine.
 I'll all this behaviour also to 2.6.32.


But I'd like to set

static void dm365_isif_setup_pinmux(void)
{
davinci_cfg_reg(DM365_VIN_CAM_WEN);
davinci_cfg_reg(DM365_VIN_CAM_VD);
davinci_cfg_reg(DM365_VIN_CAM_HD);
davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
}
in board file, due to 16bit or 8bit port selection

In my case I'd like
static void dm365_basi_isif_setup_pinmux(void)
{
davinci_cfg_reg(DM365_VIN_CAM_WEN);
davinci_cfg_reg(DM365_VIN_CAM_VD);
davinci_cfg_reg(DM365_VIN_CAM_HD);
}

Is there a clean way to do this?

Thx,
Raffaele
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Re: help : DM365 JPEG decoder error 0x8800

2010-12-05 Thread Raffaele Recalcati

On Sun, Dec 5, 2010 at 8:11 AM,  tlzjhtl...@gmail.com wrote:
 hi, everyone,
 I have resolved the problem,
 if I set the input buffer size of jpeg file length, the decoder will fail,
 so I add the input buffer size with 1024, the decoder will success then.
 it's,
 inbuf.descs[0].bufSize = jpg_len + 1024;
 But I don't know what's wrong with it.
 Best regards
 Frank
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Thank you for having posted also the solution.
I'll work on encoding, but your information can be useful also for me!

Bye,
Raffaele
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Re: IPIPE issue in DM365

2010-12-04 Thread Raffaele Recalcati

Hi Albert,

On Mon, Aug 16, 2010 at 1:17 PM, hitesh hitesh.pa...@einfochips.com wrote:

  Thanks  Albert for your prompt response..

 If my application want to allocate memory  and I want to pass that memory
 to IPIPE module then
 what should be the parameter?
 Do you have any sample application that only doing chroma conversion from
 422 to 420 without resizing of width and height?
 My application getting kernel panic as below.


I need to do this because the PAL video in, YUV422 need to be converted to
YUV420 before it can be compressed to H264 by HDVICP.
I also need to integrate it in gstreamer.
Can you point me to the right direction?

Regards,
Raffaele





 Read from file done
 hResizerHandle 0x2f6c0,srcOffset 0x8ba3e000,destOffset 0x8b87c000
 Again in Hell1
 Again in Hell22
 Unable to handle kernel NULL pointer dereference at virtual address
 
 Resize operationpgd = c41f
  completed succe[] *pgd=8770f031ssfully.Write to, *pte=
 file done
 cou, *ppte=nt 13
 file read

 Read from fileInternal error: Oops: 817 [#1]
 Modules linked in: dm365mmap edmak irqk cmemk
 CPU: 0
 PC is at nfs_update_request+0x194/0x36c
 LR is at radix_tree_node_alloc+0x24/0x5c
 pc : [c0120798]lr : [c01d68dc]Not tainted
 sp : c41dbc70  ip : c057c960  fp : c41dbcb4
 r10: c40f8a10  r9 : c40f8918  r8 : 
 r7 : c40f89f0  r6 : c44863a0  r5 : ffef  r4 : 
 r3 : ffef  r2 : 0001  r1 : c33e7ee8  r0 : ffef
 Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  Segment user
 Control: 5317F
 Table: 841F  DAC: 0015
 Process resizer_test (pid: 830, stack limit = 0xc41da258)
 Stack: (0xc41dbc70 to 0xc41dc000)

 -Hitesh




 On 08/16/2010 03:47 PM, Albert Burbea wrote:

  Hi
 seems strange to me that you use
 convert.in_buff.index = 0;
 convert.out_buff1.index = 0;
 with the same index.
 In the dvsdk for DaVinci (2.1 to the best of my knowledge) you should use
 -1 for buffers that have not been allocated by the resizer itself.
 I hope this did not confuse you
 Albert

  On Mon, Aug 16, 2010 at 11:18 AM, hitesh hitesh.pa...@einfochips.comwrote:

  Hi All,

 I am facing memory leak issue in Chroma Conversion module of  DM365 IPIPE.
 When I run the ioctl(resizer_fd, RSZ_RESIZE, convert) ioctl, It increase
 my memory usage and it is gradually increasing it in
 every call of of ioctl. Do you have any solution? I want to do chroma
 conversion for encode my video with H264 encoder.

 My configuration for IPIPE is as below.
INPUT_WIDTH =1280
INPUT_HEIGHT =720

 rsz_ss_config.input.image_width = INPUT_WIDTH;
rsz_ss_config.input.image_height = INPUT_HEIGHT;
rsz_ss_config.input.ppln = rsz_ss_config.input.image_width + 8;
rsz_ss_config.input.lpfr = rsz_ss_config.input.image_height + 10;
rsz_ss_config.input.pix_fmt = IPIPE_UYVY;
rsz_ss_config.output1.pix_fmt = IPIPE_YUV420SP;
rsz_ss_config.output1.enable = 1;
rsz_ss_config.output1.width = INPUT_WIDTH;
rsz_ss_config.output1.height = INPUT_HEIGHT;
rsz_ss_config.output2.enable = 0;

rsz_chan_config.oper_mode = IMP_MODE_SINGLE_SHOT;
rsz_chan_config.chain = 0;


 I am calling ioctl as below.

  convert.in_buff.buf_type = IMP_BUF_IN;
convert.in_buff.index = 0;
convert.in_buff.offset = buf_in[0].offset;
convert.in_buff.size = buf_in[0].size;
convert.out_buff1.buf_type = IMP_BUF_OUT1;
convert.out_buff1.index = 0;
convert.out_buff1.offset = buf_out1[0].offset;
convert.out_buff1.size = buf_out1[0].size;
if (ioctl(resizer_fd, RSZ_RESIZE, convert)  0) {
perror(Error in doing preview\n);
munmap(input_buffer, buf_in[0].size);
munmap(output_buffer, buf_out1[0].size);
close(resizer_fd);
fclose(inp_f);
fclose(outp_f);
exit(1);
}



 Thanks
 Hitesh


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 Tel/Fax + 972-3-7526016
 Mobile: +972-52-3541842


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Re: setting gpios pinmux on a custom board

2010-12-01 Thread Raffaele Recalcati

On Wed, Dec 1, 2010 at 1:04 PM, Sergei Shtylyov sshtyl...@mvista.com
wrote:
 Hello.

 On 30-11-2010 23:02, Raffaele Recalcati wrote:

   Looking at dm365.c I see that the pinmux settings are thinked for a
   particular case.
   How can I, in a clean way, to set my settings?

   By calls to davinci_cfg_reg() or davinci_cfg_reg_list()

   ok, I'm doing that.

   Can I override for instance dm365_pins in davinci_soc_info_dm365
   structure with my
   settings for my basi board, dm365_basi_pins?
   No, and you don't need to. These specify the layout of the PinMux
   registers and are used by davinci_cfg_reg().

   The problem is, for instance, that UART1_TX can be used on two (or
 more?)
 gpios.

   Sorry, I don't understand you.

 UART1_TXD can be GIO25 or GIO16 instead in dm365 we have one of them

   Ah, you mean that UART1_TX has alternate function as GPIO... even as 2
 GPIOs...

 MUX_CFG(DM365,  UART1_TXD,  3,   15,3,2, false)

 That means GIO16.
 So I can add :

 MUX_CFG(DM365,  UART1_TXD_GIO16,  3,   29,3,3, false)

   Bits 29-30 control GPIO25, not GIO16.

Yes, I'm sorry.
I'm doing like that.

MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false) /* ENET_TXEN */
MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false) /* ENET_TXC */
MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
MUX_CFG(DM365, UART1_RXD_34, 4, 14, 3, 3, false) /* uart1_rx */
MUX_CFG(DM365, UART1_TXD_25, 3, 29, 3, 3, false) /* uart1_tx */

I have checked all gpios settings,
now I go on checking on my basi board.
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setting gpios pinmux on a custom board

2010-11-30 Thread Raffaele Recalcati

Looking at dm365.c I see that the pinmux settings are thinked for a
particular case.
How can I, in a clean way, to set my settings?
Can I override for instance dm365_pins in davinci_soc_info_dm365
structure with my
settings for my basi board, dm365_basi_pins?
Thx,
Raffaele

static struct davinci_soc_info davinci_soc_info_dm365 = {
.io_desc= dm365_io_desc,
.io_desc_num= ARRAY_SIZE(dm365_io_desc),
.jtag_id_base   = IO_ADDRESS(0x01c40028),
.ids= dm365_ids,
.ids_num= ARRAY_SIZE(dm365_ids),
.cpu_clks   = dm365_clks,
.psc_bases  = dm365_psc_bases,
.psc_bases_num  = ARRAY_SIZE(dm365_psc_bases),
.pinmux_base= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
.pinmux_pins= dm365_pins,
.pinmux_pins_num= ARRAY_SIZE(dm365_pins),
.intc_base  = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
.intc_type  = DAVINCI_INTC_TYPE_AINTC,
.intc_irq_prios = dm365_default_priorities,
.intc_irq_num   = DAVINCI_N_AINTC_IRQ,
.timer_info = dm365_timer_info,
.gpio_base  = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_num   = 104,
.gpio_irq   = IRQ_DM365_GPIO0,
.gpio_unbanked  = 8,/* really 16 ... skip muxed GPIOs */
.serial_dev = dm365_serial_device,
.emac_pdata = dm365_emac_pdata,
.sram_dma   = 0x0001,
.sram_len   = SZ_32K,
};


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Re: setting gpios pinmux on a custom board

2010-11-30 Thread Raffaele Recalcati

sshtyl...@mvista.com ha scritto:
 Hello.
 Raffaele Recalcati wrote:

 Looking at dm365.c I see that the pinmux settings are thinked for a
 particular case.
 How can I, in a clean way, to set my settings?

 By calls to davinci_cfg_reg() or davinci_cfg_reg_list()

 ok, I'm doing that.

 Can I override for instance dm365_pins in davinci_soc_info_dm365
 structure with my
 settings for my basi board, dm365_basi_pins?
 No, and you don't need to. These specify the layout of the PinMux
 registers and are used by davinci_cfg_reg().

 The problem is, for instance, that UART1_TX can be used on two (or more?)
gpios.

 Sorry, I don't understand you.

UART1_TXD can be GIO25 or GIO16 instead in dm365 we have one of them

MUX_CFG(DM365,  UART1_TXD,  3,   15,3,2, false)

That means GIO16.
So I can add :

MUX_CFG(DM365,  UART1_TXD_GIO16,  3,   29,3,3, false)

The same can be said for other peripherals, because the same periperal can
be available using different pins.

 So I'll need to add more MUX_CFG lines..
 UART1_TX_GIOx
 UART1_TX_GIOy
 and then select the one I'm really using on my board.

 Still don't understand what you mean.

 I'm afraid that setting gpios in my board file is not enough, because
 I see that other modules change my settings and I'm getting crazy to
 find where they set.
 I'll search tomorrow the MUX_CFG defines around in my kernel.

 They should all be in dm365.c...

I check better in the latest kernel...

Regards,
Raffaele
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New sched fantastic patch

2010-11-28 Thread Raffaele Recalcati

Looking at
http://lkml.org/lkml/2010/10/19/123
I ask if anyone knows if this patch is good for embedded arm frame buffer or
X  2.6.32 , or the same with 2 6.36.
Thx, Raffaele
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Re: tvp5150 extension to tvp5151

2010-11-22 Thread Raffaele Recalcati

On Mon, Nov 22, 2010 at 12:32 PM, Mauro Carvalho Chehab
mche...@infradead.org wrote:
 Hi Raffaele,

 Em 19-11-2010 16:26, Raffaele Recalcati escreveu:
 I need to support fully tvp5151.
 So I'm trying to understand your driver, that is ready for VBI and not
 for video acquisition.
 I also take sometimes a look at tvp514x.c, for instance trying to add
 VIDIOC_ENUM_FMT and other ioctls.
 I think we can move from tvp5150.c to tvp515x.c, maybe...
 I don't think is good to have tvp51xx.c because tvp514x.c family is
 more complex (more inputs...).
 By now I'm using tvp5150.c with some modifications and video acquisition 
 works.
 I need to complete the support in order to have gstreamer fully running.
 I'm working on 2.6.32, but I have planned to port it to mainline.

 Renaming it to tvp515x.c and adding support for tvp5051 seems a good way.
 With tvp5150, video acquisition works fine with several devices with em28xx,
 although we may need to add more video formats at the media bus, depending
 on what you're doing. I didn't test VBI support on it, because the devices
 I have are based on em28xx, and I didn't find any way to capture the VBI
 decoded packages and sent to userspace with that design. So, the basic stuff
 is there, but maybe some adjusts may be needed for VBI.

 Do you have any suggestion for my work?

 The better is to submit the patches you have, for us to apply upstream.

Thx for your reply..
I have added many v4l2 support similar to tvp514x.
I need to test them, hoping they work.
When all we'll be ok I'll send patches.
So I go on renaming all strings from tvp5150 to tvp515x.

Thx,
Raffaele
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Re: DVDSK Installer for DM365 And DM6446

2010-11-15 Thread Raffaele Recalcati

On Fri, Nov 12, 2010 at 10:01 AM, Sean Preston se...@pfk.co.za wrote:
 Hi

 I have recently started to work on the Davinci family of processors. I am
 looking for a DVSDK package for DM365 and DM6446 processors.
 I have downloaded dvsdk_setuplinux_2_00_00_22.bin for DM6446 and I
 tried to build all the components, however I could not. I want to use open
 source kernel, codesourcery toolchain and have the control to build all
 the
 individual components like dsplink, dmai, framework etc

 Looking for some recommended version of DVSDK. Thanks.

 As far as the DM365 goes you can find the latest v4 DVSDK at this URL:
 http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/dvsdk/DVS
 DK_4_00/latest/index_FDS.html

 This uses Code Sourcery for the toolchain and Arago (based on OpenEmbedded)
 for the filesystem.

stay tuned here
http://e2e.ti.com/support/embedded/f/354.aspx


 Regards
 Sean

 --
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 Software Engineer
 Email: se...@pfk.co.za

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tvp5151: driver

2010-11-10 Thread Raffaele Recalcati

I'm writing this driver against the head of arago linux davinci kernel.
After that I'll try to port it to latest linux.davinci kernel.
Just to be sure isn't anybody working on it, or , if present, to share
considerations.

Thx,
Raffaele

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Re: tvp5151: driver

2010-11-10 Thread Raffaele Recalcati

On Wed, Nov 10, 2010 at 12:45 PM, Hans Verkuil hverk...@xs4all.nl wrote:
 Hi Raffaele,

 There is already a tvp5150.c driver available. Are there many changes
 between tvp5150 and tvp5151? If the differences are fairly limited, then
 it might make more sense to adapt tvp5150.c.

right
guessing to move to tvp515x.c (similarly to tvp514x).
I proceed this way.

 Please upstream the work you are doing into the mainline kernel as well!
 The linux-media mailinglist (www.linuxtv.org) is the best place to post
 the patches and get help.

trying.
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Re: problem with serial console

2010-10-11 Thread Raffaele Recalcati

On Mon, Oct 4, 2010 at 11:57 AM, kunal singh pahelipra...@gmail.com wrote:
 Hi all,

   I have not been able to fix the issue with early printk. I still believe
 that it is not supported in the 2.6.32 open source kernel for davinci.
   However, I was able to fix problem with the kernel (by trial and error)
 and kernel boot is ok now.

How did you fix it?
Something about earlycon?
Thx


   Thanks every one for your help on this issue.

 Regards,
 Kunal

 On Sun, Oct 3, 2010 at 10:46 AM, kunal singh pahelipra...@gmail.com wrote:

 While doing the early console set up, there is a function call to
 drivers/serial/8250_early.c/serial8250_find_port_For_earlycon()

 The above function always returns with an error condition. It does checks
 on the early_device and these checks fail (it fails because the
 early_device.port is un-initialized).

 I checked the code and see that early_device (which is a static variable)
 is never intialzed any where in the code drivers/serial/8250_early.c. I
 wonder if the earlycon support has been added for 2.6.32 kernel? any
 suggestions?

 On Thu, Sep 30, 2010 at 9:18 PM, kunal singh pahelipra...@gmail.com
 wrote:

 Tried with earlyprintk, but the problem persists

 On Thu, Sep 30, 2010 at 8:45 PM, kunal singh pahelipra...@gmail.com
 wrote:

 Hi Hemant,

    No I have not added the earlyprintk. I will investigate this. Shall I
 add earlyprintk=serial,uart0 ?

   BTW, I tried to trace down the printk code flow in kernel/printk.c.
   (1) in the function _call_console_drivers(), __call_console_drivers()
 never gets called [the if() condition is never met].
   (2) May be it probably explains why nothing gets printed on serial? Is
 this because there is no earlyprintk in bootargs?

 Regards,
 kunal




 On Thu, Sep 30, 2010 at 8:19 PM, Pedanekar, Hemant hema...@ti.com
 wrote:

 Just to check: have you added earlyprintk to your bootargs?

 -
 Hemant



 
 From: kunal singh [mailto:pahelipra...@gmail.com]
 Sent: Thursday, September 30, 2010 7:40 PM
 To: Raffaele Recalcati; Nori, Sekhar; Pedanekar, Hemant
 Cc: davinci-linux-open-source@linux.davincidsp.com
 Subject: Re: problem with serial console

 Hi All,


  Thanks a lot for posting the comments here.

  (1) I have added some printascii() statements in function
 init/main.c/start_kernel() to trace the boot sequence
  (a) printascii() to print the command line arguments
  (b) printascii() before doing the console_init()
  (c) printascii() after doing the console_init()

  (2)  The log (posted below) suggests that the boot sequence goes
 beyond console_init(). Since console_init is done I would expect that all 
 my
 printk messages should start to appear on the console . But it does not.
 (however the printascii still works, as you can see messages in the 
 bootlog,
 hence I would assume that hardware is fine)

    I would appreciate if you can give some suggestion on how to debug
 this issue further.

 Thanks,
 kunal


 /* HERE IS THE BOOT LOG /
 run devboot
 TFTP from server 10.0.0.1; our IP address is 10.0.0.3
 Filename '/home/kunal/xcaster/ingenient-bsp/images/uImage'.
 Load address: 0x8200
 Loading: #T
 

 #
  #T
 

 ##
  ###T ##T
 
  ##T 
 done
 Bytes transferred = 1898780 (1cf91c hex)
 ## Booting image at 8200 ...
    Image Name:   Linux-2.6.32-rc2-davinci1
    Image Type:   ARM Linux Kernel Image (uncompressed)
    Data Size:    1898716 Bytes =  1.8 MB
    Load Address: 80008000
    Entry Point:  80008000
    Verifying Checksum ... OK
 OK

 Starting kernel ...

 Uncompressing
 Linux...
 done, booting the kernel.

 console=ttyS0,115200n8 root=/dev/nfs rw
 nfsroot=10.0.0.1:/home/kunal/xcaster/ingenient-bsp/rootfs/fs,udp,v3,rsize=4096,wsize=1400
 ip=10.0.0.3:10.0.0.1:10.0.0.1:255.255.255.0:XCASTER5000::off mem=128M
 mtdparts=davinci-nand.0:96k(ubl),736k(uboot),64k(uboot-env),2m(kernel),61568k(app)
 eth=80:4C:EF:54:87:0A
 doing console init now
 finished console init

 /***/


 On Thu, Sep 30, 2010 at 6:26 PM, Raffaele Recalcati
 lamiapost...@gmail.com wrote:

 On Thu, Sep 30, 2010 at 2:35 PM, kunal singh pahelipra...@gmail.com
 wrote:
  Hi Raffaele,
 
    Thanks for the suggestion.
 
   (1)  Console is fine. I am able to communicate with the u-boot
  (115200,n8).
  Also if I use printascii (a kernel function) I am able to output on
  console.
   (2) There is no message, after the kernel

Re: net example?

2010-10-11 Thread Raffaele Recalcati

On Mon, Oct 11, 2010 at 10:44 AM, Andrea Gasparini gaspar...@imavis.com wrote:
 Hi,
 perhaps a recurring question: is there an example of a net driver that
 makes heavy use of edma ?

Normally a net driver doesn't use, it is instead used.
If you are thinking about net performances you can launch on your
board (ip addr = 10.39.10.183):
iperf -s

And from a PC:
iperf -c 10.39.10.183 -w 64k
(64k means 128k, due to an iperf known issue)

You will need to reach the following performances, if dm365 is your case:
http://processors.wiki.ti.com/index.php/DaVinci_PSP_03.01_GA_%28r37%29_Release_Notes#Performance_-_DM365_EVM

The only problem is that the packets, arriving to dm365 board, are
going to be discarded and I don't know if they are copied to the
user-space.
If you can do:
strace iperf -s
and check if the copy is done you will have the answer you need.

bye,
Raffaele
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Re: problem with serial console

2010-09-30 Thread Raffaele Recalcati

On Thu, Sep 30, 2010 at 2:35 PM, kunal singh pahelipra...@gmail.com wrote:
 Hi Raffaele,

   Thanks for the suggestion.

  (1)  Console is fine. I am able to communicate with the u-boot (115200,n8).
 Also if I use printascii (a kernel function) I am able to output on console.
  (2) There is no message, after the kernel decompression (because console is
 not up). Here is what I see.

 Load address: 0x8200
 Loading: T ###T
 ##
  ##
  ##T
 
  #
  ###T
 ##T ##
  ##T 
 done
 Bytes transferred = 1898828 (1cf94c hex)
 ## Booting image at 8200 ...
    Image Name:   Linux-2.6.32-rc2-davinci1
    Image Type:   ARM Linux Kernel Image (uncompressed)
    Data Size:    1898764 Bytes =  1.8 MB
    Load Address: 80008000
    Entry Point:  80008000
    Verifying Checksum ... OK
 OK

 Starting kernel ...

 Uncompressing
 Linux...
 done, booting the kernel.

 /* AND THEN NOTHING BECAUSE CONSOLE IS NOT FUNCTIONAL, but booting goes on
 */

How can you say that boot goes on?
Can you check mem inside bootargs?
For instance I have 128MB RAM and I use these bootargs.

set bootargs 'console=ttyS0,115200n8 rw
ip=10.39.10.183:10.39.10.169:10.39.8.1:255.255.248.0:::off
root=/dev/nfs nfsroot=10.39.10.169:/home/NFS/ARAGO_DEMO_IMAGE-raf/
mem=128M 
video=davincifb:output=lcd:format=rgb:vid0=240x...@0,0:vid1=240x...@0,0:osd0=240x...@0,0:osd1=240x...@0,0
'

Don't copy my bootargs, only do some tests.
I saw your behaviour when mem was wrong.
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Re: problem with serial console

2010-09-29 Thread Raffaele Recalcati

On Wed, Sep 29, 2010 at 4:48 AM, kunal singh pahelipra...@gmail.com wrote:
 Hi,

    MY SETUP
    -
    We have a dm6446 based board  we have been using 2.6.18 (MV) Linux.
 Recently I tried upgrading to kernel 2.6.32 (PSP 03.01).

   PROBLEM
   ---
    When the kernel boots I can not see any boot messages on the  serial
 console. I assume that if the boot flow passes beyond console_init (in
 init/main.c) I should start to receive printk messages on the console. But
 it does not happen so.

    ADDITIONAL INFORMATION
    -
    (1) If use the printascii function (low level debug print) in the
 init/main.c, I can get messages on serial console. So, I assume that nothing
 is wrong with hardware.
    (2) The command line arguments (printed from kernel using printascii)
 show that console=ttyS0,115200n8

   Any idea what could be wrong?

First
Check your setup.
I mean, with the same PC and serial port cable you can read and write
to another device with 115200n8 comfiguration?

Second
You need to copy, in the mail, every messages you have on the serial
line, from power up

Third
Check info here http://processors.wiki.ti.com/index.php/Category:DM644x

Good work,
Raffaele
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Re: Driver

2010-09-11 Thread Raffaele Recalcati

 Hi, I'm a novice embedded engineer who works in a IPTV STB project. We are
 using a DaVinci DM6446 based evaluation board for developing a firmware for
 our STB.  Unfortunetaly I am the only engineer who work in the software
 development side, and  don't have enough backround to deal with problems
 which I encountered.  Could you please enlighten me about these issues

I'm working on DM365 kernel support development for our boards.
I think, first of all, you need to become familiar with www.ti.com and
Ti E2E community.
Design Support -  Ti E2E community
then Support Forums
than Embedded software
and finally Linux ..
Here you can find some help about Ti releases.
But first read carefully the documentation.

 1. I will use the open source Linux DaVinci kernel for development, and I
 didn't understand the driver side, in documents of TI its been said that LSP
 is integrated with Montavista kernel, is it still available to use LSP with
 open community Linux kernel? If it is,how can I do this?

In the case of DM365 (check for DM6446) the PSP kernel release is an
easier way than  open source Linux DaVinci kernel.
Here you have the specifications of the latest PSP release
http://processors.wiki.ti.com/index.php/DaVinci_PSP_03.01_GA_%28r37%29_Release_Notes

 2. Is there any pre-builded open source Linux kernel that all these drivers
 work completely within ?

PSP kernel release is opensource


 3. It seems that the video-display  driver not functional  for Dm644x, in
 the http://processors.wiki.ti.com/index.php/DaVinci_GIT_Linux_Kernel

If not you have to develop it or ask for a roadmap to Ti

 4. What is the difference between LSP and PSP.  I couldn't find any document
 that gives detail about these issues . Could you give me any advice about
 where to start  ?

LSP = montavista
PSP = free and Ti made

Bye,
Raffaele
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Re: [PATCH v4] DaVinci: dm365: Added clockout2 management.

2010-08-24 Thread Raffaele Recalcati

2010/8/5 Kevin Hilman khil...@deeprootsystems.com

 Raffaele Recalcati lamiapost...@gmail.com writes:

  From: Davide Bonfanti davide.bonfa...@bticino.it
 
  Clockout2 is added as a child of pll1_sysclk9.
  A new dm365_clkout2_set_rate is used to set clockout2 frequency.
 
  Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
  Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
  ---
  This patch has been developed against
  http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
  and has been tested for dm365 cpu on BMX board.
  This patch depends on the following one submitted to the mailing list:
  https://patchwork.kernel.org/patch/112994
 
  TODO LIST
  -The clkout2 management needs a recalc function, but I by now I don't
 know how to
  point to it from davinci_clk_init.

 Not sure I follow the problem here, but can't you use the .recalc field
 of 'struct clk'?  What am I missing?


I didn't know it, thx.
I've added the function now.



  -The unmapping of system_module_base has to be checked.

 Looks like you're doing it in this version


ok,



  -Solving a possible race when writing PERI_CLKCTL, see Nori Sekhar
 explanation:
  Looks like the same register supports setting clocks for voice codec
  and keyscan module as well. This can cause a race if those clocks are
  modified in a different context. Can you extend this function to cover
  those clocks as well? May be clk-lpsc can be used to determine if div1,
  div2 or div3 need to be changed. This way you can serialize the setting
  up of these clocks.

 I agree with Sekhar. This needs to be addresed before this patch is
 mergable.


It is more difficult.
Something like the following?

int dm365_peri_clkctl_set_rate(struct clk *clk, unsigned long rate)
{
int i;
unsigned long input;
unsigned ratio;
unsigned regval;
void __iomem *system_module_base;

/* There must be a parent... */
if (WARN_ON(!clk-parent))
return -EINVAL;

input = clk-parent-rate;

if (input  rate)
ratio = DIV_ROUND_UP(input, rate) - 1;

system_module_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE, SZ_4K);
regval = __raw_readl(system_module_base + PERI_CLKCTL);

regval = ~DIV1_MASK;
regval |= ratio  3;

/* to make changes work stop CLOCKOUT  start it again */
regval |= BIT(CLOCKOUT2EN);

   mutex_lock(peri_clkctl_mutex);

__raw_writel(regval, system_module_base + PERI_CLKCTL);
regval = ~(1  CLOCKOUT2EN);
__raw_writel(regval, system_module_base + PERI_CLKCTL);

   mutex_unlock(peri_clkctl_mutex);

iounmap(system_module_base);
return 0;
}









  A fine tuning of clkout2 is possible using the function below (it is
  possible to do something similar with Nori Sekhar work about
 DIV_ROUND_CLOSEST()
  in the davinci_set_sysclk_rate() function (max_rate has to be passed).
 
  static int clkout2_fine_setting(unsigned long rate)
  {
  struct clk *pll1_sysclk9;
  struct clk *clkout2;
  int i, err, min_err, i_min_err;
  int ret = -EINVAL;
 
  pll1_sysclk9 = clk_get(NULL, pll1_sysclk9);
  if (IS_ERR(pll1_sysclk9)) {
  printk(KERN_ERR Could not get pll1_sysclk9\n);
  return -ENODEV;
  }
  clk_enable(pll1_sysclk9);
 
  /* check all possibilities to get best fitting for the required
 freq */
  i_min_err = min_err = INT_MAX;
  for (i = 0x0F; i  0; i--) {
  ret = clk_set_rate(pll1_sysclk9, rate * i);
  err = clk_get_rate(pll1_sysclk9) - rate * i;
  if (min_err  abs(err)) {
  min_err = abs(err);
  i_min_err = i;
  }
  }
 
  /* setting the best one to pll1_sysclk9 */
  ret = clk_set_rate(pll1_sysclk9, rate * i_min_err);
  if (ret)
  return ret;
 
  /* setting the best one to clkout2 */
  clkout2 = clk_get(NULL, clkout2);
  if (IS_ERR(clkout2)) {
  printk(KERN_ERR Could not get clkout2\n);
  return -ENODEV;
  }
  clk_enable(clkout2);
  clk_set_rate(clkout2,rate);
  return 0;
  }
 
 
 
   arch/arm/mach-davinci/dm365.c |   42
 +
   1 files changed, 42 insertions(+), 0 deletions(-)
 
  diff --git a/arch/arm/mach-davinci/dm365.c
 b/arch/arm/mach-davinci/dm365.c
  index 42fd4a4..0101a6c 100644
  --- a/arch/arm/mach-davinci/dm365.c
  +++ b/arch/arm/mach-davinci/dm365.c
  @@ -40,6 +40,40 @@
   #include mux.h
 
   #define DM365_REF_FREQ   2400/* 24 MHz on the
 DM365 EVM */
  +#define DIV1_MASK0x78/* DIV1 mask in PERI_CLKCTL
 */
  +#define PERI_CLKCTL  0x48
  +#define CLOCKOUT2EN  2
  +
  +int

Re: [PATCH v4] DaVinci: dm365: Added clockout2 management.

2010-08-24 Thread Raffaele Recalcati

Sorry, please integrate the previous e-mail with this one...
(I made a mistake sending the e-mail)


  -Solving a possible race when writing PERI_CLKCTL, see Nori Sekhar
 explanation:
  Looks like the same register supports setting clocks for voice codec
  and keyscan module as well. This can cause a race if those clocks are
  modified in a different context. Can you extend this function to cover
  those clocks as well? May be clk-lpsc can be used to determine if div1,
  div2 or div3 need to be changed. This way you can serialize the setting
  up of these clocks.

 I agree with Sekhar. This needs to be addresed before this patch is
 mergable.


 It is more difficult.
 Something like the following?


int dm365_peri_clkctl_set_rate(struct clk *clk, unsigned long rate)
{
int i;
unsigned long input;
unsigned ratio;
unsigned regval;
void __iomem *system_module_base;

/* There must be a parent... */
if (WARN_ON(!clk-parent))
return -EINVAL;

input = clk-parent-rate;

if (input  rate)
ratio = DIV_ROUND_UP(input, rate) - 1;

system_module_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE, SZ_4K);
regval = __raw_readl(system_module_base + PERI_CLKCTL);

switch (clk-lpsc) {
case DM365_LPSC_CLKOUT2:
  regval = ~DIV1_MASK;
  regval |= ratio  3;
  break;
case DM365_LPSC_VOICE_CODEC:
  regval = ~DIV2_MASK;
  regval |= ratio  7;
  break;
case DM365_LPSC_KEYSCAN:
regval = ~DIV3_MASK;
  regval |= ratio  16;
  break;

/* to make changes work stop CLOCKOUT  start it again */
regval |= BIT(CLOCKOUT2EN);

   mutex_lock(peri_clkctl_mutex);
__raw_writel(regval, system_module_base + PERI_CLKCTL);
regval = ~(1  CLOCKOUT2EN);
__raw_writel(regval, system_module_base + PERI_CLKCTL);
   mutex_unlock(peri_clkctl_mutex);

iounmap(system_module_base);
return 0;
}

Obviously a similar modification to the following recalc function will be
needed.

Regards,
Raffaele
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Re: [PATCH v3] DaVinci: dm365: Added clockout2 management.

2010-08-05 Thread Raffaele Recalcati

2010/8/5 Nori, Sekhar nsek...@ti.com

 Hi Raffaele,

 On Wed, Aug 04, 2010 at 21:56:14, Raffaele Recalcati wrote:
  From: Davide Bonfanti davide.bonfa...@bticino.it
 
  Clockout2 is added as a child of pll1_sysclk9.
  A new dm365_clkout2_set_rate is used to set clockout2 frequency.

 I thought a recalculate rate function is needed as well?


I don't know how to point to it in davinci_clk_init

/* Check if clock is a PLL */
if (clk-pll_data)
clk-recalc = clk_pllclk_recalc;

/* Else, if it is a PLL-derived clock */
else if (clk-flags  CLK_PLL)
clk-recalc = clk_sysclk_recalc;

/* Otherwise, it is a leaf clock (PSC clock) */
else if (clk-parent)
clk-recalc = clk_leafclk_recalc;

I need a new type?



 
  Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
  Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
  ---
  This patch has been developed against
 http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.gitand 
 has been tested for dm365 cpu on BMX board.
  This patch depends on the following one submitted to the mailing list:
  https://patchwork.kernel.org/patch/112994
  The clkout2 management has been introduced as leaf clock.
  A fine tuning of clkout2 is possible using the following function
  static int clkout2_fine_setting(unsigned long rate)
  {
  struct clk *pll1_sysclk9;
  struct clk *clkout2;
  int i, err, min_err, i_min_err;
  int ret = -EINVAL;
 
  pll1_sysclk9 = clk_get(NULL, pll1_sysclk9);
  if (IS_ERR(pll1_sysclk9)) {
  printk(KERN_ERR Could not get pll1_sysclk9\n);
  return -ENODEV;
  }
  clk_enable(pll1_sysclk9);
 
  /* check all possibilities to get best fitting for the required
 freq */
  i_min_err = min_err = INT_MAX;
  for (i = 0x0F; i  0; i--) {
  ret = clk_set_rate(pll1_sysclk9, rate * i);
  err = clk_get_rate(pll1_sysclk9) - rate * i;
  if (min_err  abs(err)) {
  min_err = abs(err);
  i_min_err = i;
  }
  }

 Do you really need to go through like this? the same
 'precision' should be achieved by DIV_ROUND_CLOSEST()
 in the davinci_set_sysclk_rate() function if the max_rate
 is passed for the sys clock.


I'll try do understand.



 Anyway, since my patch is not yet accepted and this code
 is not included in the patch I won't bother you further
 with my ideas :)


ok, no problem.



 
  /* setting the best one to pll1_sysclk9 */
  ret = clk_set_rate(pll1_sysclk9, rate * i_min_err);
  if (ret)
  return ret;
 
  /* setting the best one to clkout2 */
  clkout2 = clk_get(NULL, clkout2);
  if (IS_ERR(clkout2)) {
  printk(KERN_ERR Could not get clkout2\n);
  return -ENODEV;
  }
  clk_enable(clkout2);
  clk_set_rate(clkout2,rate);
  return 0;
  }
 
 
   arch/arm/mach-davinci/clock.h |3 +++
   arch/arm/mach-davinci/dm365.c |   41
 +
   2 files changed, 44 insertions(+), 0 deletions(-)
 
  diff --git a/arch/arm/mach-davinci/clock.h
 b/arch/arm/mach-davinci/clock.h
  index a717d98..00c4497 100644
  --- a/arch/arm/mach-davinci/clock.h
  +++ b/arch/arm/mach-davinci/clock.h
  @@ -50,6 +50,9 @@
   #define PLLDIV_EN   BIT(15)
   #define PLLDIV_RATIO_MASK 0x1f
 
  +#define PERI_CLKCTL  0x48
  +#define CLOCKOUT2EN  2

 These defines need to be moved into dm365.c since they are only
 used there.


done


  +
   /*
* OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
* cycles to ensure that the PLLC has switched to bypass mode. Delay of
 1us
  diff --git a/arch/arm/mach-davinci/dm365.c
 b/arch/arm/mach-davinci/dm365.c
  index 42fd4a4..4846b62 100644
  --- a/arch/arm/mach-davinci/dm365.c
  +++ b/arch/arm/mach-davinci/dm365.c
  @@ -40,6 +40,38 @@
   #include mux.h
 
   #define DM365_REF_FREQ   2400/* 24 MHz on the
 DM365 EVM */
  +#define DIV1_MASK0x78/* DIV1 mask in PERI_CLKCTL
 */
  +
  +int dm365_clkout2_set_rate(struct clk *clk, unsigned long rate)
  +{
  + int i;
  + unsigned long input;
  + unsigned ratio;
  + u32 regval;

 Can you either use 'unsigned' or 'u32' instead of mixing them?


  + static void __iomem *system_module_base;


 Why does this have to be static?


ok



  +
  + /* There must be a parent... */
  + if (WARN_ON(!clk-parent))
  + return 0;

 Should return -EINVAL?


right



  +
  + input = clk-parent-rate;
  +
  + if (input  rate)
  + ratio = DIV_ROUND_UP(input

[PATCH v4] DaVinci: dm365: Added clockout2 management.

2010-08-05 Thread Raffaele Recalcati

From: Davide Bonfanti davide.bonfa...@bticino.it

Clockout2 is added as a child of pll1_sysclk9.
A new dm365_clkout2_set_rate is used to set clockout2 frequency.

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
This patch has been developed against 
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git 
and has been tested for dm365 cpu on BMX board.
This patch depends on the following one submitted to the mailing list:
https://patchwork.kernel.org/patch/112994

TODO LIST
-The clkout2 management needs a recalc function, but I by now I don't know how 
to
point to it from davinci_clk_init.
-The unmapping of system_module_base has to be checked.
-Solving a possible race when writing PERI_CLKCTL, see Nori Sekhar explanation:
Looks like the same register supports setting clocks for voice codec
and keyscan module as well. This can cause a race if those clocks are
modified in a different context. Can you extend this function to cover
those clocks as well? May be clk-lpsc can be used to determine if div1,
div2 or div3 need to be changed. This way you can serialize the setting
up of these clocks.

A fine tuning of clkout2 is possible using the function below (it is 
possible to do something similar with Nori Sekhar work about DIV_ROUND_CLOSEST()
in the davinci_set_sysclk_rate() function (max_rate has to be passed).

static int clkout2_fine_setting(unsigned long rate)
{
struct clk *pll1_sysclk9;
struct clk *clkout2;
int i, err, min_err, i_min_err;
int ret = -EINVAL;

pll1_sysclk9 = clk_get(NULL, pll1_sysclk9);
if (IS_ERR(pll1_sysclk9)) {
printk(KERN_ERR Could not get pll1_sysclk9\n);
return -ENODEV;
}
clk_enable(pll1_sysclk9);

/* check all possibilities to get best fitting for the required freq */
i_min_err = min_err = INT_MAX;
for (i = 0x0F; i  0; i--) {
ret = clk_set_rate(pll1_sysclk9, rate * i);
err = clk_get_rate(pll1_sysclk9) - rate * i;
if (min_err  abs(err)) {
min_err = abs(err);
i_min_err = i;
}
}

/* setting the best one to pll1_sysclk9 */
ret = clk_set_rate(pll1_sysclk9, rate * i_min_err);
if (ret)
return ret;

/* setting the best one to clkout2 */
clkout2 = clk_get(NULL, clkout2);
if (IS_ERR(clkout2)) {
printk(KERN_ERR Could not get clkout2\n);
return -ENODEV;
}
clk_enable(clkout2);
clk_set_rate(clkout2,rate);
return 0;
}



 arch/arm/mach-davinci/dm365.c |   42 +
 1 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 42fd4a4..0101a6c 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -40,6 +40,40 @@
 #include mux.h
 
 #define DM365_REF_FREQ 2400/* 24 MHz on the DM365 EVM */
+#define DIV1_MASK  0x78/* DIV1 mask in PERI_CLKCTL */
+#define PERI_CLKCTL0x48
+#define CLOCKOUT2EN2
+
+int dm365_clkout2_set_rate(struct clk *clk, unsigned long rate)
+{
+   int i;
+   unsigned long input;
+   unsigned ratio;
+   unsigned regval;
+   void __iomem *system_module_base;
+
+   /* There must be a parent... */
+   if (WARN_ON(!clk-parent))
+   return -EINVAL;
+
+   input = clk-parent-rate;
+
+   if (input  rate)
+   ratio = DIV_ROUND_UP(input, rate) - 1;
+
+   system_module_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE, SZ_4K);
+   regval = __raw_readl(system_module_base + PERI_CLKCTL);
+   regval = ~DIV1_MASK;
+   regval |= ratio  3;
+
+   /* to make changes work stop CLOCKOUT  start it again */
+   regval |= BIT(CLOCKOUT2EN);
+   __raw_writel(regval, system_module_base + PERI_CLKCTL);
+   regval = ~(1  CLOCKOUT2EN);
+   __raw_writel(regval, system_module_base + PERI_CLKCTL);
+   iounmap(system_module_base);
+   return 0;
+}
 
 static struct pll_data pll1_data = {
.num= 1,
@@ -145,6 +179,13 @@ static struct clk pll1_sysclk9 = {
.parent = pll1_clk,
.flags  = CLK_PLL,
.div_reg= PLLDIV9,
+   .set_rate   = davinci_set_sysclk_rate,
+};
+
+static struct clk clkout2_clk = {
+   .name   = clkout2,
+   .parent = pll1_sysclk9,
+   .set_rate   = dm365_clkout2_set_rate,
 };
 
 static struct clk pll2_clk = {
@@ -421,6 +462,7 @@ static struct clk_lookup dm365_clks[] = {
CLK(NULL, pll1_sysclk7, pll1_sysclk7),
CLK(NULL, pll1_sysclk8, pll1_sysclk8),
CLK(NULL, pll1_sysclk9, pll1_sysclk9),
+   CLK(NULL, clkout2, clkout2_clk

[PATCH v3] DaVinci: dm365: Added clockout2 management.

2010-08-04 Thread Raffaele Recalcati

From: Davide Bonfanti davide.bonfa...@bticino.it

Clockout2 is added as a child of pll1_sysclk9.
A new dm365_clkout2_set_rate is used to set clockout2 frequency.

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
This patch has been developed against 
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git and 
has been tested for dm365 cpu on BMX board.
This patch depends on the following one submitted to the mailing list:
https://patchwork.kernel.org/patch/112994
The clkout2 management has been introduced as leaf clock.
A fine tuning of clkout2 is possible using the following function
static int clkout2_fine_setting(unsigned long rate)
{
struct clk *pll1_sysclk9;
struct clk *clkout2;
int i, err, min_err, i_min_err;
int ret = -EINVAL;

pll1_sysclk9 = clk_get(NULL, pll1_sysclk9);
if (IS_ERR(pll1_sysclk9)) {
printk(KERN_ERR Could not get pll1_sysclk9\n);
return -ENODEV;
}
clk_enable(pll1_sysclk9);

/* check all possibilities to get best fitting for the required freq */
i_min_err = min_err = INT_MAX;
for (i = 0x0F; i  0; i--) {
ret = clk_set_rate(pll1_sysclk9, rate * i);
err = clk_get_rate(pll1_sysclk9) - rate * i;
if (min_err  abs(err)) {
min_err = abs(err);
i_min_err = i;
}
}

/* setting the best one to pll1_sysclk9 */
ret = clk_set_rate(pll1_sysclk9, rate * i_min_err);
if (ret)
return ret;

/* setting the best one to clkout2 */
clkout2 = clk_get(NULL, clkout2);
if (IS_ERR(clkout2)) {
printk(KERN_ERR Could not get clkout2\n);
return -ENODEV;
}
clk_enable(clkout2);
clk_set_rate(clkout2,rate);
return 0;
}


 arch/arm/mach-davinci/clock.h |3 +++
 arch/arm/mach-davinci/dm365.c |   41 +
 2 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index a717d98..00c4497 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -50,6 +50,9 @@
 #define PLLDIV_EN   BIT(15)
 #define PLLDIV_RATIO_MASK 0x1f
 
+#define PERI_CLKCTL0x48
+#define CLOCKOUT2EN2
+
 /*
  * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
  * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 42fd4a4..4846b62 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -40,6 +40,38 @@
 #include mux.h
 
 #define DM365_REF_FREQ 2400/* 24 MHz on the DM365 EVM */
+#define DIV1_MASK  0x78/* DIV1 mask in PERI_CLKCTL */
+
+int dm365_clkout2_set_rate(struct clk *clk, unsigned long rate)
+{
+   int i;
+   unsigned long input;
+   unsigned ratio;
+   u32 regval;
+   static void __iomem *system_module_base;
+
+   /* There must be a parent... */
+   if (WARN_ON(!clk-parent))
+   return 0;
+
+   input = clk-parent-rate;
+
+   if (input  rate)
+   ratio = DIV_ROUND_UP(input, rate) - 1;
+
+   system_module_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE, SZ_4K);
+   regval = __raw_readl(system_module_base + PERI_CLKCTL);
+   regval = DIV1_MASK;
+   regval |= ratio  3;
+
+   /* to make changes work stop CLOCKOUT  start it again */
+   regval |= 1  CLOCKOUT2EN;
+   __raw_writel(regval, system_module_base + PERI_CLKCTL);
+   regval = ~(1  CLOCKOUT2EN);
+   __raw_writel(regval, system_module_base + PERI_CLKCTL);
+
+   return 0;
+}
 
 static struct pll_data pll1_data = {
.num= 1,
@@ -124,6 +156,7 @@ static struct clk pll1_sysclk6 = {
.parent = pll1_clk,
.flags  = CLK_PLL,
.div_reg= PLLDIV6,
+   .set_rate   = davinci_set_sysclk_rate,
 };
 
 static struct clk pll1_sysclk7 = {
@@ -145,6 +178,13 @@ static struct clk pll1_sysclk9 = {
.parent = pll1_clk,
.flags  = CLK_PLL,
.div_reg= PLLDIV9,
+   .set_rate   = davinci_set_sysclk_rate,
+};
+
+static struct clk clkout2_clk = {
+   .name   = clkout2,
+   .parent = pll1_sysclk9,
+   .set_rate   = dm365_clkout2_set_rate,
 };
 
 static struct clk pll2_clk = {
@@ -421,6 +461,7 @@ static struct clk_lookup dm365_clks[] = {
CLK(NULL, pll1_sysclk7, pll1_sysclk7),
CLK(NULL, pll1_sysclk8, pll1_sysclk8),
CLK(NULL, pll1_sysclk9, pll1_sysclk9),
+   CLK(NULL, clkout2, clkout2_clk),
CLK(NULL, pll2, pll2_clk),
CLK(NULL, pll2_aux, pll2_aux_clk

[PATCH v2] DaVinci: dm365: Added clockout2 management.

2010-08-02 Thread Raffaele Recalcati

From: Davide Bonfanti davide.bonfa...@bticino.it

Clockout2 is added as a child of pll1_sysclk9, because they have
the same pll divisor.
Added dm365_clkout2_set_rate to properly set clockout2 frequency.
Modified the davinci_set_sysclk_rate function in order
to get the right ancestor.

This patch has been developed against the
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and tested on bmx board.

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 arch/arm/mach-davinci/clock.c  |   32 
 arch/arm/mach-davinci/clock.h  |5 ++
 arch/arm/mach-davinci/dm365.c  |   57 
 arch/arm/mach-davinci/include/mach/dm365.h |1 +
 4 files changed, 87 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index f29a526..6e45808 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -254,7 +254,15 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
u32 v, plldiv;
struct pll_data *pll;
unsigned long rate = clk-rate;
+   struct clk *parent = clk;
 
+   if (clk == NULL || IS_ERR(clk))
+   return -EINVAL;
+   while (parent-parent-parent)
+   parent = parent-parent;
+
+   if (parent == clk)
+   return -EPERM;
/* If this is the PLL base clock, no more calculations needed */
if (clk-pll_data)
return rate;
@@ -262,13 +270,13 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
if (WARN_ON(!clk-parent))
return rate;
 
-   rate = clk-parent-rate;
+   rate = parent-rate;
+
 
/* Otherwise, the parent must be a PLL */
-   if (WARN_ON(!clk-parent-pll_data))
+   if (WARN_ON(!parent-pll_data))
return rate;
-
-   pll = clk-parent-pll_data;
+   pll = parent-pll_data;
 
/* If pre-PLL, source clock is before the multiplier and divider(s) */
if (clk-flags  PRE_PLL)
@@ -293,26 +301,33 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned 
long rate)
struct pll_data *pll;
unsigned long input;
unsigned ratio = 0;
+   struct clk *parent = clk;
+
+   /* searching the right ancestor (pll1_clk or pll2_clk) */
+   while (parent-parent-parent)
+   parent = parent-parent;
+   if (parent == clk)
+   return -EPERM;
 
/* If this is the PLL base clock, wrong function to call */
if (clk-pll_data)
return 0;
 
/* There must be a parent... */
-   if (WARN_ON(!clk-parent))
+   if (WARN_ON(!parent))
return 0;
 
/* ... the parent must be a PLL... */
-   if (WARN_ON(!clk-parent-pll_data))
+   if (WARN_ON(!parent-pll_data))
return 0;
 
/* ... and this clock must have a divider. */
if (WARN_ON(!clk-div_reg))
return 0;
 
-   pll = clk-parent-pll_data;
+   pll = parent-pll_data;
 
-   input = clk-parent-rate;
+   input = parent-rate;
 
/* If pre-PLL, source clock is before the multiplier and divider(s) */
if (clk-flags  PRE_PLL)
@@ -343,6 +358,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long 
rate)
 
return 0;
 }
+EXPORT_SYMBOL(davinci_set_sysclk_rate);
 
 static unsigned long clk_leafclk_recalc(struct clk *clk)
 {
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index a717d98..df36d73 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -50,6 +50,11 @@
 #define PLLDIV_EN   BIT(15)
 #define PLLDIV_RATIO_MASK 0x1f
 
+#define PERI_CLKCTL0x48
+#define CLOCKOUT2EN2
+#define CLOCKOUT1EN1
+#define CLOCKOUT0EN0
+
 /*
  * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
  * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 42fd4a4..902e9a0 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -40,6 +40,11 @@
 #include mux.h
 
 #define DM365_REF_FREQ 2400/* 24 MHz on the DM365 EVM */
+#define PINMUX00x00
+#define PINMUX10x04
+#define PINMUX20x08
+#define PINMUX30x0c
+#define PINMUX40x10
 
 static struct pll_data pll1_data = {
.num= 1,
@@ -124,6 +129,7 @@ static struct clk pll1_sysclk6 = {
.parent = pll1_clk,
.flags  = CLK_PLL,
.div_reg= PLLDIV6,
+   .set_rate   = davinci_set_sysclk_rate,
 };
 
 static struct clk pll1_sysclk7 = {
@@ -145,6 +151,14 @@ static struct clk pll1_sysclk9 = {
.parent = pll1_clk,
.flags

Re: Boot time

2010-07-31 Thread Raffaele Recalcati

You should use qt statically linked. I would like to see the final
boot chart . Bye

2010/7/30, Nicolas Luna luna...@gmail.com:
 Hi,

 Thanks guys for your advices, I applied few of them and I save a lot of
 time, I'm at 3.9 seconds now. I'll also apply the deferred init calls
 concept
 later.

 I have two other questions.

 I'm not sure to understand how to use EDMA to copy from NOR to RAM in uboot.
 Every post that I found it is never explain the procedure to apply this
 patch. Do you guys have a piece of code or something to get started with
 that?

 In the same way, after the kernel boot, I have to start an application with
 QT and it takes 10 seconds to transfert QT lib (libQtCore, libQtGui,
 libQtNetwork, fonts) from NOR to RAM and start the application. QT stuff is
 ~20MB, I removed every useless lib to reduce the amount of data to
 transfert. I also optimised the EMIFA CS2 (I changed EMIFA clock to 150 Mhz
 and changed CS timing to be at the maximum of my NOR). I probed the NOR chip
 select and there are big delays between read access. I suppose that is
 because it is not using EDMA and the CPU is not able to feed the NOR... I
 would like to reduce this transfert time to ~4 secondes or less and I think
 that EDMA could maybe help to do it. Do you have any idea how to apply it,
 or any other ideas?

 Thanks for your time.

 Regards,

 Nicolas


 On Thu, Jul 29, 2010 at 10:42 PM, rohan tabish
 rohan_ja...@yahoo.co.ukwrote:

 set verify=n this will ignore checksum

 Regard's
 RT

 --- On *Thu, 29/7/10, Nicolas Luna luna...@gmail.com* wrote:


 From: Nicolas Luna luna...@gmail.com
 Subject: Boot time
 To: davinci-linux-open-source@linux.davincidsp.com
 Date: Thursday, 29 July, 2010, 0:59


 Hi guys,

 I'm trying to make by board boot as quick as possible. I did some
 optimisation with the All This For 1 Second Boot wiki and other website.
 I
 would like to reduce a little bit more the boot time and I wonder if you
 guys could give me some clues.

 I copied my boot log below. For sure I'll remove the uboot autoboot delay
 and probably build a new kernel with modules. I putted in bold part that I
 think it is possible to do more optimisation.

 1- See bullet #3.
 2- The verifying Checksum is about 400 msec is it possible to skip it?
 3- It takes ~1 sec to start booting the kernel and there is a other ~1 sec
 delay between the starting kernel and the beginning of the uncompressing.
 Why it's so long? Ok maybe there is the copy from NOR to RAM but it should
 not take more than few msec.
 4- It takes ~1 sec to the kernel to free 120K memory... I got enought RAM
 is it possible to remove it?

 I got custom hardware based on OMAP-L138 with FS (jffs2) and compressed
 kernel in NOR Flash.

 Thanks a lot

 Nicolas


 -

 0.000 0.000: OMAP-L138 initialization passed!
 0.000 0.000: Booting TI User Boot Loader
 0.004 0.004:UBL Version: 1.65
 0.004 0.000:UBL Flashtype: NOR
 0.008 0.004: Starting NOR Copy...
 0.008 0.000: CFI Query...passed.
 0.012 0.004: NOR Initialization:
 0.012 0.000:Command Set: Intel
 0.012 0.000:Manufacturer: INTEL
 0.016 0.004:Size: 0x0020 MB
 0.020 0.004: Valid magicnum, 0x55424CBB, found..
 0.184 0.164:DONE
 0.188 0.004: Jumping to entry point at 0xC108.
 0.504 0.316:
 1.548 1.044: Hit any key to stop autoboot:  0
 *2.372 0.824: ## Booting kernel from Legacy Image at c0007fc0 ...*
 2.372 0.000:Image Name:   Linux-2.6.34
 2.380 0.008:Image Type:   ARM Linux Kernel Image (uncompressed)
 2.380 0.000:Data Size:1505956 Bytes =  1.4 MB
 2.384 0.004:Load Address: c0008000
 2.388 0.004:Entry Point:  c0008000
 *2.808 0.420:Verifying Checksum ... OK*
 2.808 0.000:Loading Kernel Image ... OK
 2.808 0.000: OK
 2.808 0.000:
 *2.812 0.004: Starting kernel ...*
 *2.812 0.000:*
 *3.860 1.048: Uncompressing Linux... done, booting the kernel.*
 4.264 0.404: Linux version 2.6.34 (i...@idt-ubuntu-linux) (gcc version 4.3.3
 (Sourcery G++ Lite 2009q1-203) ) #89 PREEMPT Thu Jul 22 15:24:03 EDT 2010
 4.268 0.004: CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
 4.272 0.004: CPU: VIVT data cache, VIVT instruction cache
 4.276 0.004: Machine: DaVinci DA850/OMAP-L138 EVM
 4.280 0.004: Memory policy: ECC disabled, Data cache writeback
 4.284 0.004: DaVinci da850/omap-l138 variant 0x0
 4.288 0.004: Built 1 zonelists in Zone order, mobility grouping on.  Total
 pages: 32512
 4.300 0.012: Kernel command line: lpj=747520 mem=128M
 console=ttyS2,115200n8 root=/dev/mtdblock2 rootfstype=jffs2 rw ip=off
 4.304 0.004: PID hash table entries: 512 (order: -1, 2048 bytes)
 4.308 0.004: Dentry cache hash table entries: 16384 (order: 4, 65536
 bytes)
 4.316 0.008: Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
 4.316 0.000: Memory: 128MB = 128MB total
 4.324 0.008: Memory: 126752k/126752k available, 4320k reserved, 0K highmem
 4.324 0.000: Virtual kernel

Re: Boot time

2010-07-29 Thread Raffaele Recalcati

Hi Nicolas,

2010/7/28 Nicolas Luna luna...@gmail.com

 Hi guys,

 I'm trying to make by board boot as quick as possible. I did some
 optimisation with the All This For 1 Second Boot wiki and other website. I
 would like to reduce a little bit more the boot time and I wonder if you
 guys could give me some clues.

Did you also look at:

http://processors.wiki.ti.com/index.php/Boot_Time_Optimization

http://processors.wiki.ti.com/index.php/Measuring_Boot_Time


 I copied my boot log below. For sure I'll remove the uboot autoboot delay
 and probably build a new kernel with modules. I putted in bold part that I
 think it is possible to do more optimisation.

 1- See bullet #3.
 2- The verifying Checksum is about 400 msec is it possible to skip it?


use:
set verify n

3- It takes ~1 sec to start booting the kernel and there is a other ~1 sec
 delay between the starting kernel and the beginning of the uncompressing.
 Why it's so long? Ok maybe there is the copy from NOR to RAM but it should
 not take more than few msec.


In the links above there was the possibility to use EDMA to copy from NOR to
RAM.
It is also possible to use uncompresses kernel and there is a trade of about
uncompressing kernel and managing a bigger uncompressed kernel image.


 4- It takes ~1 sec to the kernel to free 120K memory... I got enought RAM
 is it possible to remove it?


I don't know.. but interesting.



 I got custom hardware based on OMAP-L138 with FS (jffs2) and compressed
 kernel in NOR Flash.


Have you used JFFS2_SUMMARY ?
UBIFS?
Have you checked cpu frequency?
Have you checked NOR bus timings?


 Thanks a lot

 Nicolas


 -

 0.000 0.000: OMAP-L138 initialization passed!
 0.000 0.000: Booting TI User Boot Loader
 0.004 0.004:UBL Version: 1.65
 0.004 0.000:UBL Flashtype: NOR
 0.008 0.004: Starting NOR Copy...
 0.008 0.000: CFI Query...passed.
 0.012 0.004: NOR Initialization:
 0.012 0.000:Command Set: Intel
 0.012 0.000:Manufacturer: INTEL
 0.016 0.004:Size: 0x0020 MB
 0.020 0.004: Valid magicnum, 0x55424CBB, found..
 0.184 0.164:DONE
 0.188 0.004: Jumping to entry point at 0xC108.


Delete every messages not absolutely critical.
Did you skip from .config every DEBUG,KALLSYMS and similar configs?


 0.504 0.316:
 1.548 1.044: Hit any key to stop autoboot:  0
 *2.372 0.824: ## Booting kernel from Legacy Image at c0007fc0 ...*
 2.372 0.000:Image Name:   Linux-2.6.34
 2.380 0.008:Image Type:   ARM Linux Kernel Image (uncompressed)
 2.380 0.000:Data Size:1505956 Bytes =  1.4 MB
 2.384 0.004:Load Address: c0008000
 2.388 0.004:Entry Point:  c0008000
 *2.808 0.420:Verifying Checksum ... OK*
 2.808 0.000:Loading Kernel Image ... OK
 2.808 0.000: OK
 2.808 0.000:
 *2.812 0.004: Starting kernel ...*
 *2.812 0.000:*
 *3.860 1.048: Uncompressing Linux... done, booting the kernel.*
 4.264 0.404: Linux version 2.6.34 (i...@idt-ubuntu-linux) (gcc version 4.3.3
 (Sourcery G++ Lite 2009q1-203) ) #89 PREEMPT Thu Jul 22 15:24:03 EDT 2010
 4.268 0.004: CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
 4.272 0.004: CPU: VIVT data cache, VIVT instruction cache
 4.276 0.004: Machine: DaVinci DA850/OMAP-L138 EVM
 4.280 0.004: Memory policy: ECC disabled, Data cache writeback
 4.284 0.004: DaVinci da850/omap-l138 variant 0x0
 4.288 0.004: Built 1 zonelists in Zone order, mobility grouping on.  Total
 pages: 32512
 4.300 0.012: Kernel command line: lpj=747520 mem=128M
 console=ttyS2,115200n8 root=/dev/mtdblock2 rootfstype=jffs2 rw ip=off
 4.304 0.004: PID hash table entries: 512 (order: -1, 2048 bytes)
 4.308 0.004: Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
 4.316 0.008: Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
 4.316 0.000: Memory: 128MB = 128MB total
 4.324 0.008: Memory: 126752k/126752k available, 4320k reserved, 0K highmem
 4.324 0.000: Virtual kernel memory layout:
 4.332 0.008: vector  : 0x - 0x1000   (   4 kB)


Put 'quiet' at the end of bootargs


 4.336 0.004: fixmap  : 0xfff0 - 0xfffe   ( 896 kB)
 4.340 0.004: DMA : 0xff00 - 0xffe0   (  14 MB)
 4.344 0.004: vmalloc : 0xc880 - 0xfea0   ( 866 MB)
 4.348 0.004: lowmem  : 0xc000 - 0xc800   ( 128 MB)
 4.352 0.004: modules : 0xbf00 - 0xc000   (  16 MB)
 4.356 0.004:   .init : 0xc0008000 - 0xc0026000   ( 120 kB)
 4.360 0.004:   .text : 0xc0026000 - 0xc02e8000   (2824 kB)
 4.364 0.004:   .data : 0xc02e8000 - 0xc0307a60   ( 127 kB)
 4.372 0.008: SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0,
 CPUs=1, Nodes=1
 4.376 0.004: Hierarchical RCU implementation.
 4.376 0.000: NR_IRQS:245
 4.380 0.004: Console: colour dummy device 80x30
 4.384 0.004: Calibrating delay loop (skipped) preset value.. 149.50
 BogoMIPS (lpj=747520)
 4.388 0.004: Mount-cache hash table entries: 512
 4.392 0.004: CPU: Testing

Re: [PATCH v2] DaVinci: dm365: Added clockout2 management.

2010-07-29 Thread Raffaele Recalcati

Hi Nori,



--- a/arch/arm/mach-davinci/clock.c
 +++ b/arch/arm/mach-davinci/clock.c
 @@ -254,7 +254,15 @@ static unsigned long
  clk_sysclk_recalc(struct clk *clk)
   u32 v, plldiv;
   struct pll_data *pll;
   unsigned long rate = clk-rate;
 + struct clk *parent = clk;

 + if (clk == NULL || IS_ERR(clk))
 + return -EINVAL;
 + while (parent-parent-parent)
 + parent = parent-parent;
 +
 + if (parent == clk)
 + return -EPERM;
 
 
It is not clear to me why this change in needed. It is not
described in the patch description as well. Most likely this
needs to be carved into a separate patch as well describing
what is wrong with the existing clk_sysclk_recalc() routine.
 
 
 
 
  now, whith the last check, we don't need that modifications, but only
 
  /* Otherwise, the parent must be a PLL */
  -   if (WARN_ON(!parent-pll_data))
  +   if (!clk-parent-pll_data)
 
  clkout2 is a sub-divider and so its parent is not a pll.

 This function is meant to recalculate the rate for a sysclk.
 For clkout2, a new recalculate function should be written.


Due to the fact that clkout2 is after the second divider I guess I'll have
to semplify the recalc function.
I'll try.



 [...]

 +int dm365_clkout2_set_rate(unsigned long rate)
 
 
Is clockout2 specific to DM365? DM355/DM6446 manuals mention
clkout signal as well. If this routine can cater to more SoCs
with simple modifications, you can attempt to generalize it.
 
 
 
  we check in dm355 and clkout2 is really a different clock.
  it seems difficult to integrate.
  we'd prefer not to do it.

 Okay.


:)



 [...]

 
 +
 + /* check all possibilities to get best fitting for the
  required freq */
 
 + i_min_err = min_err = INT_MAX;
 + for (i = 0x0F; i  0; i--) {
 + if (clk-parent-set_rate) {
 + ret = clk_set_rate(clk-parent, rate *
  i) ;
 + err = clk_get_rate(clk-parent) - rate *
  i;
 + if (min_err  abs(err)) {
 + min_err = abs(err);
 + i_min_err = i;
 + }
 + }
 + }
 
 
Why should the child touch the parent's clock output? Users of
  the
clock framework should be able to set these rates independently.
 
 
 
  right.
  we tried.
  the problem is that the clkout2 is used for uda1345 system clock.
  without chenig the parent we can't get close.
  the sound is really too fast.
 

 You should be able to change both clocks independently.
 Example, in your board code:

 xxx uda135_set_clk_rate(xxx)
 {
clk_set_rate(sysclkN, desired_rate);
clk_set_rate(clkout2, desired_rate);
 }



Doing like that I should put a logic in that driver.
It is not wrong, because I'm writing a cpu_dai, but, anyway, I will change
the sysclk9 that, maybe, is used from someone else.

Isn't there the possibility to occupy a sysclk?



 That should work?

 
 
 
  Tomorrow, if you agree, I'll send you 2 patches:
  -patch1:  clkout2

 This is fine..

  -patch2:  removing warn from sysclk recalc

 ... but as I wrote above, still don't see a need for this.


Can't I use clk-flags to have a conditional behaviour of clk_sysclk_recalc
if it is called from pll1_sysclk9 or from clkout2 ?

Thx,
Raffaele
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Re: Davinci RTC

2010-07-27 Thread Raffaele Recalcati

2010/7/26 Hank Magnuski ha...@mtinet.com


 In rtv-davinci.c there is this piece of code:

 static inline void davinci_rtcif_wait(struct davinci_rtc *davinci_rtc)
 {
while (davinci_rtcif_read(davinci_rtc, DAVINCI_PRTCIF_CTLR) 
   DAVINCI_PRTCIF_CTLR_BUSY)
cpu_relax();
 }


 If there is any problem with the hardware configuration so that the rtc is
 not receiving clocking, this wait loop will completely hang the kernel.

 Is it normal in the kernel to have wait loops with no exits?

 I would have expected some type of countdown loop with an unconditional
 exit.

 Hank



Hi Hank,
in http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
I don't see this call.

Where do you find it, please?

Raffaele
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Re: [PATCH v2] DaVinci: dm365: Added clockout2 management.

2010-07-26 Thread Raffaele Recalcati

2010/7/22 Nori, Sekhar nsek...@ti.com

 Hi Raffaele,

 On Wed, Jul 21, 2010 at 16:21:49, Raffaele Recalcati wrote:
  From: Davide Bonfanti davide.bonfa...@bticino.it
 
  Clockout2 is added as a child of pll1_sysclk9, because they have
  the same pll divisor.
  Added dm365_clkout2_set_rate to properly set clockout2 frequency.

  Modified the davinci_set_sysclk_rate function in order
  to get the right ancestor.

 This change should be carved into a separate patch since
 it is not directly related to adding clockout2 support.


ok, it will be done



 In the new patch please describe how the existing code isn't
 getting the right ancestor.


now it is not more needed.
there was a mistake in the call.



 Also, that patch should note below the '---' that it depends
 on this patch submitted to the mailing list:

 https://patchwork.kernel.org/patch/112994/

 This helps maintainer derive the correct order in which patches
 need to be applied.


 
  This patch has been developed against the
 
 http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git

 As, mentioned before, this is implied when submitting to
 davinci-linux-open-source@linux.davincidsp.com and so can
 be removed. If you want to note it, please note below the
 '---' in the patch so it wont make it to the commit log.


ok,thx


  git tree and tested on bmx board.
 
  Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
  Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
  ---
   arch/arm/mach-davinci/clock.c  |   32 
   arch/arm/mach-davinci/clock.h  |5 ++
   arch/arm/mach-davinci/dm365.c  |   57
 
   arch/arm/mach-davinci/include/mach/dm365.h |1 +
   4 files changed, 87 insertions(+), 8 deletions(-)
 
  diff --git a/arch/arm/mach-davinci/clock.c
 b/arch/arm/mach-davinci/clock.c
  index f29a526..6e45808 100644
  --- a/arch/arm/mach-davinci/clock.c
  +++ b/arch/arm/mach-davinci/clock.c
  @@ -254,7 +254,15 @@ static unsigned long clk_sysclk_recalc(struct clk
 *clk)
u32 v, plldiv;
struct pll_data *pll;
unsigned long rate = clk-rate;
  + struct clk *parent = clk;
 
  + if (clk == NULL || IS_ERR(clk))
  + return -EINVAL;
  + while (parent-parent-parent)
  + parent = parent-parent;
  +
  + if (parent == clk)
  + return -EPERM;

 It is not clear to me why this change in needed. It is not
 described in the patch description as well. Most likely this
 needs to be carved into a separate patch as well describing
 what is wrong with the existing clk_sysclk_recalc() routine.



now, whith the last check, we don't need that modifications, but only

/* Otherwise, the parent must be a PLL */
-   if (WARN_ON(!parent-pll_data))
+   if (!clk-parent-pll_data)

clkout2 is a sub-divider and so its parent is not a pll.



 [...]

  @@ -293,26 +301,33 @@ int davinci_set_sysclk_rate(struct clk *clk,
 unsigned long rate)
struct pll_data *pll;
unsigned long input;
unsigned ratio = 0;
  + struct clk *parent = clk;
  +
  + /* searching the right ancestor (pll1_clk or pll2_clk) */
  + while (parent-parent-parent)
  + parent = parent-parent;
  + if (parent == clk)
  + return -EPERM;

 As noted above, please carve into separate patch.


ok



 [...]

  diff --git a/arch/arm/mach-davinci/clock.h
 b/arch/arm/mach-davinci/clock.h
  index a717d98..df36d73 100644
  --- a/arch/arm/mach-davinci/clock.h
  +++ b/arch/arm/mach-davinci/clock.h
  @@ -50,6 +50,11 @@
   #define PLLDIV_EN   BIT(15)
   #define PLLDIV_RATIO_MASK 0x1f
 
  +#define PERI_CLKCTL  0x48
  +#define CLOCKOUT2EN  2
  +#define CLOCKOUT1EN  1
  +#define CLOCKOUT0EN  0
  +
   /*
* OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
* cycles to ensure that the PLLC has switched to bypass mode. Delay of
 1us
  diff --git a/arch/arm/mach-davinci/dm365.c
 b/arch/arm/mach-davinci/dm365.c
  index 42fd4a4..902e9a0 100644
  --- a/arch/arm/mach-davinci/dm365.c
  +++ b/arch/arm/mach-davinci/dm365.c
  @@ -40,6 +40,11 @@
   #include mux.h
 
   #define DM365_REF_FREQ   2400/* 24 MHz on the
 DM365 EVM */
  +#define PINMUX0  0x00
  +#define PINMUX1  0x04
  +#define PINMUX2  0x08
  +#define PINMUX3  0x0c
  +#define PINMUX4  0x10

 Why are PINMUX defines added here? You don't seem to use
 these elsewhere in the patch.


deleting ...



 
   static struct pll_data pll1_data = {
.num= 1,
  @@ -124,6 +129,7 @@ static struct clk pll1_sysclk6 = {
.parent = pll1_clk,
.flags  = CLK_PLL,
.div_reg= PLLDIV6,
  + .set_rate   = davinci_set_sysclk_rate,
   };
 
   static struct clk pll1_sysclk7 = {
  @@ -145,6 +151,14 @@ static struct clk pll1_sysclk9

[PATCH 3/3] ASoC: DaVinci: Voicecodec: Added support based on davinci-pcm-copyfromuser

From: Davide Bonfanti davide.bonfa...@bticino.it

The driver uses the pcm implementation without the use of DMA in
order to support Voicecodec (cq93vc).

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 sound/soc/davinci/Makefile  |3 +
 sound/soc/davinci/cq93vc_copy.c |  130 +++
 sound/soc/davinci/cq93vc_copy.h |   26 
 3 files changed, 159 insertions(+), 0 deletions(-)
 create mode 100644 sound/soc/davinci/cq93vc_copy.c
 create mode 100644 sound/soc/davinci/cq93vc_copy.h

diff --git a/sound/soc/davinci/Makefile b/sound/soc/davinci/Makefile
index 7d6a9a1..44c17ad 100644
--- a/sound/soc/davinci/Makefile
+++ b/sound/soc/davinci/Makefile
@@ -1,6 +1,7 @@
 # DAVINCI Platform Support
 snd-soc-davinci-objs := davinci-pcm.o
 snd-soc-davinci-objs += davinci-pcm-copyfromuser.o
+snd-soc-davinci-objs += cq93vc_copy.o
 snd-soc-davinci-i2s-objs := davinci-i2s.o
 snd-soc-davinci-mcasp-objs:= davinci-mcasp.o
 snd-soc-davinci-vcif-objs:= davinci-vcif.o
@@ -13,9 +14,11 @@ obj-$(CONFIG_SND_DAVINCI_SOC_VCIF) += snd-soc-davinci-vcif.o
 # DAVINCI Machine Support
 snd-soc-evm-objs := davinci-evm.o
 snd-soc-sffsdr-objs := davinci-sffsdr.o
+snd-soc-bmx-objs := davinci-bmx.o
 
 obj-$(CONFIG_SND_DAVINCI_SOC_EVM) += snd-soc-evm.o
 obj-$(CONFIG_SND_DM6467_SOC_EVM) += snd-soc-evm.o
 obj-$(CONFIG_SND_DA830_SOC_EVM) += snd-soc-evm.o
 obj-$(CONFIG_SND_DA850_SOC_EVM) += snd-soc-evm.o
 obj-$(CONFIG_SND_DAVINCI_SOC_SFFSDR) += snd-soc-sffsdr.o
+obj-$(CONFIG_SND_DAVINCI_SOC_BMX) += snd-soc-bmx.o
diff --git a/sound/soc/davinci/cq93vc_copy.c b/sound/soc/davinci/cq93vc_copy.c
new file mode 100644
index 000..41747dd
--- /dev/null
+++ b/sound/soc/davinci/cq93vc_copy.c
@@ -0,0 +1,130 @@
+/*
+ *
+ * Copyright (C) 2010 Bticino S.p.a
+ * Author: Davide Bonfanti davide.bonfa...@bticino.it
+ *
+ * Contributors:
+ * Raffaele Recalcati raffaele.recalc...@bticino.it
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/module.h
+#include linux/init.h
+#include linux/platform_device.h
+#include linux/slab.h
+#include linux/kernel.h
+#include linux/hrtimer.h
+#include linux/clk.h
+
+#include sound/core.h
+#include sound/pcm.h
+#include sound/pcm_params.h
+#include sound/soc.h
+
+#include mach/gpio.h
+
+#include davinci-pcm-copy.h
+#include cq93vc_copy.h
+
+#define DAVINCI_VOICECODEC_MODULE_BASE 0x01D0C000
+#define VC_PID  0x00
+#define VC_CTRL 0x04
+#define VC_INTEN0x08
+#define VC_INTSTATUS0x0C
+#define VC_INTCLR   0x10
+#define VC_EMUL_CTRL0x14
+#define RFIFO   0x20
+#define WFIFO   0x24
+#define FIFOSTAT0x28
+#define VC_REG000x80
+#define VC_REG010x84
+#define VC_REG020x88
+#define VC_REG030x8C
+#define VC_REG040x90
+#define VC_REG050x94
+#define VC_REG060x98
+#define VC_REG090xA4
+#define VC_REG100xA8
+#define VC_REG120xB0
+
+/* bit definitions */
+#define VC_CTRL_WFIFOMD BIT(14)
+#define VC_CTRL_WFIFOCL BIT(13)
+#define VC_CTRL_WFIFOEN BIT(12)
+#define VC_CTRL_RFIFOMD BIT(10)
+#define VC_CTRL_RFIFOCL BIT(9)
+#define VC_CTRL_RFIFOEN BIT(8)
+#define VC_CTRL_WDUNSIGNED  BIT(7)
+#define VC_CTRL_WDSIZE  BIT(6)
+#define VC_CTRL_RDUNSIGNED  BIT(5)
+#define VC_CTRL_RDSIZE  BIT(4)
+#define VC_CTRL_RSTDAC  BIT(1)
+#define VC_CTRL_RSTADC  BIT(0)
+
+#define VC_INTSTATUS_WDREQ BIT(3)
+
+#define FIFOSTAT_WDATACOUNT_MASK   0x1F00
+#define FIFOSTAT_WDATACOUNT_OFFSET 8
+
+#define HW_FIFO_SIZE 0x10
+
+void __iomem *voice_codec_base;
+
+void cq93vc_enable(void)
+{
+   __raw_writel(0, voice_codec_base + VC_CTRL);
+   __raw_writel(0, voice_codec_base + VC_INTEN);
+   __raw_writel(VC_CTRL_RFIFOMD | VC_CTRL_WFIFOEN |
+VC_CTRL_WFIFOMD, voice_codec_base + VC_CTRL);
+}
+
+void cq93vc_write(u16 data)
+{
+   __raw_writew(data, voice_codec_base + WFIFO);
+}
+
+void cq93vc_wait_fifo_ready(void)
+{
+   u32 diff;
+   do {
+   diff = __raw_readl(voice_codec_base + VC_INTSTATUS);
+   } while (!(diff  VC_INTSTATUS_WDREQ));
+}
+
+int cq93vc_get_fifo_size(void)
+{
+   return HW_FIFO_SIZE;
+}
+
+int cq93vc_get_fifo_status(void)
+{
+   int fifo;
+   fifo =  __raw_readl(voice_codec_base + FIFOSTAT);
+   fifo = (fifo  FIFOSTAT_WDATACOUNT_MASK)  FIFOSTAT_WDATACOUNT_OFFSET;
+   return fifo;
+}
+
+void cq93vc_init(void)
+{
+   voice_codec_base = ioremap(DAVINCI_VOICECODEC_MODULE_BASE

[PATCH 1/3] ASoC: soc-core: soc_pcm_ops dynamically allocated

From: Davide Bonfanti davide.bonfa...@bticino.it

If soc_pcm_ops is statically allocated, more than one call to soc_new_pcm
cause operations overwrite. The problem is overcome usyng dynamic
allocation.

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 sound/soc/soc-core.c |   38 +-
 1 files changed, 17 insertions(+), 21 deletions(-)

diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index ad7f952..6500686 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -801,17 +801,6 @@ static int soc_pcm_trigger(struct snd_pcm_substream 
*substream, int cmd)
}
return 0;
 }
-
-/* ASoC PCM operations */
-static struct snd_pcm_ops soc_pcm_ops = {
-   .open   = soc_pcm_open,
-   .close  = soc_codec_close,
-   .hw_params  = soc_pcm_hw_params,
-   .hw_free= soc_pcm_hw_free,
-   .prepare= soc_pcm_prepare,
-   .trigger= soc_pcm_trigger,
-};
-
 #ifdef CONFIG_PM
 /* powers down audio subsystem for suspend */
 static int soc_suspend(struct device *dev)
@@ -1306,6 +1295,7 @@ static int soc_new_pcm(struct snd_soc_device *socdev,
struct snd_pcm *pcm;
char new_name[64];
int ret = 0, playback = 0, capture = 0;
+   struct snd_pcm_ops *soc_pcm_ops;
 
rtd = kzalloc(sizeof(struct snd_soc_pcm_runtime), GFP_KERNEL);
if (rtd == NULL)
@@ -1335,19 +1325,25 @@ static int soc_new_pcm(struct snd_soc_device *socdev,
 
dai_link-pcm = pcm;
pcm-private_data = rtd;
-   soc_pcm_ops.mmap = platform-pcm_ops-mmap;
-   soc_pcm_ops.pointer = platform-pcm_ops-pointer;
-   soc_pcm_ops.ioctl = platform-pcm_ops-ioctl;
-   soc_pcm_ops.copy = platform-pcm_ops-copy;
-   soc_pcm_ops.silence = platform-pcm_ops-silence;
-   soc_pcm_ops.ack = platform-pcm_ops-ack;
-   soc_pcm_ops.page = platform-pcm_ops-page;
+   soc_pcm_ops = kmalloc(sizeof(struct snd_pcm_ops), GFP_KERNEL);
+   soc_pcm_ops-open   = soc_pcm_open;
+   soc_pcm_ops-close  = soc_codec_close;
+   soc_pcm_ops-hw_params  = soc_pcm_hw_params;
+   soc_pcm_ops-hw_free= soc_pcm_hw_free;
+   soc_pcm_ops-prepare= soc_pcm_prepare;
+   soc_pcm_ops-trigger= soc_pcm_trigger;
+   soc_pcm_ops-mmap = platform-pcm_ops-mmap;
+   soc_pcm_ops-pointer = platform-pcm_ops-pointer;
+   soc_pcm_ops-ioctl = platform-pcm_ops-ioctl;
+   soc_pcm_ops-copy = platform-pcm_ops-copy;
+   soc_pcm_ops-silence = platform-pcm_ops-silence;
+   soc_pcm_ops-ack = platform-pcm_ops-ack;
+   soc_pcm_ops-page = platform-pcm_ops-page;
 
if (playback)
-   snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, soc_pcm_ops);
-
+   snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, soc_pcm_ops);
if (capture)
-   snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, soc_pcm_ops);
+   snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, soc_pcm_ops);
 
ret = platform-pcm_new(codec-card, codec_dai, pcm);
if (ret  0) {
-- 
1.7.0.4

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[PATCH 2/3] ASoC: DaVinci: Added support based on copy_from_user instead of DMA

From: Davide Bonfanti davide.bonfa...@bticino.it

This driver implements a pcm interface without the use of a DMA but with
a copy_from_user.
There's a buffer in the driver that is filled with davinci_pcm_copy.
When pcm is running, a TIMER interrupt is activated in order to fill
HW FIFO.
BUG: It happens sometimes that the peripheral stops working so there's a
trap.

This patch has been developed against the
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and tested on bmx board.

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 sound/soc/davinci/Makefile   |1 +
 sound/soc/davinci/davinci-pcm-copy.h |   52 +
 sound/soc/davinci/davinci-pcm-copyfromuser.c |  278 ++
 sound/soc/davinci/davinci-pcm.h  |1 +
 4 files changed, 332 insertions(+), 0 deletions(-)
 create mode 100644 sound/soc/davinci/davinci-pcm-copy.h
 create mode 100644 sound/soc/davinci/davinci-pcm-copyfromuser.c

diff --git a/sound/soc/davinci/Makefile b/sound/soc/davinci/Makefile
index a93679d..7d6a9a1 100644
--- a/sound/soc/davinci/Makefile
+++ b/sound/soc/davinci/Makefile
@@ -1,5 +1,6 @@
 # DAVINCI Platform Support
 snd-soc-davinci-objs := davinci-pcm.o
+snd-soc-davinci-objs += davinci-pcm-copyfromuser.o
 snd-soc-davinci-i2s-objs := davinci-i2s.o
 snd-soc-davinci-mcasp-objs:= davinci-mcasp.o
 snd-soc-davinci-vcif-objs:= davinci-vcif.o
diff --git a/sound/soc/davinci/davinci-pcm-copy.h 
b/sound/soc/davinci/davinci-pcm-copy.h
new file mode 100644
index 000..c143fb3
--- /dev/null
+++ b/sound/soc/davinci/davinci-pcm-copy.h
@@ -0,0 +1,52 @@
+/*
+ *
+ * Copyright (C) 2010 Bticino S.p.a
+ * Author: Davide Bonfanti davide.bonfa...@bticino.it
+ *
+ * Contributors:
+ * Raffaele Recalcati raffaele.recalc...@bticino.it
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DAVINCI_PCM_COPY_H
+#define _DAVINCI_PCM_COPY_H
+
+struct davinci_pcm_copy_ops {
+   /* called to perform initial settings - optional */
+   void (*init)(void);
+   /* called to enable codec - mandatory */
+   void (*enable)(void);
+   /* called to push one data into hw_fifo - mandatory */
+   void (*write)(u16);
+   /* called to wait hw_fifo is ready for more data - optional */
+   void (*wait_fifo_ready)(void);
+   /* called to get hw_fifo size - mandatory */
+   int (*get_fifo_size)(void);
+   /* called to get number of samples already into the hw_fifo */
+   int (*get_fifo_status)(void);
+};
+
+struct davinci_pcm_copy_platform_data {
+   /* length required for samples buffer in bytes */
+   int buffer_size;
+   /* minimum time in ps between an interrupt and another */
+   int min_interrupt_interval_ps;
+   /*
+* margin between next interrupt occurrency and hw_fifo end_of_play
+* using loaded samples
+*/
+   int interrupt_margin_ps;
+   /* codec operations as explained above */
+   struct davinci_pcm_copy_ops *ops;
+};
+
+#endif /* _DAVINCI_PCM_COPY_H */
diff --git a/sound/soc/davinci/davinci-pcm-copyfromuser.c 
b/sound/soc/davinci/davinci-pcm-copyfromuser.c
new file mode 100644
index 000..7494afe
--- /dev/null
+++ b/sound/soc/davinci/davinci-pcm-copyfromuser.c
@@ -0,0 +1,278 @@
+/*
+ *
+ * Copyright (C) 2010 Bticino S.p.a
+ * Author: Davide Bonfanti davide.bonfa...@bticino.it
+ *
+ * Contributors:
+ * Raffaele Recalcati raffaele.recalc...@bticino.it
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/module.h
+#include linux/init.h
+#include linux/platform_device.h
+#include linux/slab.h
+#include linux/kernel.h
+#include linux/hrtimer.h
+#include linux/clk.h
+
+#include sound/core.h
+#include sound/pcm.h
+#include sound/pcm_params.h
+#include sound/soc.h
+
+#include mach/gpio.h
+
+#include davinci-pcm.h
+#include davinci-pcm-copy.h
+
+#define DEF_BUF_SIZE   2048
+#define DEF_MIN_INT50
+#define DEF_INT_MARGIN 50
+
+int pointer_sub;
+int hw_fifo_size;
+u16 *local_buffer;
+static struct hrtimer

Re: [PATCH 1/3] ASoC: soc-core: soc_pcm_ops dynamically allocated

2010/7/16 Mark Brown broo...@opensource.wolfsonmicro.com

 On Fri, Jul 16, 2010 at 04:46:57PM +0200, Raffaele Recalcati wrote:

  If soc_pcm_ops is statically allocated, more than one call to
 soc_new_pcm
  cause operations overwrite. The problem is overcome usyng dynamic
  allocation.

 As I said previously you're looking for Liam's multi-component work
 here rather than this (or at least should be basing your work off his).


ok.
For us it is better to have also more feedback from you about the other two
patches.
So the next patchset we'll submit shall be more complete.

Thx
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[PATCH] DaVinci: dm365: Added clockout2 management.

2010-07-15 Thread Raffaele Recalcati

From: Davide Bonfanti davide.bonfa...@bticino.it

Clockout2 is added as a child of pll1_sysclk9, because they have
the same pll divisor.
Added dm365_clkout2_set_rate to properly set clockout2 frequency.
Modified the davinci_set_sysclk_rate function in order
to get the right ancestor.

This patch has been developed against the
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and tested on bmx board.

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 arch/arm/mach-davinci/clock.c  |   32 
 arch/arm/mach-davinci/clock.h  |5 ++
 arch/arm/mach-davinci/dm365.c  |   57 
 arch/arm/mach-davinci/include/mach/dm365.h |1 +
 4 files changed, 87 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index f29a526..6e45808 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -254,7 +254,15 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
u32 v, plldiv;
struct pll_data *pll;
unsigned long rate = clk-rate;
+   struct clk *parent = clk;
 
+   if (clk == NULL || IS_ERR(clk))
+   return -EINVAL;
+   while (parent-parent-parent)
+   parent = parent-parent;
+
+   if (parent == clk)
+   return -EPERM;
/* If this is the PLL base clock, no more calculations needed */
if (clk-pll_data)
return rate;
@@ -262,13 +270,13 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
if (WARN_ON(!clk-parent))
return rate;
 
-   rate = clk-parent-rate;
+   rate = parent-rate;
+
 
/* Otherwise, the parent must be a PLL */
-   if (WARN_ON(!clk-parent-pll_data))
+   if (WARN_ON(!parent-pll_data))
return rate;
-
-   pll = clk-parent-pll_data;
+   pll = parent-pll_data;
 
/* If pre-PLL, source clock is before the multiplier and divider(s) */
if (clk-flags  PRE_PLL)
@@ -293,26 +301,33 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned 
long rate)
struct pll_data *pll;
unsigned long input;
unsigned ratio = 0;
+   struct clk *parent = clk;
+
+   /* searching the right ancestor (pll1_clk or pll2_clk) */
+   while (parent-parent-parent)
+   parent = parent-parent;
+   if (parent == clk)
+   return -EPERM;
 
/* If this is the PLL base clock, wrong function to call */
if (clk-pll_data)
return 0;
 
/* There must be a parent... */
-   if (WARN_ON(!clk-parent))
+   if (WARN_ON(!parent))
return 0;
 
/* ... the parent must be a PLL... */
-   if (WARN_ON(!clk-parent-pll_data))
+   if (WARN_ON(!parent-pll_data))
return 0;
 
/* ... and this clock must have a divider. */
if (WARN_ON(!clk-div_reg))
return 0;
 
-   pll = clk-parent-pll_data;
+   pll = parent-pll_data;
 
-   input = clk-parent-rate;
+   input = parent-rate;
 
/* If pre-PLL, source clock is before the multiplier and divider(s) */
if (clk-flags  PRE_PLL)
@@ -343,6 +358,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long 
rate)
 
return 0;
 }
+EXPORT_SYMBOL(davinci_set_sysclk_rate);
 
 static unsigned long clk_leafclk_recalc(struct clk *clk)
 {
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index a717d98..df36d73 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -50,6 +50,11 @@
 #define PLLDIV_EN   BIT(15)
 #define PLLDIV_RATIO_MASK 0x1f
 
+#define PERI_CLKCTL0x48
+#define CLOCKOUT2EN2
+#define CLOCKOUT1EN1
+#define CLOCKOUT0EN0
+
 /*
  * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
  * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 42fd4a4..56a425f 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -40,6 +40,11 @@
 #include mux.h
 
 #define DM365_REF_FREQ 2400/* 24 MHz on the DM365 EVM */
+#define PINMUX00x00
+#define PINMUX10x04
+#define PINMUX20x08
+#define PINMUX30x0c
+#define PINMUX40x10
 
 static struct pll_data pll1_data = {
.num= 1,
@@ -124,6 +129,7 @@ static struct clk pll1_sysclk6 = {
.parent = pll1_clk,
.flags  = CLK_PLL,
.div_reg= PLLDIV6,
+   .set_rate   = davinci_set_sysclk_rate,
 };
 
 static struct clk pll1_sysclk7 = {
@@ -147,6 +153,14 @@ static struct clk pll1_sysclk9 = {
.div_reg= PLLDIV9,
 };
 
+static

Re: [PATCH] DaVinci: dm365: Added clockout2 management and set_sysclk_rate

2010-07-15 Thread Raffaele Recalcati

Please not consider this patch.
I have to re-check it.
I'm sorry for the mistake.

2010/7/14 Raffaele Recalcati lamiapost...@gmail.com

 From: Davide Bonfanti davide.bonfa...@bticino.it

Added also possibility to set sysclk frequency.

Added possibility to set clockout2 frequency.
Clockout2 is a child of pll1_sysclk9, because they have
the same pll divisor.

This patch has been developed against the

 http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and tested on bmx board.

 Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
 Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
 ---
  arch/arm/mach-davinci/clock.c  |  113
 +++-
  arch/arm/mach-davinci/clock.h  |   14 
  arch/arm/mach-davinci/dm365.c  |   23 +-
  arch/arm/mach-davinci/include/mach/clock.h |3 +
  4 files changed, 146 insertions(+), 7 deletions(-)

 diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
 index 054c303..464c289 100644
 --- a/arch/arm/mach-davinci/clock.c
 +++ b/arch/arm/mach-davinci/clock.c
 @@ -144,6 +144,69 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
  }
  EXPORT_SYMBOL(clk_set_rate);

 +int clkout2_set_rate(struct clk *clk, unsigned long rate)
 +{
 +   unsigned long flags;
 +   int ret = -EINVAL;
 +   int i, err, min_err, i_min_err;
 +   u32 regval;
 +   struct pll_data *pll;
 +   struct clk *parent = clk;
 +
 +   if (clk == NULL || IS_ERR(clk))
 +   return ret;
 +   if (!cpu_is_davinci_dm365())
 +   return -ENODEV;
 +
 +   while (parent-parent-parent)
 +   parent = parent-parent;
 +
 +   parent = clk-parent;
 +
 +   if (parent == clk)
 +   return -EPERM;
 +
 +   pll = parent-pll_data;
 +   regval = __raw_readl(IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE +
 +   PERI_CLKCTL));
 +
 +   i_min_err = min_err = INT_MAX;
 +   for (i = 0x0F; i  0; i--) {
 +   if (clk-set_rate) {
 +   ret = clk_set_rate(clk, rate * i) ;
 +   err = clk_get_rate(clk) - rate * i;
 +   if (abs(min_err)  abs(err)) {
 +   min_err = err;
 +   i_min_err = i;
 +   }
 +   }
 +   }
 +   i = i_min_err;
 +   ret = clk-set_rate(clk, rate * i) ;
 +
 +   regval = ~(0x0F  3);
 +   regval |= (i-1)  3;
 +   regval |= 1  CLOCKOUT2EN;
 +   __raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE +
 +   PERI_CLKCTL));
 +   rate *= i;
 +
 +   spin_lock_irqsave(clockfw_lock, flags);
 +   if (ret == 0) {
 +   if (clk-recalc)
 +   clk-rate = clk-recalc(clk);
 +   propagate_rate(clk);
 +   regval = ~(1  CLOCKOUT2EN);
 +   __raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE
 +
 +   PERI_CLKCTL));
 +   } else
 +   return -EINVAL;
 +   spin_unlock_irqrestore(clockfw_lock, flags);
 +
 +   return ret;
 +}
 +EXPORT_SYMBOL(clkout2_set_rate);
 +
  int clk_set_parent(struct clk *clk, struct clk *parent)
  {
unsigned long flags;
 @@ -254,7 +317,15 @@ static unsigned long clk_sysclk_recalc(struct clk
 *clk)
u32 v, plldiv;
struct pll_data *pll;
unsigned long rate = clk-rate;
 +   struct clk *parent = clk;
 +
 +   if (clk == NULL || IS_ERR(clk))
 +   return -EINVAL;
 +   while (parent-parent-parent)
 +   parent = parent-parent;

 +   if (parent == clk)
 +   return -EPERM;
/* If this is the PLL base clock, no more calculations needed */
if (clk-pll_data)
return rate;
 @@ -262,13 +333,13 @@ static unsigned long clk_sysclk_recalc(struct clk
 *clk)
if (WARN_ON(!clk-parent))
return rate;

 -   rate = clk-parent-rate;
 +   rate = parent-rate;
 +

/* Otherwise, the parent must be a PLL */
 -   if (WARN_ON(!clk-parent-pll_data))
 +   if (WARN_ON(!parent-pll_data))
return rate;
 -
 -   pll = clk-parent-pll_data;
 +   pll = parent-pll_data;

/* If pre-PLL, source clock is before the multiplier and divider(s)
 */
if (clk-flags  PRE_PLL)
 @@ -286,6 +357,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)

return rate;
  }
 +EXPORT_SYMBOL(clk_sysclk_recalc);

  static unsigned long clk_leafclk_recalc(struct clk *clk)
  {
 @@ -433,6 +505,39 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned
 int prediv,
  }
  EXPORT_SYMBOL(davinci_set_pllrate);

 +int set_sysclk_rate(struct clk *clk, unsigned long rate)
 +{
 +   u32 clk_freq_min, clk_freq_max, plldiv;
 +   struct pll_data *pll;
 +   struct clk *parent = clk;
 +
 +   while (parent

Re: Lauterbach and DM365

2010/7/5 Diego Dompe diego.do...@ridgerun.com

 Hi,

 Yes, you can attach the lauterbach to a DM365. I think is even on the list
 of processors supported on recent versions.

 Diego


 On Jun 28, 2010, at 7:16 AM, Kieran Bingham wrote:

  Hi Guys,
 
  Has anyone used a lauterbach to connect the DM365?
 
  I can't find documentation anywhere on what settings to use...



it works perfectly.
Ask to Lauterbach, they will help you!



 
  --
  Regards
  Kieran
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[PATCH 3/3] ASoC: DaVinci: Added fast clock timing for McBSP (I2S)

From: Raffaele Recalcati raffaele.recalc...@bticino.it

i2s_fast_clock switch can be used to have a better approximate
frequency.
The waveform will be not symmetric.

This patch has been developed against the
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm, but using
uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 arch/arm/mach-davinci/include/mach/asp.h |7 +++
 sound/soc/davinci/davinci-i2s.c  |   24 +++-
 2 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h 
b/arch/arm/mach-davinci/include/mach/asp.h
index 314570d..2d8f8af 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -63,6 +63,13 @@ struct snd_platform_data {
unsigned sram_size_playback;
unsigned sram_size_capture;
 
+   /*
+* This define works when both clock and FS are output for the cpu
+* and makes clock very fast (FS is not symmetrical, but sampling
+* frequency is better approximated
+*/
+   bool i2s_fast_clock;
+
/* To be used when cpu gets clock from external pin */
int clk_input_pin;
 
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index e478be9..0af5bae 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -150,6 +150,7 @@ struct davinci_mcbsp_dev {
 */
unsigned enable_channel_combine:1;
 
+   bool i2s_fast_clock;
unsigned int fmt;
int clk_div;
int clk_input_pin;
@@ -443,11 +444,23 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
   DAVINCI_MCBSP_SRGR_CLKSM;
srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
8 - 1);
-   /* symmetric waveforms */
-   clk_div = freq / (mcbsp_word_length * 16) /
- params-rate_num * params-rate_den;
-   srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
-   16 - 1);
+   if (dev-i2s_fast_clock) {
+   clk_div = 256;
+   do {
+   framesize = (freq / (--clk_div)) /
+   params-rate_num *
+   params-rate_den;
+   } while (((framesize  33) || (framesize  4095)) 
+(clk_div));
+   clk_div--;
+   srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
+   } else {
+   /* symmetric waveforms */
+   clk_div = freq / (mcbsp_word_length * 16) /
+ params-rate_num * params-rate_den;
+   srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
+   16 - 1);
+   }
clk_div = 0xFF;
srgr |= clk_div;
break;
@@ -643,6 +656,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
pdata-sram_size_playback;
dev-dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
pdata-sram_size_capture;
+   dev-i2s_fast_clock = pdata-i2s_fast_clock;
dev-clk_input_pin = pdata-clk_input_pin;
}
dev-clk = clk_get(pdev-dev, NULL);
-- 
1.7.0.4

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[PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S)

From: Raffaele Recalcati raffaele.recalc...@bticino.it

Added two clocking options for dm365 McBSP peripheral when used
with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu generates
clock and frame sync) and SND_SOC_DAIFMT_CBS_CFM (the cpu gets clock
from external pin and generates frame sync).
A slave clock management can be important when the external codec needs
the system clock and the bit clock synchronized (tested with uda1345).
This patch has been developed against the:
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm, but using
uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 sound/soc/davinci/davinci-i2s.c |   92 +++
 1 files changed, 83 insertions(+), 9 deletions(-)

diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index adadcd3..319e8ca 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -68,16 +68,21 @@
 #define DAVINCI_MCBSP_RCR_RDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_RCR_RFIG (1  18)
 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_RCR_RFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_RCR_RPHASE   (1  31)
 
 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)   ((v)  5)
 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)   ((v)  8)
 #define DAVINCI_MCBSP_XCR_XDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_XCR_XFIG (1  18)
 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_XCR_XFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_XCR_XPHASE   (1  31)
 
 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v)  8)
 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v)  16)
 #define DAVINCI_MCBSP_SRGR_FSGM(1  28)
+#define DAVINCI_MCBSP_SRGR_CLKSM   (1  29)
 
 #define DAVINCI_MCBSP_PCR_CLKRP(1  0)
 #define DAVINCI_MCBSP_PCR_CLKXP(1  1)
@@ -144,6 +149,9 @@ struct davinci_mcbsp_dev {
 * won't end up being swapped because of the underrun.
 */
unsigned enable_channel_combine:1;
+
+   unsigned int fmt;
+   int clk_div;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -254,10 +262,12 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
struct davinci_mcbsp_dev *dev = cpu_dai-private_data;
unsigned int pcr;
unsigned int srgr;
+   /* Attention srgr is updated by hw_params! */
srgr = DAVINCI_MCBSP_SRGR_FSGM |
DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
 
+   dev-fmt = fmt;
/* set master/slave audio interface */
switch (fmt  SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
@@ -372,6 +382,16 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
return 0;
 }
 
+static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
+   int div_id, int div)
+{
+   struct davinci_mcbsp_dev *dev = cpu_dai-private_data;
+   int srgr;
+
+   dev-clk_div = div;
+   return 0;
+}
+
 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 struct snd_pcm_hw_params *params,
 struct snd_soc_dai *dai)
@@ -380,8 +400,8 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
struct davinci_pcm_dma_params *dma_params =
dev-dma_params[substream-stream];
struct snd_interval *i = NULL;
-   int mcbsp_word_length;
-   unsigned int rcr, xcr, srgr;
+   int mcbsp_word_length, master;
+   unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
u32 spcr;
snd_pcm_format_t fmt;
unsigned element_cnt = 1;
@@ -396,12 +416,44 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
}
 
-   i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
-   srgr = DAVINCI_MCBSP_SRGR_FSGM;
-   srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
+   master = dev-fmt  SND_SOC_DAIFMT_MASTER_MASK;
+   fmt = params_format(params);
+   mcbsp_word_length = asp_word_length[fmt];
 
-   i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
-   srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
+   switch (master) {
+   case SND_SOC_DAIFMT_CBS_CFS:
+   freq = clk_get_rate(dev-clk);
+   srgr = DAVINCI_MCBSP_SRGR_FSGM |
+  DAVINCI_MCBSP_SRGR_CLKSM;
+   srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length

[PATCH 2/3] ASoC: DaVinci: Added selection of clk input pin for McBSP

From: Raffaele Recalcati raffaele.recalc...@bticino.it

When McBSP peripheral gets the clock from an external pin,
there are three possible chooses, MCBSP_CLKX, MCBSP_CLKR
and MCBSP_CLKS.
evm-dm365 uses MCBSP_CLKR, instead in bmx board I have a different
hardware connection and I use MCBSP_CLKS, so I have added
this possibility.

This patch has been developed against the:
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm)

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 arch/arm/mach-davinci/include/mach/asp.h |8 
 sound/soc/davinci/davinci-i2s.c  |   28 +++-
 2 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h 
b/arch/arm/mach-davinci/include/mach/asp.h
index 834725f..314570d 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -63,6 +63,9 @@ struct snd_platform_data {
unsigned sram_size_playback;
unsigned sram_size_capture;
 
+   /* To be used when cpu gets clock from external pin */
+   int clk_input_pin;
+
/* McASP specific fields */
int tdm_slots;
u8 op_mode;
@@ -78,6 +81,11 @@ enum {
MCASP_VERSION_2,/* DA8xx/OMAPL1x */
 };
 
+enum {
+   MCBSP_CLKR = 0, /* DM365 */
+   MCBSP_CLKS,
+};
+
 #define INACTIVE_MODE  0
 #define TX_MODE1
 #define RX_MODE2
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index 319e8ca..e478be9 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -152,6 +152,7 @@ struct davinci_mcbsp_dev {
 
unsigned int fmt;
int clk_div;
+   int clk_input_pin;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -278,11 +279,26 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
DAVINCI_MCBSP_PCR_CLKRM;
break;
case SND_SOC_DAIFMT_CBM_CFS:
-   /* McBSP CLKR pin is the input for the Sample Rate Generator.
-* McBSP FSR and FSX are driven by the Sample Rate Generator. */
-   pcr = DAVINCI_MCBSP_PCR_SCLKME |
-   DAVINCI_MCBSP_PCR_FSXM |
-   DAVINCI_MCBSP_PCR_FSRM;
+   pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
+   /*
+* Selection of the clock input pin that is the
+* input for the Sample Rate Generator.
+* McBSP FSR and FSX are driven by the Sample Rate
+* Generator.
+*/
+   switch (dev-clk_input_pin) {
+   case MCBSP_CLKS:
+   pcr |= DAVINCI_MCBSP_PCR_CLKXM |
+   DAVINCI_MCBSP_PCR_CLKRM;
+   break;
+   case MCBSP_CLKR:
+   pcr |= DAVINCI_MCBSP_PCR_SCLKME;
+   break;
+   default:
+   printk(KERN_ERR %s:bad clk_input_pin\n, __func__);
+   return -EINVAL;
+   }
+
break;
case SND_SOC_DAIFMT_CBM_CFM:
/* codec is master */
@@ -436,6 +452,7 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
srgr |= clk_div;
break;
case SND_SOC_DAIFMT_CBM_CFS:
+   /* Clock given on CLKS */
srgr = DAVINCI_MCBSP_SRGR_FSGM;
clk_div = dev-clk_div - 1;
srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
@@ -626,6 +643,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
pdata-sram_size_playback;
dev-dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
pdata-sram_size_capture;
+   dev-clk_input_pin = pdata-clk_input_pin;
}
dev-clk = clk_get(pdev-dev, NULL);
if (IS_ERR(dev-clk)) {
-- 
1.7.0.4

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Rif: Re: [PATCH] spi: davinci: Added support for chip select using gpio

2010-07-06 Thread raffaele . recalcati


-glik...@secretlab.ca ha scritto: -

Per: Raffaele Recalcati lamiapost...@gmail.com, Brian Niebuhr
bniebu...@gmail.com
Da: Grant Likely grant.lik...@secretlab.ca
Inviato da: glik...@secretlab.ca
Data: 01/07/2010 01.03
Cc: davinci-linux-open-sou...@linux.davincidsp.com, Raffaele
Recalcati raffaele.recalc...@bticino.it, Davide Bonfanti
davide.bonfa...@bticino.it, Russell King li...@arm.linux.org.uk,
Sandeep Paulraj s-paul...@ti.com, Cyril Chemparathy cy...@ti.com,
Miguel Aguilar miguel.agui...@ridgerun.com, Thomas Koeller
thomas.koel...@baslerweb.com, David Brownell
dbrown...@users.sourceforge.net, Philby John pj...@in.mvista.com,
Sudhakar Rajashekhara sudhakar@ti.com,
linux-arm-ker...@lists.infradead.org, linux-ker...@vger.kernel.org,
spi-devel-gene...@lists.sourceforge.net
Oggetto: Re: [PATCH] spi: davinci: Added support for chip select
using gpio

On Mon, Jun 28, 2010 at 12:47 AM, Raffaele Recalcati
lamiapost...@gmail.com wrote:
 From: Raffaele Recalcati raffaele.recalc...@bticino.it

It is not everytime possible, due to hardware constraints,
to use the hw chip select available on spi port.
So I add this possibility using a gpio as chip select.
If controller_data variable is not null it is
the gpio to be used as chip select.
The default case is compatible with evmdm365.
This patch has been developed against the

http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.
git
git tree and has been tested on bmx board (similar to dm365 evm
but with
gpio as spi chip select).

 Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
 Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it

The davinci SPI driver is getting completely replaced (as soon as I
receive the respun patches), and I assume this patch will no longer
apply after the fact, so I'm not going to pick this patch up.  You
should coordinate with Brian Niebuhr to get this feature into his new
driver.

I'm not very lucky with davinci-linux-open-source patching.
Thank you for the information.
The patch is really simple and so it will be not a real problem to up port
it.

I'd like anyway a timing roadmap, because,
if now the best kernel choose for dm365 is surely
http://arago-project.org/git/projects/linux-davinci.git
because of dvsdk (video codec) compatibility,
it is possible that next year 2.6.36 will be stable and compatible to dvsdk
(video codec).
The kernel of dm365 (that is a video processor) has to be compatible to its
video codec.
How to manage the transition?


Cheers,
g.

 ---
  arch/arm/mach-davinci/dm365.c |   10 ++
  drivers/spi/davinci_spi.c |   27 ++-
  2 files changed, 24 insertions(+), 13 deletions(-)

 diff --git a/arch/arm/mach-davinci/dm365.c
b/arch/arm/mach-davinci/dm365.c
 index a146849..42fd4a4 100644
 --- a/arch/arm/mach-davinci/dm365.c
 +++ b/arch/arm/mach-davinci/dm365.c
 @@ -677,10 +677,12 @@ void __init dm365_init_spi0(unsigned
chipselect_mask,
davinci_cfg_reg(DM365_SPI0_SDO);

/* not all slaves will be wired up */
 -   if (chipselect_mask  BIT(0))
 -   davinci_cfg_reg(DM365_SPI0_SDENA0);
 -   if (chipselect_mask  BIT(1))
 -   davinci_cfg_reg(DM365_SPI0_SDENA1);
 +   if  (!((unsigned long) info-controller_data)) {
 +   if (chipselect_mask  BIT(0))
 +   davinci_cfg_reg(DM365_SPI0_SDENA0);
 +   if (chipselect_mask  BIT(1))
 +   davinci_cfg_reg(DM365_SPI0_SDENA1);
 +   }

spi_register_board_info(info, len);

 diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
 index 95afb6b..621ae46 100644
 --- a/drivers/spi/davinci_spi.c
 +++ b/drivers/spi/davinci_spi.c
 @@ -29,6 +29,7 @@
  #include linux/spi/spi_bitbang.h
  #include linux/slab.h

 +#include mach/gpio.h
  #include mach/spi.h
  #include mach/edma.h

 @@ -270,18 +271,26 @@ static void davinci_spi_chipselect(struct
spi_device *spi, int value)
pdata = davinci_spi-pdata;

/*
 -* Board specific chip select logic decides the polarity
and cs
 -* line for the controller
 -*/
 +   * Board specific chip select logic decides the polarity and
cs
 +   * line for the controller
 +   */
if (value == BITBANG_CS_INACTIVE) {
 -   set_io_bits(davinci_spi-base + SPIDEF,
CS_DEFAULT);
 -
 -   data1_reg_val |= CS_DEFAULT  SPIDAT1_CSNR_SHIFT;
 -   iowrite32(data1_reg_val, davinci_spi-base +
SPIDAT1);
 -
 +   if  ((unsigned long) spi-controller_data) {
 +   gpio_set_value(spi-controller_data, \
 +   !(spi-mode  SPI_CS_HIGH));
 +   } else {
 +   set_io_bits(davinci_spi-base + SPIDEF,
CS_DEFAULT);
 +
 +   data1_reg_val |= CS_DEFAULT 
SPIDAT1_CSNR_SHIFT;
 +   iowrite32(data1_reg_val, davinci_spi-base
+ SPIDAT1

Rif: Re: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S)

2010-07-06 Thread raffaele . recalcati

-Mark Brown broo...@opensource.wolfsonmicro.com ha scritto: -
Per: Raffaele Recalcati lamiapost...@gmail.com
Da: Mark Brown broo...@opensource.wolfsonmicro.com
Data: 04/07/2010 11.15
Cc: davinci-linux-open-sou...@linux.davincidsp.com, Raffaele
Recalcati raffaele.recalc...@bticino.it, Davide Bonfanti
davide.bonfa...@bticino.it, ...@slimlogic.co.uk
Oggetto: Re: [PATCH 1/3] ASoC: DaVinci: Added two clocking
possibilities to McBSP (I2S)

On Fri, Jul 02, 2010 at 07:12:25PM +0200, Raffaele Recalcati wrote:
 From: Raffaele Recalcati raffaele.recalc...@bticino.it

 Added two clocking options for dm365 McBSP peripheral when used
 with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu
generates

You've not sent any of these patches to the ALSA list or to Liam
Girdwood, the other ASoC maintainer.  In general you should be
looking
to include at least the subsystem maintainers and mailing list for
the
relevant code, anyone who actively works on the driver and possibly
an
architecture-specific list.

ok, but, first I was using scripts/get_maintainer.pl, but it created a too
long cc list.
 thinking 
anyway, if get_mantainer is not right, it is better to fix it, instead of
guessing who to send the patches to.

So I'll use this -cc list from the script.

scripts/get_maintainer.pl -f sound/soc/davinci/davinci-i2s.c
Liam Girdwood l...@slimlogic.co.uk
Mark Brown broo...@opensource.wolfsonmicro.com
Jaroslav Kysela pe...@perex.cz
Takashi Iwai ti...@suse.de
Troy Kisky troy.ki...@boundarydevices.com
Raffaele Recalcati raffaele.recalc...@bticino.it
Davide Bonfanti davide.bonfa...@bticino.it
alsa-de...@alsa-project.org
linux-ker...@vger.kernel.org

The first two patches look OK, though I'd like to see some DaVinci
people confirming they're OK.

I hope they answer.


Raffaele Recalcati
Driver Linux BSP
Bticino S.p.A.
Via L.Manara
 4, Erba (CO), Italy
Tel:  +39.(0)31.653.252
Tel2:
+39.(0)31.653.652
Fax: +39.(0)31.653.283
E-mail: raffaele.recalc...@bticino.it
Web:
 www.bticino.it
Bticino
Legrand
Zucchini
Cablofil
Ortronics


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[PATCH] ASoC: DaVinci: More accurate calculation for clock divider for McBSP (I2S)

From: Raffaele Recalcati raffaele.recalc...@bticino.it

i2s_accurate_sck switch can be used to have a better approximate
sampling frequency.
The trade off is between more accurate clock (fast clock)
and less accurate clock (slow clock).
The waveform will be not symmetric.
Probably it is possible to get a better algorithm for calculating
the divider, trying to keep a slower clock as possible.

This patch has been developed against the
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm, but using
uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 arch/arm/mach-davinci/include/mach/asp.h |   33 ++
 sound/soc/davinci/davinci-i2s.c  |   28 -
 2 files changed, 55 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h 
b/arch/arm/mach-davinci/include/mach/asp.h
index 0847d21..5149abe 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -73,6 +73,39 @@ struct snd_platform_data {
 */
int clk_input_pin;
 
+   /*
+* This flag works when both clock and FS are outputs for the cpu
+* and makes clock more accurate (FS is not symmetrical and the
+* clock is very fast.
+* The clock becoming faster is named
+* i2s continuous serial clocl (I2S_SCK) and it is an externally
+* visible bit clock.
+*
+* first line : WordSelect
+* second line : ContinuousSerialClock
+* third line: SerialData
+*
+* SYMMETRICAL APPROACH:
+*   ___  LEFT
+* _| RIGHT |__|
+* _   _ _   _   _   _ _   _
+*   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
+* _   _ _   _   _   _ _   _
+*   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
+*\_/ \_/   \_/ \_/ \_/ \_/   \_/ \_/
+*
+* ACCURATE CLOCK APPROACH:
+*   __  LEFT
+* _| RIGHT|___|
+* _ _   _ _   _   _   _   _   _
+*   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
+* _ _   _  _  dummy cycles
+*   _/ \_ ... _/ \_/ \_  ... _/ \__
+*\_/   \_/ \_/\_/
+*
+*/
+   bool i2s_accurate_sck;
+
/* McASP specific fields */
int tdm_slots;
u8 op_mode;
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index 17f594f..e6dcd81 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -122,6 +122,7 @@ static const unsigned char 
double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
 };
 
 struct davinci_mcbsp_dev {
+   struct device *dev;
struct davinci_pcm_dma_params   dma_params[2];
void __iomem*base;
 #define MOD_DSP_A  0
@@ -154,6 +155,7 @@ struct davinci_mcbsp_dev {
unsigned int fmt;
int clk_div;
int clk_input_pin;
+   bool i2s_accurate_sck;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -296,7 +298,7 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
pcr |= DAVINCI_MCBSP_PCR_SCLKME;
break;
default:
-   dev_err(pdev-dev, bad clk_input_pin\n);
+   dev_err(dev-dev, bad clk_input_pin\n);
return -EINVAL;
}
 
@@ -447,11 +449,23 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
   DAVINCI_MCBSP_SRGR_CLKSM;
srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
8 - 1);
-   /* symmetric waveforms */
-   clk_div = freq / (mcbsp_word_length * 16) /
- params-rate_num * params-rate_den;
-   srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
-   16 - 1);
+   if (dev-i2s_accurate_sck) {
+   clk_div = 256;
+   do {
+   framesize = (freq / (--clk_div)) /
+   params-rate_num *
+   params-rate_den;
+   } while (((framesize  33) || (framesize  4095)) 
+(clk_div));
+   clk_div--;
+   srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
+   } else

Rif: Re: [PATCH 3/3] ASoC: DaVinci: More accurate calculation for clock divider for McBSP (I2S)

2010-07-06 Thread raffaele . recalcati


-Troy Kisky troy.ki...@boundarydevices.com ha scritto: -

Per: Raffaele Recalcati lamiapost...@gmail.com
Da: Troy Kisky troy.ki...@boundarydevices.com
Data: 02/07/2010 22.57
Cc: davinci-linux-open-sou...@linux.davincidsp.com, Mark Brown
broo...@opensource.wolfsonmicro.com, Raffaele Recalcati
raffaele.recalc...@bticino.it
Oggetto: Re: [PATCH 3/3] ASoC: DaVinci: More accurate calculation for
clock divider for McBSP (I2S)

Raffaele Recalcati wrote:
 @@ -447,6 +448,24 @@ static int davinci_i2s_hw_params(struct
snd_pcm_substream *substream,

8 - 1);
 +if (dev-i2s_accurate_clock) {
 +clk_div = 256;
 +do {
 +
framesize = (freq / (--clk_div)) /
 +params-rate_num *
 +params-
rate_den;
 +
} while (((framesize  33) || (framesize  4095))

 + (clk_div));
 +clk_div--;
 +srgr |= DAVINCI_MCBSP_SRGR_FPER
(framesize - 1);
 +} else {
 +/* symmetric waveforms */
 +
clk_div = freq / (mcbsp_word_length * 16) /
 +  params-
rate_num * params-rate_den;
 +srgr |= DAVINCI_MCBSP_SRGR_FPER
(mcbsp_word_length *
 +
16 - 1);
 +}
 +
  /* symmetric waveforms */
  clk_div = freq / (mcbsp_word_length * 16) /
    params-rate_num * params-
rate_den;

Can you test to see if this works to replace all the above ?

unsigned cycles;
framesize = mcbsp_word_length * 16;
cycles = (freq / params-rate_num) * params-
rate_den;
 clk_div = cycles / framesize;

if (dev-i2s_accurate_clock) {
framesize = cycles / clk_div;
if (framesize  4096))
framesize = 4096;
}
srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);

yes, it works.
Now I'm trying to understand the differences:

your solution with i2s_accurate_clock enabled:
davinci-asp davinci-asp.0: framesize = 32
davinci-asp davinci-asp.0: clk_div = 86

your solution with i2s_accurate_clock NOT enabled:

davinci-asp davinci-asp.0: framesize = 32

davinci-asp davinci-asp.0: clk_div = 86

the same.



my solution with i2s_accurate_clock enabled:

davinci-asp davinci-asp.0: my framesize = 33
davinci-asp
davinci-asp.0: clk_div = 82

here the continuous serial clock is faster

my solution with i2s_accurate_clock NOT enabled
davinci-asp davinci-asp.0: my framesize = 32
davinci-asp davinci-asp.0: clk_div = 86

here the continuous
serial clock is the same as yours.


it seems better my and Davide solution.



Raffaele Recalcati
Driver Linux BSP
Bticino S.p.A.
Via
 L.Manara 4, Erba (CO), Italy
Tel:  +39.(0)31.653.252
Tel2:
+39.(0)31.653.652
Fax: +39.(0)31.653.283
E-mail:
raffaele.recalc...@bticino.it

Web:
www.bticino.it

Bticino
Legrand
Zucchini
Cablofil
Ortronics











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[PATCH 2/3] ASoC: DaVinci: Added selection of clk input pin for McBSP

From: Raffaele Recalcati raffaele.recalc...@bticino.it

When McBSP peripheral gets the clock from an external pin,
there are three possible chooses, MCBSP_CLKX, MCBSP_CLKR
and MCBSP_CLKS.
evm-dm365 uses MCBSP_CLKR, instead in bmx board I have a different
hardware connection and I use MCBSP_CLKS, so I have added
this possibility.

This patch has been developed against the:
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm)

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 arch/arm/mach-davinci/include/mach/asp.h |   15 +++
 sound/soc/davinci/davinci-i2s.c  |   29 -
 2 files changed, 39 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h 
b/arch/arm/mach-davinci/include/mach/asp.h
index 834725f..0847d21 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -63,6 +63,16 @@ struct snd_platform_data {
unsigned sram_size_playback;
unsigned sram_size_capture;
 
+   /*
+* If McBSP peripheral gets the clock from an external pin,
+* there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
+* and MCBSP_CLKS.
+* Depending on different hardware connections it is possible
+* to use this setting to change the behaviour of McBSP
+* driver. The dm365_clk_input_pin enum is available for dm365
+*/
+   int clk_input_pin;
+
/* McASP specific fields */
int tdm_slots;
u8 op_mode;
@@ -78,6 +88,11 @@ enum {
MCASP_VERSION_2,/* DA8xx/OMAPL1x */
 };
 
+enum dm365_clk_input_pin {
+   MCBSP_CLKR = 0, /* DM365 */
+   MCBSP_CLKS,
+};
+
 #define INACTIVE_MODE  0
 #define TX_MODE1
 #define RX_MODE2
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index c8f038c..ba5644b 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -122,6 +122,7 @@ static const unsigned char 
double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
 };
 
 struct davinci_mcbsp_dev {
+   struct device *dev;
struct davinci_pcm_dma_params   dma_params[2];
void __iomem*base;
 #define MOD_DSP_A  0
@@ -153,6 +154,7 @@ struct davinci_mcbsp_dev {
 
unsigned int fmt;
int clk_div;
+   int clk_input_pin;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -279,11 +281,26 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
DAVINCI_MCBSP_PCR_CLKRM;
break;
case SND_SOC_DAIFMT_CBM_CFS:
-   /* McBSP CLKR pin is the input for the Sample Rate Generator.
-* McBSP FSR and FSX are driven by the Sample Rate Generator. */
-   pcr = DAVINCI_MCBSP_PCR_SCLKME |
-   DAVINCI_MCBSP_PCR_FSXM |
-   DAVINCI_MCBSP_PCR_FSRM;
+   pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
+   /*
+* Selection of the clock input pin that is the
+* input for the Sample Rate Generator.
+* McBSP FSR and FSX are driven by the Sample Rate
+* Generator.
+*/
+   switch (dev-clk_input_pin) {
+   case MCBSP_CLKS:
+   pcr |= DAVINCI_MCBSP_PCR_CLKXM |
+   DAVINCI_MCBSP_PCR_CLKRM;
+   break;
+   case MCBSP_CLKR:
+   pcr |= DAVINCI_MCBSP_PCR_SCLKME;
+   break;
+   default:
+   dev_err(dev-dev, bad clk_input_pin\n);
+   return -EINVAL;
+   }
+
break;
case SND_SOC_DAIFMT_CBM_CFM:
/* codec is master */
@@ -644,6 +661,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
pdata-sram_size_playback;
dev-dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
pdata-sram_size_capture;
+   dev-clk_input_pin = pdata-clk_input_pin;
}
dev-clk = clk_get(pdev-dev, NULL);
if (IS_ERR(dev-clk)) {
@@ -676,6 +694,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
goto err_free_mem;
}
dev-dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res-start;
+   dev-dev = pdev-dev;
 
davinci_i2s_dai.private_data = dev;
davinci_i2s_dai.capture.dma_data = dev-dma_params;
-- 
1.7.0.4

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[PATCH 3/3] ASoC: DaVinci: More accurate continuous serial clock for McBSP (I2S)

From: Raffaele Recalcati raffaele.recalc...@bticino.it

i2s_accurate_sck switch can be used to have a better approximate
sampling frequency.
The clock is an externally visible bit clock and it is named
i2s continuous serial clock (I2S_SCK).
The trade off is between more accurate clock (fast clock)
and less accurate clock (slow clock).
The waveform will be not symmetric.
Probably it is possible to get a better algorithm for calculating
the divider, trying to keep a slower clock as possible.

This patch has been developed against the
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm, but using
uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 arch/arm/mach-davinci/include/mach/asp.h |   33 ++
 sound/soc/davinci/davinci-i2s.c  |   24 +
 2 files changed, 52 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h 
b/arch/arm/mach-davinci/include/mach/asp.h
index 0847d21..b12c69e 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -73,6 +73,39 @@ struct snd_platform_data {
 */
int clk_input_pin;
 
+   /*
+* This flag works when both clock and FS are outputs for the cpu
+* and makes clock more accurate (FS is not symmetrical and the
+* clock is very fast.
+* The clock becoming faster is named
+* i2s continuous serial clock (I2S_SCK) and it is an externally
+* visible bit clock.
+*
+* first line : WordSelect
+* second line : ContinuousSerialClock
+* third line: SerialData
+*
+* SYMMETRICAL APPROACH:
+*   ___  LEFT
+* _| RIGHT |__|
+* _   _ _   _   _   _ _   _
+*   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
+* _   _ _   _   _   _ _   _
+*   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
+*\_/ \_/   \_/ \_/ \_/ \_/   \_/ \_/
+*
+* ACCURATE CLOCK APPROACH:
+*   __  LEFT
+* _| RIGHT|___|
+* _ _   _ _   _   _   _   _   _
+*   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
+* _ _   _  _  dummy cycles
+*   _/ \_ ... _/ \_/ \_  ... _/ \__
+*\_/   \_/ \_/\_/
+*
+*/
+   bool i2s_accurate_sck;
+
/* McASP specific fields */
int tdm_slots;
u8 op_mode;
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index ba5644b..b251bc9 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -155,6 +155,7 @@ struct davinci_mcbsp_dev {
unsigned int fmt;
int clk_div;
int clk_input_pin;
+   bool i2s_accurate_sck;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -447,11 +448,23 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
   DAVINCI_MCBSP_SRGR_CLKSM;
srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
8 - 1);
-   /* symmetric waveforms */
-   clk_div = freq / (mcbsp_word_length * 16) /
- params-rate_num * params-rate_den;
-   srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
-   16 - 1);
+   if (dev-i2s_accurate_sck) {
+   clk_div = 256;
+   do {
+   framesize = (freq / (--clk_div)) /
+   params-rate_num *
+   params-rate_den;
+   } while (((framesize  33) || (framesize  4095)) 
+(clk_div));
+   clk_div--;
+   srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
+   } else {
+   /* symmetric waveforms */
+   clk_div = freq / (mcbsp_word_length * 16) /
+ params-rate_num * params-rate_den;
+   srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
+   16 - 1);
+   }
clk_div = 0xFF;
srgr |= clk_div;
break;
@@ -662,6 +675,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
dev-dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size

[PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S)

From: Raffaele Recalcati raffaele.recalc...@bticino.it

Added two clocking options for dm365 McBSP peripheral when used
with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu generates
clock and frame sync) and SND_SOC_DAIFMT_CBS_CFM (the cpu gets clock
from external pin and generates frame sync).
A slave clock management can be important when the external codec needs
the system clock and the bit clock synchronized (tested with uda1345).
This patch has been developed against the:
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm, but using
uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 sound/soc/davinci/davinci-i2s.c |  110 +++---
 sound/soc/davinci/davinci-i2s.h |5 ++
 2 files changed, 106 insertions(+), 9 deletions(-)

diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index adadcd3..c8f038c 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -26,6 +26,7 @@
 #include mach/asp.h
 
 #include davinci-pcm.h
+#include davinci-i2s.h
 
 
 /*
@@ -68,16 +69,21 @@
 #define DAVINCI_MCBSP_RCR_RDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_RCR_RFIG (1  18)
 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_RCR_RFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_RCR_RPHASE   BIT(31)
 
 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)   ((v)  5)
 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)   ((v)  8)
 #define DAVINCI_MCBSP_XCR_XDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_XCR_XFIG (1  18)
 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_XCR_XFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_XCR_XPHASE   BIT(31)
 
 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v)  8)
 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v)  16)
 #define DAVINCI_MCBSP_SRGR_FSGM(1  28)
+#define DAVINCI_MCBSP_SRGR_CLKSM   BIT(29)
 
 #define DAVINCI_MCBSP_PCR_CLKRP(1  0)
 #define DAVINCI_MCBSP_PCR_CLKXP(1  1)
@@ -144,6 +150,9 @@ struct davinci_mcbsp_dev {
 * won't end up being swapped because of the underrun.
 */
unsigned enable_channel_combine:1;
+
+   unsigned int fmt;
+   int clk_div;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -254,10 +263,12 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
struct davinci_mcbsp_dev *dev = cpu_dai-private_data;
unsigned int pcr;
unsigned int srgr;
+   /* Attention srgr is updated by hw_params! */
srgr = DAVINCI_MCBSP_SRGR_FSGM |
DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
 
+   dev-fmt = fmt;
/* set master/slave audio interface */
switch (fmt  SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
@@ -372,6 +383,18 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
return 0;
 }
 
+static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
+   int div_id, int div)
+{
+   struct davinci_mcbsp_dev *dev = cpu_dai-private_data;
+
+   if (div_id != DAVINCI_MCBSP_CLKGDV)
+   return -ENODEV;
+
+   dev-clk_div = div;
+   return 0;
+}
+
 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 struct snd_pcm_hw_params *params,
 struct snd_soc_dai *dai)
@@ -380,8 +403,8 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
struct davinci_pcm_dma_params *dma_params =
dev-dma_params[substream-stream];
struct snd_interval *i = NULL;
-   int mcbsp_word_length;
-   unsigned int rcr, xcr, srgr;
+   int mcbsp_word_length, master;
+   unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
u32 spcr;
snd_pcm_format_t fmt;
unsigned element_cnt = 1;
@@ -396,12 +419,47 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
}
 
-   i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
-   srgr = DAVINCI_MCBSP_SRGR_FSGM;
-   srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
+   master = dev-fmt  SND_SOC_DAIFMT_MASTER_MASK;
+   fmt = params_format(params);
+   mcbsp_word_length = asp_word_length[fmt];
 
-   i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
-   srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
+   switch (master) {
+   case SND_SOC_DAIFMT_CBS_CFS:
+   freq = clk_get_rate(dev-clk

Re: Question on RAMDISK

2010-07-05 Thread Raffaele Recalcati

2010/7/5 rohan tabish rohan_ja...@yahoo.co.uk

 Hello everyone

 I am using a ramdisk image to boot the system its takes around 7secs to
 copy the ramdisk image from the flash to the RAM and then takes 3.6 seconds
 after kernal uncompressing to the linux prompt

 I want to know that how to reduce this time of 7seconds.



you can use, if not already done,  cp.l and not cp.b and divide the lenght
to copy by 4.




 Also can anyone tell how to update the ramdisk image from the linux
 prompt.e.g if i have created a file and now iwant it at the next boot then
 how to make this file part of the old ramdisk image

 Regard's
 RT


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[PATCH 2/3] ASoC: DaVinci: Added selection of clk input pin for McBSP

From: Raffaele Recalcati raffaele.recalc...@bticino.it

When McBSP peripheral gets the clock from an external pin,
there are three possible chooses, MCBSP_CLKX, MCBSP_CLKR
and MCBSP_CLKS.
evm-dm365 uses MCBSP_CLKR, instead in bmx board I have a different
hardware connection and I use MCBSP_CLKS, so I have added
this possibility.

This patch has been developed against the:
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm)

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 arch/arm/mach-davinci/include/mach/asp.h |   15 +++
 sound/soc/davinci/davinci-i2s.c  |   27 ++-
 2 files changed, 37 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h 
b/arch/arm/mach-davinci/include/mach/asp.h
index 834725f..0847d21 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -63,6 +63,16 @@ struct snd_platform_data {
unsigned sram_size_playback;
unsigned sram_size_capture;
 
+   /*
+* If McBSP peripheral gets the clock from an external pin,
+* there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
+* and MCBSP_CLKS.
+* Depending on different hardware connections it is possible
+* to use this setting to change the behaviour of McBSP
+* driver. The dm365_clk_input_pin enum is available for dm365
+*/
+   int clk_input_pin;
+
/* McASP specific fields */
int tdm_slots;
u8 op_mode;
@@ -78,6 +88,11 @@ enum {
MCASP_VERSION_2,/* DA8xx/OMAPL1x */
 };
 
+enum dm365_clk_input_pin {
+   MCBSP_CLKR = 0, /* DM365 */
+   MCBSP_CLKS,
+};
+
 #define INACTIVE_MODE  0
 #define TX_MODE1
 #define RX_MODE2
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index a893538..17f594f 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -153,6 +153,7 @@ struct davinci_mcbsp_dev {
 
unsigned int fmt;
int clk_div;
+   int clk_input_pin;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -279,11 +280,26 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
DAVINCI_MCBSP_PCR_CLKRM;
break;
case SND_SOC_DAIFMT_CBM_CFS:
-   /* McBSP CLKR pin is the input for the Sample Rate Generator.
-* McBSP FSR and FSX are driven by the Sample Rate Generator. */
-   pcr = DAVINCI_MCBSP_PCR_SCLKME |
-   DAVINCI_MCBSP_PCR_FSXM |
-   DAVINCI_MCBSP_PCR_FSRM;
+   pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
+   /*
+* Selection of the clock input pin that is the
+* input for the Sample Rate Generator.
+* McBSP FSR and FSX are driven by the Sample Rate
+* Generator.
+*/
+   switch (dev-clk_input_pin) {
+   case MCBSP_CLKS:
+   pcr |= DAVINCI_MCBSP_PCR_CLKXM |
+   DAVINCI_MCBSP_PCR_CLKRM;
+   break;
+   case MCBSP_CLKR:
+   pcr |= DAVINCI_MCBSP_PCR_SCLKME;
+   break;
+   default:
+   dev_err(pdev-dev, bad clk_input_pin\n);
+   return -EINVAL;
+   }
+
break;
case SND_SOC_DAIFMT_CBM_CFM:
/* codec is master */
@@ -645,6 +661,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
pdata-sram_size_playback;
dev-dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
pdata-sram_size_capture;
+   dev-clk_input_pin = pdata-clk_input_pin;
}
dev-clk = clk_get(pdev-dev, NULL);
if (IS_ERR(dev-clk)) {
-- 
1.7.0.4

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[no subject]

The actual DaVinci tree McBSP driver, used for i2S interface, supports
clk and frame sync only if generated externally (see for instance evm-dm365).
This patch series add two new clocking possibilities and also it allows
to select the clock input pin.
It is also possible, with the last patch, to better approximate the frequency,
accepting a non symmetric waveform.

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[PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S)

From: Raffaele Recalcati raffaele.recalc...@bticino.it

Added two clocking options for dm365 McBSP peripheral when used
with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu generates
clock and frame sync) and SND_SOC_DAIFMT_CBS_CFM (the cpu gets clock
from external pin and generates frame sync).
A slave clock management can be important when the external codec needs
the system clock and the bit clock synchronized (tested with uda1345).
This patch has been developed against the:
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm, but using
uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 sound/soc/davinci/davinci-i2s.c |  111 +++---
 sound/soc/davinci/davinci-i2s.h |5 ++
 2 files changed, 107 insertions(+), 9 deletions(-)

diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index adadcd3..a893538 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -26,6 +26,7 @@
 #include mach/asp.h
 
 #include davinci-pcm.h
+#include davinci-i2s.h
 
 
 /*
@@ -68,16 +69,21 @@
 #define DAVINCI_MCBSP_RCR_RDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_RCR_RFIG (1  18)
 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_RCR_RFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_RCR_RPHASE   (1  31)
 
 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)   ((v)  5)
 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)   ((v)  8)
 #define DAVINCI_MCBSP_XCR_XDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_XCR_XFIG (1  18)
 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_XCR_XFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_XCR_XPHASE   (1  31)
 
 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v)  8)
 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v)  16)
 #define DAVINCI_MCBSP_SRGR_FSGM(1  28)
+#define DAVINCI_MCBSP_SRGR_CLKSM   (1  29)
 
 #define DAVINCI_MCBSP_PCR_CLKRP(1  0)
 #define DAVINCI_MCBSP_PCR_CLKXP(1  1)
@@ -144,6 +150,9 @@ struct davinci_mcbsp_dev {
 * won't end up being swapped because of the underrun.
 */
unsigned enable_channel_combine:1;
+
+   unsigned int fmt;
+   int clk_div;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -254,10 +263,12 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
struct davinci_mcbsp_dev *dev = cpu_dai-private_data;
unsigned int pcr;
unsigned int srgr;
+   /* Attention srgr is updated by hw_params! */
srgr = DAVINCI_MCBSP_SRGR_FSGM |
DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
 
+   dev-fmt = fmt;
/* set master/slave audio interface */
switch (fmt  SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
@@ -372,6 +383,19 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
return 0;
 }
 
+static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
+   int div_id, int div)
+{
+   struct davinci_mcbsp_dev *dev = cpu_dai-private_data;
+   int srgr;
+
+   if (div_id != DAVINCI_MCBSP_CLKGDV)
+   return -ENODEV;
+
+   dev-clk_div = div;
+   return 0;
+}
+
 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 struct snd_pcm_hw_params *params,
 struct snd_soc_dai *dai)
@@ -380,8 +404,8 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
struct davinci_pcm_dma_params *dma_params =
dev-dma_params[substream-stream];
struct snd_interval *i = NULL;
-   int mcbsp_word_length;
-   unsigned int rcr, xcr, srgr;
+   int mcbsp_word_length, master;
+   unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
u32 spcr;
snd_pcm_format_t fmt;
unsigned element_cnt = 1;
@@ -396,12 +420,47 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
}
 
-   i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
-   srgr = DAVINCI_MCBSP_SRGR_FSGM;
-   srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
+   master = dev-fmt  SND_SOC_DAIFMT_MASTER_MASK;
+   fmt = params_format(params);
+   mcbsp_word_length = asp_word_length[fmt];
 
-   i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
-   srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
+   switch (master) {
+   case SND_SOC_DAIFMT_CBS_CFS:
+   freq

[PATCH 3/3] ASoC: DaVinci: More accurate calculation for clock divider for McBSP (I2S)

From: Raffaele Recalcati raffaele.recalc...@bticino.it

i2s_accurate_clock switch can be used to have a better approximate
frequency.
The trade off is between more accurate clock (fast clock)
and less accurate clock (slow clock).
The waveform will be not symmetric.
Probably it is possible to get a better algorithm for calculating
the divider, trying to keep a slower clock as possible.

This patch has been developed against the
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm, but using
uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 arch/arm/mach-davinci/include/mach/asp.h |7 +++
 sound/soc/davinci/davinci-i2s.c  |   20 
 2 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h 
b/arch/arm/mach-davinci/include/mach/asp.h
index 0847d21..21c886e 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -73,6 +73,13 @@ struct snd_platform_data {
 */
int clk_input_pin;
 
+   /*
+* This define works when both clock and FS are output for the cpu
+* and makes clock more accurate (FS is not symmetrical and the
+* clock is very fast.
+*/
+   bool i2s_accurate_clock;
+
/* McASP specific fields */
int tdm_slots;
u8 op_mode;
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index 17f594f..2fb1209 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -154,6 +154,7 @@ struct davinci_mcbsp_dev {
unsigned int fmt;
int clk_div;
int clk_input_pin;
+   bool i2s_accurate_clock;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -447,6 +448,24 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
   DAVINCI_MCBSP_SRGR_CLKSM;
srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
8 - 1);
+   if (dev-i2s_accurate_clock) {
+   clk_div = 256;
+   do {
+   framesize = (freq / (--clk_div)) /
+   params-rate_num *
+   params-rate_den;
+   } while (((framesize  33) || (framesize  4095)) 
+(clk_div));
+   clk_div--;
+   srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
+   } else {
+   /* symmetric waveforms */
+   clk_div = freq / (mcbsp_word_length * 16) /
+ params-rate_num * params-rate_den;
+   srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
+   16 - 1);
+   }
+
/* symmetric waveforms */
clk_div = freq / (mcbsp_word_length * 16) /
  params-rate_num * params-rate_den;
@@ -662,6 +681,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
dev-dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
pdata-sram_size_capture;
dev-clk_input_pin = pdata-clk_input_pin;
+   dev-i2s_accurate_clock = pdata-i2s_accurate_clock;
}
dev-clk = clk_get(pdev-dev, NULL);
if (IS_ERR(dev-clk)) {
-- 
1.7.0.4

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Re: [PATCH] ASoC: DaVinci: Added support for cpu clocking I2S

2010-06-30 Thread Raffaele Recalcati

 The freq problem is describe here below, but it is not clear to me:

 From *TMS320DM36x DMSoC Multichannel Buffered Serial Port User's Guide
 (Rev. A) http://www.ti.com/litv/pdf/sprufi3a*
 2.5.3 Data Clock Generation
 When the receive/transmit clock mode is set to 1 (CLK(R/X)M = 1 in the pin
 control register (PCR)), the
 data clocks (CLK(R/X)) are driven by the internal sample rate generator
 output clock, CLKG. You can
 select for the receiver and transmitter from a variety of data bit clocks
 including:
 • The input clock to the sample rate generator, which can be either the
 internal clock source or a
 dedicated external clock source via the MCBSP_CLKX, MCBSP_CLKR, or
 MCBSP_CLKS pins. The
 McBSP internal clock is the CPU/6 clock. See Section 2.5.3.1 for details on
 the source of the McBSP
 internal clock.
 • The input clock source (internal clock source or external clock
 MCBSP_CLKX/MCBSP_CLKR/MCBSP_CLKS) to the sample rate generator can be
 divided-down by a
 programmable value (CLKGDV bit in the sample rate generator register
 (SRGR)) to drive CLKG.
 Regardless of the source to the sample rate generator, the rising edge of
 CLKSRG (see Figure 5)
 generates CLKG and FSG.

 CPU/6 is not clear.



Reading better the documentation the point seems now clear.
We have pllc1 sysclk4 that is the clock of McBSP peripheral.
And so it was abviously this frequency to be used when McBSP has to generate
the clock.
Sorry..

Raffaele
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Re: [PATCH] ASoC: DaVinci: Added support for cpu clocking I2S

2010-06-30 Thread Raffaele Recalcati

2010/6/28 Mark Brown broo...@opensource.wolfsonmicro.com

 On Mon, Jun 28, 2010 at 08:44:46AM +0200, Raffaele Recalcati wrote:
  From: Raffaele Recalcati raffaele.recalc...@bticino.it

 It's still very hard to understand what this patch is supposed to do.
 As previously mentioned this would probably be a lot clearer if you
 split this into multiple patches, for example one adding support for the
 fast clock mode, one adding support for selecting the pin used for any
 external clock and then further patches with any other changes.


Looking at other paches, they are simpler than mine.
I'll try to split it, hoping to obtain the final result.



 I strongly suggest looking at the commit messages for other patches in
 the kernel and trying to follow a similar style.

  Added audio playback support with [frame sync master - clock master]
 mode
  and with [frame sync master - clock slave].

 What are these modes - which clock are you talking about?


McBSP i2s interface to external codec.



 i2s_fast_clock switch can be used to have better approximate or
 symmetric waveforms.

 Why would someone choose not to use this?


I was not sure if symmetric waveform can be a must.
In general I think it is better a non symmetric, but better approximate,
waveform.
Anyway, it is better to have the possibility to choose in my opinion,
because I have not so much experience in i2s communication.



 clk_input_pin board info can be used to select it depending on hw
 connections

  3. We haven't changed the evmdm365 support (due also to CPLD that
 doesn't
  help to understand)
  We don't know in this mode if audio stereo works on evmdm365.
  Probably it does.

 This is what makes me unsure if you're trying to add new modes or not -
 if you're adding new modes then I'd expect that existing boards would be
 unaffected with any changes to use the new feature being easily
 seperable.


Some tests are needed, but it requires time.
I'll try try to make some tests on evmdm365, but I'm not sure to have time
to do it.


  + /*
  +  * This define works when both clock and FS are output for the cpu
  +  * and makes clock very fast (FS is not simmetrical, but sampling

 symmetrical.


thx



  +  * frequency is better approximated
  +  */
  + int i2s_fast_clock;

 Is this a bool?


yes, I'll change it.



  + /* To be used when cpu gets clock from extenal pin */
  + int clk_input_pin;
  +

 How would one use this?


looking at 2.5 Clock, Frames, and Data in
you can select MCBSP_CLKS or other input clock pins.

From board file you can select the possibilites:
static struct snd_platform_data dm365_bmx_snd_data[] = {
{
},
{
.i2s_fast_clock = 0,
.clk_input_pin = MCBSP_CLKS,
},
};

If not set, it works as evm works, that is the default mode.


case SND_SOC_DAIFMT_CBM_CFS:
  - /* McBSP CLKR pin is the input for the Sample Rate
 Generator.
  -  * McBSP FSR and FSX are driven by the Sample Rate
 Generator. */
  - pcr = DAVINCI_MCBSP_PCR_SCLKME |
  - DAVINCI_MCBSP_PCR_FSXM |
  - DAVINCI_MCBSP_PCR_FSRM;
  + pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
  + if (dev-clk_input_pin == MCBSP_CLKS)
  + pcr |= DAVINCI_MCBSP_PCR_CLKXM |
  + DAVINCI_MCBSP_PCR_CLKRM;
  + else
  + /*
  +  * McBSP CLKR pin is the input for the Sample Rate
  +  * Generator.
  +  * McBSP FSR and FSX are driven by the Sample Rate
  +  * Generator.
  +  */
  + pcr |= DAVINCI_MCBSP_PCR_SCLKME;

 This looks like you need a switch statement for the clock selection.



ok.



  +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
  + int div_id, int div)
  +{
  + struct davinci_mcbsp_dev *dev = cpu_dai-private_data;
  + int srgr;
  +
  + dev-clk_div = div;
  + return 0;
  +}
  +

 I would add a clock ID here in case someone wants to configure another
 clock in the patch.


Can you explain better,
please?



  + if (master == SND_SOC_DAIFMT_CBS_CFS) {

 Use a switch staetment for this too.

  + clk = clk_get(NULL, pll1_sysclk6);

 You're doing a clk_get() every time you go through here but never
 freeing it - it would seem better to just do the clk_get() at startup.


Thx for this.
I think it could create problems, right?
I can do it in the probe, I think, similarly to other drivers.


 I'd also expect this to be doing a clk_get() using the struct device for
 the DAI so that the driver can function even if the clock tree for a new..
 SoC is different.


Sorry, I don't understand, can you explain me

Re: [PATCH] ASoC: DaVinci: Added support for cpu clocking I2S

2010-06-30 Thread Raffaele Recalcati

2010/6/28 Troy Kisky troy.ki...@boundarydevices.com

 Raffaele Recalcati wrote:
  + if (dev-i2s_fast_clock) {
  + clk_div = 256;
 can you have
   f = (freq / params-rate_num) * params-rate_den;
  + do {
  + framesize = (freq / (--clk_div)) /
  + params-rate_num *
  + params-rate_den;
 and
framesize = f / (--clk_div);
  + } while (((framesize  33) || (framesize  4095))
 
  +  (clk_div));
  + clk_div--;
 looks like clk_div can go negative here, should the above while say
 (clk_div  1)


 + } while (((framesize  33) || (framesize  4095)) 
 +  (clk_div));

only if clk_div not null stay inside the while.

 + clk_div--;

and here can at minumum be 0, not negative.



  + srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
  + } else {
  + /* symmetric waveforms */
  + clk_div = freq / (mcbsp_word_length * 16) /
  +   params-rate_num * params-rate_den;
  + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
  + 16 - 1);
  + }
  + clk_div = 0xFF;
  + srgr |= clk_div;



so, dividing for (CLKGDV + 1) it is ok.

Raffaele
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[PATCH] ASoC: DaVinci: Added support for cpu clocking I2S

From: Raffaele Recalcati raffaele.recalc...@bticino.it

Added audio playback support with [frame sync master - clock master] mode
and with [frame sync master - clock slave].

1. SND_SOC_DAIFMT_CBS_CFS (the cpu generates clock and frame sync)
   I need to clarify how the McBSP is clocked internally.
   Reading sprufi3a-1.pdf (TMS320DM36x DMSoC Multichannel Buffered Serial
   Port (McBSP) Interface) at 2.5.3 Data Clock Generation paragraph this
   info not appears really clear if we are in the case of McBSP internal
   input clock.
   I hope some Ti developers can help me.
   There is a FIXME message in the patch.

   i2s_fast_clock switch can be used to have better approximate or
   symmetric waveforms.
   clk_input_pin board info can be used to select it depending on hw
   connections

2. SND_SOC_DAIFMT_CBS_CFM (the cpu get clock from external pin
   and generates frame sync)
   Clock slave can be important when the external codec need system clock
   and bit clock synchronized (tested with uda1345).

3. We haven't changed the evmdm365 support (due also to CPLD that doesn't
help to understand)
We don't know in this mode if audio stereo works on evmdm365.
Probably it does.

This patch has been developed against the

http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm, but 
using
uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 arch/arm/mach-davinci/include/mach/asp.h |   16 
 sound/soc/davinci/davinci-i2s.c  |  126 ++
 2 files changed, 128 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h 
b/arch/arm/mach-davinci/include/mach/asp.h
index 834725f..f9b6da2 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -63,6 +63,16 @@ struct snd_platform_data {
unsigned sram_size_playback;
unsigned sram_size_capture;
 
+   /*
+* This define works when both clock and FS are output for the cpu
+* and makes clock very fast (FS is not simmetrical, but sampling
+* frequency is better approximated
+*/
+   int i2s_fast_clock;
+
+   /* To be used when cpu gets clock from extenal pin */
+   int clk_input_pin;
+
/* McASP specific fields */
int tdm_slots;
u8 op_mode;
@@ -78,6 +88,12 @@ enum {
MCASP_VERSION_2,/* DA8xx/OMAPL1x */
 };
 
+enum {
+   MCBSP_CLKR = 0, /* DM365 */
+   MCBSP_CLKS,
+};
+
+
 #define INACTIVE_MODE  0
 #define TX_MODE1
 #define RX_MODE2
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index adadcd3..786ade6 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -68,16 +68,21 @@
 #define DAVINCI_MCBSP_RCR_RDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_RCR_RFIG (1  18)
 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_RCR_RFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_RCR_RPHASE   (1  31)
 
 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)   ((v)  5)
 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)   ((v)  8)
 #define DAVINCI_MCBSP_XCR_XDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_XCR_XFIG (1  18)
 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_XCR_XFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_XCR_XPHASE   (1  31)
 
 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v)  8)
 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v)  16)
 #define DAVINCI_MCBSP_SRGR_FSGM(1  28)
+#define DAVINCI_MCBSP_SRGR_CLKSM   (1  29)
 
 #define DAVINCI_MCBSP_PCR_CLKRP(1  0)
 #define DAVINCI_MCBSP_PCR_CLKXP(1  1)
@@ -144,6 +149,11 @@ struct davinci_mcbsp_dev {
 * won't end up being swapped because of the underrun.
 */
unsigned enable_channel_combine:1;
+
+   int i2s_fast_clock;
+   unsigned int fmt;
+   int clk_div;
+   int clk_input_pin;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -254,10 +264,12 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
struct davinci_mcbsp_dev *dev = cpu_dai-private_data;
unsigned int pcr;
unsigned int srgr;
+   /* Attention srgr is updated by hw_params! */
srgr = DAVINCI_MCBSP_SRGR_FSGM |
DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
 
+   dev-fmt = fmt;
/* set master/slave audio interface */
switch (fmt  SND_SOC_DAIFMT_MASTER_MASK) {
case

Re: [PATCH] ASoC: DaVinci: Added support for stereo I2S

Hi Liam,

2010/6/23 Liam Girdwood l...@slimlogic.co.uk

 On Wed, 2010-06-23 at 16:33 +0200, Raffaele Recalcati wrote:
  From: Raffaele Recalcati raffaele.recalc...@bticino.it
 
Added audio playback support with [frame sync master - clock
 master] mode
and with [frame sync master - clock slave].
Clock slave can be important when the external codec need system
 clock
and bit clock synchronized.
In the clock master case there is a FIXME message in the source
 code, because we
(Davide and myself) have guessed a frequency of 12200 that
 seems the base
to be divided.
This patch has been developed against the
 
 http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm,
 but using
uda1345 as external audio codec).
 
  Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
  Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it

 Had a quick check, it looks like you have made some unintended
 formatting changes that make the patch look more complex than necessary.


I was making correction for keeping aligned my lines like these...
+   srgr = DAVINCI_MCBSP_SRGR_FSGM |
+  DAVINCI_MCBSP_SRGR_CLKSM;

and so I changed some existing ones...
but looking at CodingStyle and Greg notes, seems that, when breaking lines,
we need to keep alignment.
So maybe, if I'm right, in the future, we'll need to re-align all the file
with another patch..
I'll change anyway the code back to be simpler to be understood.



  ---
   arch/arm/mach-davinci/include/mach/asp.h |7 ++
   sound/soc/davinci/davinci-i2s.c  |  141
 ++
   2 files changed, 129 insertions(+), 19 deletions(-)
 
  diff --git a/arch/arm/mach-davinci/include/mach/asp.h
 b/arch/arm/mach-davinci/include/mach/asp.h
  index 834725f..b1faeb9 100644
  --- a/arch/arm/mach-davinci/include/mach/asp.h
  +++ b/arch/arm/mach-davinci/include/mach/asp.h
  @@ -63,6 +63,13 @@ struct snd_platform_data {
unsigned sram_size_playback;
unsigned sram_size_capture;
 
  + /*
  +  * This define works when both clock and FS are output for the cpu
  +  * and makes clock very fast (FS is not simmetrical, but sampling
  +  * frequency is better approximated
  +  */
  + int i2s_fast_clock;
  +
/* McASP specific fields */
int tdm_slots;
u8 op_mode;
  diff --git a/sound/soc/davinci/davinci-i2s.c
 b/sound/soc/davinci/davinci-i2s.c
  index adadcd3..8811d25 100644
  --- a/sound/soc/davinci/davinci-i2s.c
  +++ b/sound/soc/davinci/davinci-i2s.c
  @@ -68,16 +68,23 @@
   #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v)  16)
   #define DAVINCI_MCBSP_RCR_RFIG   (1  18)
   #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v)  21)
  +#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v)  24)
  +#define DAVINCI_MCBSP_RCR_RPHASE (1  31)
 
   #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v)  5)
   #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v)  8)
   #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v)  16)
   #define DAVINCI_MCBSP_XCR_XFIG   (1  18)
   #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v)  21)
  +#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v)  24)
  +#define DAVINCI_MCBSP_XCR_XPHASE (1  31)
 
  +
  +#define CLKGDV(v)(v) /* Bits 0:7 */

 Should you not have a DAVINCI prefix here too ?


Sorry, CLKGDV was not more used.
So I'm deleting it in the new patch coming today.



   #define DAVINCI_MCBSP_SRGR_FWID(v)   ((v)  8)
   #define DAVINCI_MCBSP_SRGR_FPER(v)   ((v)  16)
   #define DAVINCI_MCBSP_SRGR_FSGM  (1  28)
  +#define DAVINCI_MCBSP_SRGR_CLKSM (1  29)
 
   #define DAVINCI_MCBSP_PCR_CLKRP  (1  0)
   #define DAVINCI_MCBSP_PCR_CLKXP  (1  1)
  @@ -144,8 +151,17 @@ struct davinci_mcbsp_dev {
 * won't end up being swapped because of the underrun.
 */
unsigned enable_channel_combine:1;
  +
  + int i2s_fast_clock;
  +};
  +
  +struct davinci_mcbsp_data {
  + unsigned intfmt;
  + int clk_div;
   };
 
  +static struct davinci_mcbsp_data mcbsp_data;
  +

 This struct should be part of the dai private data.


done.



   static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev
 *dev,
   int reg, u32 val)
   {
  @@ -255,24 +271,27 @@ static int davinci_i2s_set_dai_fmt(struct
 snd_soc_dai *cpu_dai,
unsigned int pcr;
unsigned int srgr;
srgr = DAVINCI_MCBSP_SRGR_FSGM |
  - DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
  - DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
  +DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
  +DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
  + /* Attention srgr is updated by hw_params! */
 
  + mcbsp_data.fmt = fmt

[PATCH] davinci: dm365: Added swap between y and c data in isif port.

From: Raffaele Recalcati raffaele.recalc...@bticino.it

Added the possibility to change the position of y and c
data in the isif port.
This patch has been developed against the
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and tested on bmx board.

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 drivers/media/video/davinci/isif.c |6 +-
 include/media/davinci/isif.h   |2 ++
 include/media/davinci/vpfe_types.h |8 
 3 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/drivers/media/video/davinci/isif.c 
b/drivers/media/video/davinci/isif.c
index 29c29c6..02a8bdb 100644
--- a/drivers/media/video/davinci/isif.c
+++ b/drivers/media/video/davinci/isif.c
@@ -105,6 +105,7 @@ static struct isif_oper_config {
.hd_pol = VPFE_PINPOL_POSITIVE,
.pix_order = CCDC_PIXORDER_CBYCRY,
.buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED,
+   .ycswap = YCIN_NOT_SWP,
},
.bayer = {
.pix_fmt = CCDC_PIXFMT_RAW,
@@ -864,6 +865,7 @@ static void isif_setfbaddr(unsigned long addr)
 static int isif_set_hw_if_params(struct vpfe_hw_if_param *params)
 {
isif_cfg.if_type = params-if_type;
+   isif_cfg.ycbcr.ycswap = params-ycswap;
 
switch (params-if_type) {
case VPFE_BT656:
@@ -914,7 +916,9 @@ static int isif_config_ycbcr(void)
}
modeset |= (VPFE_PINPOL_NEGATIVE  ISIF_VD_POL_SHIFT);
regw(3, REC656IF);
-   ccdcfg = ccdcfg | ISIF_DATA_PACK8 | ISIF_YCINSWP_YCBCR;
+   ccdcfg = ccdcfg | ISIF_DATA_PACK8;
+   if (params-ycswap == YCIN_SWP)
+   ccdcfg |= ISIF_YCINSWP_YCBCR;
break;
case VPFE_BT656_10BIT:
if (params-pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
diff --git a/include/media/davinci/isif.h b/include/media/davinci/isif.h
index b0b74ad..b123f2c 100644
--- a/include/media/davinci/isif.h
+++ b/include/media/davinci/isif.h
@@ -466,6 +466,8 @@ struct isif_ycbcr_config {
enum vpfe_pin_pol hd_pol;
/* isif pix order. Only used for ycbcr capture */
enum ccdc_pixorder pix_order;
+   /* ccdc data connection. 8 bit ycbcr data bus connection */
+   enum vpfe_data_swap ycswap;
/* isif buffer type. Only used for ycbcr capture */
enum ccdc_buftype buf_type;
 };
diff --git a/include/media/davinci/vpfe_types.h 
b/include/media/davinci/vpfe_types.h
index 76fb74b..337c917 100644
--- a/include/media/davinci/vpfe_types.h
+++ b/include/media/davinci/vpfe_types.h
@@ -40,12 +40,20 @@ enum vpfe_hw_if_type {
VPFE_BT656_10BIT
 };
 
+/* 8 bit interface can be swapped */
+enum vpfe_data_swap {
+   YCIN_NOT_SWP,
+   YCIN_SWP,
+};
+
 /* interface description */
 struct vpfe_hw_if_param {
enum vpfe_hw_if_type if_type;
enum vpfe_pin_pol hdpol;
enum vpfe_pin_pol vdpol;
+   enum vpfe_data_swap ycswap;
 };
 
+
 #endif
 #endif
-- 
1.7.0.4

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[PATCH] spi: davinci: Added support for chip select using gpio

From: Raffaele Recalcati raffaele.recalc...@bticino.it

It is not everytime possible, due to hardware constraints,
to use the hw chip select available on spi port.
So I add this possibility using a gpio as chip select.
If controller_data variable is not null it is
the gpio to be used as chip select.
The default case is compatible with evmdm365.
This patch has been developed against the
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm but with
gpio as spi chip select).

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 arch/arm/mach-davinci/dm365.c |   10 ++
 drivers/spi/davinci_spi.c |   27 ++-
 2 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a146849..42fd4a4 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -677,10 +677,12 @@ void __init dm365_init_spi0(unsigned chipselect_mask,
davinci_cfg_reg(DM365_SPI0_SDO);
 
/* not all slaves will be wired up */
-   if (chipselect_mask  BIT(0))
-   davinci_cfg_reg(DM365_SPI0_SDENA0);
-   if (chipselect_mask  BIT(1))
-   davinci_cfg_reg(DM365_SPI0_SDENA1);
+   if  (!((unsigned long) info-controller_data)) {
+   if (chipselect_mask  BIT(0))
+   davinci_cfg_reg(DM365_SPI0_SDENA0);
+   if (chipselect_mask  BIT(1))
+   davinci_cfg_reg(DM365_SPI0_SDENA1);
+   }
 
spi_register_board_info(info, len);
 
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 95afb6b..621ae46 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -29,6 +29,7 @@
 #include linux/spi/spi_bitbang.h
 #include linux/slab.h
 
+#include mach/gpio.h
 #include mach/spi.h
 #include mach/edma.h
 
@@ -270,18 +271,26 @@ static void davinci_spi_chipselect(struct spi_device 
*spi, int value)
pdata = davinci_spi-pdata;
 
/*
-* Board specific chip select logic decides the polarity and cs
-* line for the controller
-*/
+   * Board specific chip select logic decides the polarity and cs
+   * line for the controller
+   */
if (value == BITBANG_CS_INACTIVE) {
-   set_io_bits(davinci_spi-base + SPIDEF, CS_DEFAULT);
-
-   data1_reg_val |= CS_DEFAULT  SPIDAT1_CSNR_SHIFT;
-   iowrite32(data1_reg_val, davinci_spi-base + SPIDAT1);
-
+   if  ((unsigned long) spi-controller_data) {
+   gpio_set_value(spi-controller_data, \
+   !(spi-mode  SPI_CS_HIGH));
+   } else {
+   set_io_bits(davinci_spi-base + SPIDEF, CS_DEFAULT);
+
+   data1_reg_val |= CS_DEFAULT  SPIDAT1_CSNR_SHIFT;
+   iowrite32(data1_reg_val, davinci_spi-base + SPIDAT1);
+   }
while ((ioread32(davinci_spi-base + SPIBUF)
-SPIBUF_RXEMPTY_MASK) == 0)
+SPIBUF_RXEMPTY_MASK) == 0)
cpu_relax();
+   } else {
+   if  ((unsigned long) spi-controller_data)
+   gpio_set_value(spi-controller_data, \
+   (spi-mode  SPI_CS_HIGH));
}
 }
 
-- 
1.7.0.4

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[PATCH] DaVinci: dm365: Added clockout2 management and set_sysclk_rate

From: Davide Bonfanti davide.bonfa...@bticino.it

Added also possibility to set sysclk frequency.

Added possibility to set clockout2 frequency.
Clockout2 is a child of pll1_sysclk9, because they have
the same pll divisor.

This patch has been developed against the
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and tested on bmx board.

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 arch/arm/mach-davinci/clock.c  |  113 +++-
 arch/arm/mach-davinci/clock.h  |   14 
 arch/arm/mach-davinci/dm365.c  |   23 +-
 arch/arm/mach-davinci/include/mach/clock.h |3 +
 4 files changed, 146 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 054c303..464c289 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -144,6 +144,69 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 }
 EXPORT_SYMBOL(clk_set_rate);
 
+int clkout2_set_rate(struct clk *clk, unsigned long rate)
+{
+   unsigned long flags;
+   int ret = -EINVAL;
+   int i, err, min_err, i_min_err;
+   u32 regval;
+   struct pll_data *pll;
+   struct clk *parent = clk;
+
+   if (clk == NULL || IS_ERR(clk))
+   return ret;
+   if (!cpu_is_davinci_dm365())
+   return -ENODEV;
+
+   while (parent-parent-parent)
+   parent = parent-parent;
+
+   parent = clk-parent;
+
+   if (parent == clk)
+   return -EPERM;
+
+   pll = parent-pll_data;
+   regval = __raw_readl(IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE +
+   PERI_CLKCTL));
+
+   i_min_err = min_err = INT_MAX;
+   for (i = 0x0F; i  0; i--) {
+   if (clk-set_rate) {
+   ret = clk_set_rate(clk, rate * i) ;
+   err = clk_get_rate(clk) - rate * i;
+   if (abs(min_err)  abs(err)) {
+   min_err = err;
+   i_min_err = i;
+   }
+   }
+   }
+   i = i_min_err;
+   ret = clk-set_rate(clk, rate * i) ;
+
+   regval = ~(0x0F  3);
+   regval |= (i-1)  3;
+   regval |= 1  CLOCKOUT2EN;
+   __raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE +
+   PERI_CLKCTL));
+   rate *= i;
+
+   spin_lock_irqsave(clockfw_lock, flags);
+   if (ret == 0) {
+   if (clk-recalc)
+   clk-rate = clk-recalc(clk);
+   propagate_rate(clk);
+   regval = ~(1  CLOCKOUT2EN);
+   __raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE +
+   PERI_CLKCTL));
+   } else
+   return -EINVAL;
+   spin_unlock_irqrestore(clockfw_lock, flags);
+
+   return ret;
+}
+EXPORT_SYMBOL(clkout2_set_rate);
+
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
unsigned long flags;
@@ -254,7 +317,15 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
u32 v, plldiv;
struct pll_data *pll;
unsigned long rate = clk-rate;
+   struct clk *parent = clk;
+
+   if (clk == NULL || IS_ERR(clk))
+   return -EINVAL;
+   while (parent-parent-parent)
+   parent = parent-parent;
 
+   if (parent == clk)
+   return -EPERM;
/* If this is the PLL base clock, no more calculations needed */
if (clk-pll_data)
return rate;
@@ -262,13 +333,13 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
if (WARN_ON(!clk-parent))
return rate;
 
-   rate = clk-parent-rate;
+   rate = parent-rate;
+
 
/* Otherwise, the parent must be a PLL */
-   if (WARN_ON(!clk-parent-pll_data))
+   if (WARN_ON(!parent-pll_data))
return rate;
-
-   pll = clk-parent-pll_data;
+   pll = parent-pll_data;
 
/* If pre-PLL, source clock is before the multiplier and divider(s) */
if (clk-flags  PRE_PLL)
@@ -286,6 +357,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
 
return rate;
 }
+EXPORT_SYMBOL(clk_sysclk_recalc);
 
 static unsigned long clk_leafclk_recalc(struct clk *clk)
 {
@@ -433,6 +505,39 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int 
prediv,
 }
 EXPORT_SYMBOL(davinci_set_pllrate);
 
+int set_sysclk_rate(struct clk *clk, unsigned long rate)
+{
+   u32 clk_freq_min, clk_freq_max, plldiv;
+   struct pll_data *pll;
+   struct clk *parent = clk;
+
+   while (parent-parent-parent)
+   parent = parent-parent;
+   if (parent == clk)
+   return -EPERM;
+
+   clk_freq_max = parent-rate;
+   pll = parent-pll_data;
+   if (clk-flags  PRE_PLL)
+   clk_freq_max

Re: RE: [PATCH 14/14] davinci: video: davincifb Parallel RBG LCD management

2010-06-25 Thread Raffaele Recalcati

Hi Muralidharan,

2010/6/25, Karicheri, Muralidharan m-kariche...@ti.com:
 Raffaele,


I guess you are developing V4L2 without changing the DM365 VPFE porting,
 for example I'm seeing the isif.c file equal to the one in Kevin tree.

 The vpfe driver is already upstream though it doesn’t have all the
 functionality that we have in Arago tree. That is why you are seing it in
 Kevin’s tree.

Also I don't see any info about VPFE in the readme.

 That is because this branch is for adding just vpbe v4l2 display support.

ok


Anyway I'm going on trying to understand how to implement:

 Are you willing to take up this activity to upstream VPBE fb display driver?
 If so, let me know so that I can discuss this with the TI’s development team
 and get back to you on this. I have some version of vpbe_fb.c and vpbe_fb.h
 that partially builds with the vpbe display controller. But some
 functionality to set mode is missing.

It's ok,
please send me your work.
Let me have also your .config, so I can start from something clear.
If you also some other guidelines to implement it let me know.

Thanks,
Raffaele.


 Murali Karicheri
 Software Design Engineer
 Texas Instruments Inc.
 Germantown, MD 20874
 email: m-kariche...@ti.com

 
 From: Raffaele Recalcati [mailto:lamiapost...@gmail.com]
 Sent: Thursday, June 24, 2010 11:29 AM
 To: Karicheri, Muralidharan
 Cc: Kevin Hilman; davide.bonfa...@bticino.it;
 davinci-linux-open-source@linux.davincidsp.com; Selvamani, Senthilnathan
 Subject: Re: RE: [PATCH 14/14] davinci: video: davincifb Parallel RBG LCD
 management

 Hi Muralidharan,

 2010/6/17 Karicheri, Muralidharan
 m-kariche...@ti.commailto:m-kariche...@ti.com
 Raffaele,

 You got the readme.txt right!

 Arago tree has the latest video drivers for DM365. But this is a temporary
 staging tree that has all of the video
 drivers up ported from the MV kernel. Some of these drivers (vpfe capture on
 DM6446, DM355, DM365
 and vpif capture and display on DM646x) are already up ported to mainline
 kernel and are available on
 Kevin’s tree as well (got merged via mainline kernel). devel_2_6_35rc2
 branch is used for up porting
 the display driver.

 I guess you are developing V4L2 without changing the DM365 VPFE porting, for
 example I'm seeing the isif.c file equal to the one in Kevin tree.
 Also I don't see any info about VPFE in the readme.
 Anyway I'm going on trying to understand how to implement:

 Frame buffer display device driver
 drivers/media/video/davinci/vpbe_fb.c
 drivers/media/video/davinci/vpbe_fb.h

 First of all, I'm compiling with:
 commit 01fcd84c3a781063038e6a27dd7e1cd8dc9695da
 Author: Muralidharan Karicheri
 m-kariche...@ti.commailto:m-kariche...@ti.com
 Date:   Thu Jun 17 15:13:26 2010 -0400

 and I have some compiling errors doing these commands:

 export ARCH=arm
 export
 CROSS_COMPILE=/home/sources/NEXTGEN/M/toolc/arm-2009q1/bin/arm-none-linux-gnueabi-
 make mrproper
 make davinci_all_defconfig
 make uImage

 can you please give me a good .config so I can start in a clean way?

 thanks,
 Raffaele




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Re: RE: [PATCH 14/14] davinci: video: davincifb Parallel RBG LCD management

2010-06-24 Thread Raffaele Recalcati

Hi Muralidharan,

2010/6/17 Karicheri, Muralidharan m-kariche...@ti.com

  Raffaele,



 You got the readme.txt right!



 Arago tree has the latest video drivers for DM365. But this is a temporary
 staging tree that has all of the video

 drivers up ported from the MV kernel. Some of these drivers (vpfe capture
 on DM6446, DM355, DM365

 and vpif capture and display on DM646x) are already up ported to mainline
 kernel and are available on

 Kevin’s tree as well (got merged via mainline kernel). devel_2_6_35rc2
 branch is used for up porting

 the display driver.


I guess you are developing V4L2 without changing the DM365 VPFE porting, for
example I'm seeing the isif.c file equal to the one in Kevin tree.
Also I don't see any info about VPFE in the readme.
Anyway I'm going on trying to understand how to implement:

Frame buffer display device driver
drivers/media/video/davinci/vpbe_fb.c
drivers/media/video/davinci/vpbe_fb.h

First of all, I'm compiling with:
commit 01fcd84c3a781063038e6a27dd7e1cd8dc9695da
Author: Muralidharan Karicheri m-kariche...@ti.com
Date:   Thu Jun 17 15:13:26 2010 -0400

and I have some compiling errors doing these commands:

export ARCH=arm
export
CROSS_COMPILE=/home/sources/NEXTGEN/M/toolc/arm-2009q1/bin/arm-none-linux-gnueabi-
make mrproper
make davinci_all_defconfig
make uImage

can you please give me a good .config so I can start in a clean way?

thanks,
Raffaele
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Re: [PATCH 01/14] ASoC: DaVinci: Added support for stereo I2S

2010-06-23 Thread Raffaele Recalcati

Hi Kevin,
first of all thanks for your reply.

I'm very happy to see a feedback.

2010/6/22 Kevin Hilman khil...@deeprootsystems.com

 Raffaele Recalcati lamiapost...@gmail.com writes:

  From: Raffaele Recalcati raffaele.recalc...@bticino.it
 
 - Frame Sync master and Clock master (internally generated)
 - Frame Sync master and Clock slave
 
  Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
  Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
  ---

 First, some general comments on your series.

 1) Grouping patches together in series is usually done to suggest
 interdependencies, or that all the patches go together towards a
 single problem/feature etc.  Your current series combines multiple
 patches, most of which are independent and most of which need to go
 upstream through different subsytems.


It will be done.



 For example, the audio/asoc patches go upstream through the ASoC
 maintainers, and the SPI, touchscreen, mfd, MTD drivers all have
 different subsystems and maintainers.

 The only thing that gets merged directly through me and the davinci
 git tree are changes to arch/arm/mach-davinci/*.


 So, I suggest you break this up into patches that are per-subsytem.
 In other words, one patch/series for arch/arm/mach-davinci/* another
 for audio, another for video, etc.


Ok, but what about sound/soc/davinci and similar directories?
Anyway ... the patches are sent also to davinci mailing list and you can see
them.



 To find out the right mailing lists for each of these subsystems,
 please consult the MAINTAINERS file.  A really useful tool is the
 scripts/get_maintainer.pl script.  Running that on a patch will
 suggest the right audience for that patch using the MAINTAINERS file.
 Since I gathered you're now using git-send-email, you can use this script
 in combination with git-send-email's --cc-cmd option.  e.g.

   git-send-email --to davinci list --cc-cmd=scripts/get_maintainer.pl [...]

 will automatically add the right folks to the Cc: line of the emails
 sent by git-send-email.

 2) For each series, please be sure to state what tree the patches
 were generated against, and on what platforms they were tested.


I will write for example:
The patch has been created against
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
and checked with bmx dm365 board (similar to evm dm365).


 3) Please add descriptive changelogs to each patch.  The changelog
   should describe the problem being addressed, the solution and
   why.


It will be done.



 Some other comments below on this patch...

   sound/soc/davinci/davinci-i2s.c |  120
 +++---
   1 files changed, 110 insertions(+), 10 deletions(-)
 
  diff --git a/sound/soc/davinci/davinci-i2s.c
 b/sound/soc/davinci/davinci-i2s.c
  index adadcd3..620f977 100644
  --- a/sound/soc/davinci/davinci-i2s.c
  +++ b/sound/soc/davinci/davinci-i2s.c
  @@ -68,16 +68,23 @@
   #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v)  16)
   #define DAVINCI_MCBSP_RCR_RFIG   (1  18)
   #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v)  21)
  +#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v)  24)
  +#define DAVINCI_MCBSP_RCR_RPHASE (1  31)
 
   #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v)  5)
   #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v)  8)
   #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v)  16)
   #define DAVINCI_MCBSP_XCR_XFIG   (1  18)
   #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v)  21)
  +#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v)  24)
  +#define DAVINCI_MCBSP_XCR_XPHASE (1  31)
 
  +
  +#define CLKGDV(v)(v) /* Bits 0:7 */
   #define DAVINCI_MCBSP_SRGR_FWID(v)   ((v)  8)
   #define DAVINCI_MCBSP_SRGR_FPER(v)   ((v)  16)
   #define DAVINCI_MCBSP_SRGR_FSGM  (1  28)
  +#define DAVINCI_MCBSP_SRGR_CLKSM (1  29)
 
   #define DAVINCI_MCBSP_PCR_CLKRP  (1  0)
   #define DAVINCI_MCBSP_PCR_CLKXP  (1  1)
  @@ -89,6 +96,13 @@
   #define DAVINCI_MCBSP_PCR_FSRM   (1  10)
   #define DAVINCI_MCBSP_PCR_FSXM   (1  11)
 
  +/*
  + * This define works when both clock and FS are output for the cpu
  + * and makes clock very fast (FS is not simmetrical, but sampling
  + * frequency is better approximated
  + */
  +#define I2S_FAST_CLOCK
  +
   enum {
DAVINCI_MCBSP_WORD_8 = 0,
DAVINCI_MCBSP_WORD_12,
  @@ -146,6 +160,13 @@ struct davinci_mcbsp_dev {
unsigned enable_channel_combine:1;
   };
 
  +struct davinci_mcbsp_data {
  + unsigned intfmt;

 this indent is a tab (as it should be)

  +int clk_div;

 and this is spaces.  Please use tabs throughout.


I had a checkpatch false positive.
I have fixed it sending this patch to its mantainers.
Sorry, but this mail client (gmail with webmail) converts tabs in spaces so
the following patch
is not directly usable.

diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index a4d7434..315a827 100755

[PATCH] ASoC: DaVinci: Added support for stereo I2S

2010-06-23 Thread Raffaele Recalcati

From: Raffaele Recalcati raffaele.recalc...@bticino.it

Added audio playback support with [frame sync master - clock master] 
mode
and with [frame sync master - clock slave].
Clock slave can be important when the external codec need system clock
and bit clock synchronized.
In the clock master case there is a FIXME message in the source code, 
because we
(Davide and myself) have guessed a frequency of 12200 that seems 
the base
to be divided.
This patch has been developed against the

http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and has been tested on bmx board (similar to dm365 evm, but 
using
uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 arch/arm/mach-davinci/include/mach/asp.h |7 ++
 sound/soc/davinci/davinci-i2s.c  |  141 ++
 2 files changed, 129 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h 
b/arch/arm/mach-davinci/include/mach/asp.h
index 834725f..b1faeb9 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -63,6 +63,13 @@ struct snd_platform_data {
unsigned sram_size_playback;
unsigned sram_size_capture;
 
+   /*
+* This define works when both clock and FS are output for the cpu
+* and makes clock very fast (FS is not simmetrical, but sampling
+* frequency is better approximated
+*/
+   int i2s_fast_clock;
+
/* McASP specific fields */
int tdm_slots;
u8 op_mode;
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index adadcd3..8811d25 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -68,16 +68,23 @@
 #define DAVINCI_MCBSP_RCR_RDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_RCR_RFIG (1  18)
 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_RCR_RFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_RCR_RPHASE   (1  31)
 
 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)   ((v)  5)
 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)   ((v)  8)
 #define DAVINCI_MCBSP_XCR_XDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_XCR_XFIG (1  18)
 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_XCR_XFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_XCR_XPHASE   (1  31)
 
+
+#define CLKGDV(v)  (v) /* Bits 0:7 */
 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v)  8)
 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v)  16)
 #define DAVINCI_MCBSP_SRGR_FSGM(1  28)
+#define DAVINCI_MCBSP_SRGR_CLKSM   (1  29)
 
 #define DAVINCI_MCBSP_PCR_CLKRP(1  0)
 #define DAVINCI_MCBSP_PCR_CLKXP(1  1)
@@ -144,8 +151,17 @@ struct davinci_mcbsp_dev {
 * won't end up being swapped because of the underrun.
 */
unsigned enable_channel_combine:1;
+
+   int i2s_fast_clock;
+};
+
+struct davinci_mcbsp_data {
+   unsigned intfmt;
+   int clk_div;
 };
 
+static struct davinci_mcbsp_data mcbsp_data;
+
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
   int reg, u32 val)
 {
@@ -255,24 +271,27 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
unsigned int pcr;
unsigned int srgr;
srgr = DAVINCI_MCBSP_SRGR_FSGM |
-   DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
-   DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
+  DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
+  DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
+   /* Attention srgr is updated by hw_params! */
 
+   mcbsp_data.fmt = fmt;
/* set master/slave audio interface */
switch (fmt  SND_SOC_DAIFMT_MASTER_MASK) {
+   case SND_SOC_DAIFMT_CBS_CFM:
case SND_SOC_DAIFMT_CBS_CFS:
/* cpu is master */
pcr = DAVINCI_MCBSP_PCR_FSXM |
-   DAVINCI_MCBSP_PCR_FSRM |
-   DAVINCI_MCBSP_PCR_CLKXM |
-   DAVINCI_MCBSP_PCR_CLKRM;
+ DAVINCI_MCBSP_PCR_FSRM |
+ DAVINCI_MCBSP_PCR_CLKXM |
+ DAVINCI_MCBSP_PCR_CLKRM;
break;
case SND_SOC_DAIFMT_CBM_CFS:
/* McBSP CLKR pin is the input for the Sample Rate Generator.
 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
pcr = DAVINCI_MCBSP_PCR_SCLKME |
-   DAVINCI_MCBSP_PCR_FSXM |
-   DAVINCI_MCBSP_PCR_FSRM;
+ DAVINCI_MCBSP_PCR_FSXM |
+ DAVINCI_MCBSP_PCR_FSRM

Re: RE: [PATCH 14/14] davinci: video: davincifb Parallel RBG LCD management

2010-06-17 Thread Raffaele Recalcati

Hi Karicheri,

2010/6/16 Karicheri, Muralidharan m-kariche...@ti.com

  Hi,



 A snapshot of the work can be previewed at




 http://git.linuxtv.org/mkaricheri/vpfe-vpbe-video.git?a=shortlog;h=refs/heads/devel_2_6_35rc2



 It is based on sub device interface. Currently we have ported the v4l2
 display driver and just

 build tested it. The unit test is ongoing. I have copied Senthil who is
 working on this to this email.



 This is planned to be sent to v4l2 mailing list for review once the unit
 testing is complete. Once it

 is merged to the v4l2 tree, it will become part of kernel.org git tree
 through upstream merge.



 The fb driver will be ported next. Do you think you have some bandwidth to
 up port the fbdev driver

 in parallel so that we can speed up this? I have put a readme.txt


Looking at :

commit 5e01fcc3e352a6600706ba36dd0736089abb3781
Author: Murali Karicheri mkarich...@gmail.com
Date:   Sun Jun 13 13:11:59 2010 -0400

some cosmetic changes added to osd and venc modules


Here my .git/config

[remote linuxtv]
url = http://linuxtv.org/git/mkaricheri/vpfe-vpbe-video.git
fetch = +refs/heads/*:refs/remotes/linuxtv/*
[branch media-master]
remote = linuxtv
merge = refs/heads/master
[branch devel_2_6_35rc2]
remote = linuxtv
merge = refs/heads/devel_2_6_35rc2


I've found :
find . -iname *readme*  | grep video
...
..
./drivers/media/video/davinci/VPBE-display-design-readme.txt

it is the right file?

  (under media/video/davinci) that

 explains the vpbe display controller that we use (based on sub device
 interface) for this. I have

 added basic support for LogicPD LCD display support and your input will
 help us to improve

 this driver.


The 2.6.31 arago development is actually a good check for evm dm365.
The 2.6.34 Kevin Hilman instead is the actual base for our bmx board.
I sent,  in June the 11, the patchset involving some easy linux general
fixes and some additions to DaVinci development, for instance fb parallel
LCD, i2s stereo, mtd-nand 16bit, ...
[PATCH 14/14] davinci: video: davincifb Parallel RBG LCD management
[PATCH 13/14] davinci: video: davincifb Added operation in order to turn
on/off hw in platform management
[PATCH 12/14] davinci: video: davincifb import fb parameters from platform
data
[PATCH 10/14] DaVinci: dm365: Added clokout2 management and set_sysclk_rate
[PATCH 05/14] mtd-nand: davinci: Added 16 bit wide bus for DaVinci bmx board
[PATCH 03/14] davinci: dm365: Added swap between y and c data in isif port.
[PATCH 02/14] spi: davinci: Added support for chip select using gpio
[PATCH 01/14] ASoC: DaVinci: Added support for stereo I2S

The remaining work for us involve:
1. DVSDK compatibility with 2.6.34 or later kernel  (OE or Arago based
compilation is preferred)
(needed completely tested before november included our applications)
1.1 deciding if to use Arago or OE .. which toolchain? (choose needed within
this month)
2. tvp5151 (maybe nothing to do..)
3. nand better tests
4. ubl for dm365 - we are starting a project in order to be included in
http://sourceforge.net/projects/dvflashutils.
5. u-boot tests

Our focus is on dm365, but we'd prefer to make changes compatible with
DaVinci family.

Finally we can surely join to
devel_2_6_35rc2http://git.linuxtv.org/mkaricheri/vpfe-vpbe-video.git?a=shortlog;h=refs/heads/devel_2_6_35rc2
work, but first I need a better clarification of our development roadmap and
who is mantaining what.

Best Regards,
Raffaele Recalcati
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Re: RE: [PATCH 14/14] davinci: video: davincifb Parallel RBG LCD management

2010-06-17 Thread Raffaele Recalcati

Hi Muralidharan,

2010/6/17 Karicheri, Muralidharan m-kariche...@ti.com

Raffaele,

You got the readme.txt right!

:)
I'm reading it.

Arago tree has the latest video drivers for DM365. But this is a temporary
staging tree that has all of the video

drivers up ported from the MV kernel. Some of these drivers (vpfe capture
on DM6446, DM355, DM365

and vpif capture and display on DM646x) are already up ported to mainline
kernel and are available on

Kevin’s tree as well (got merged via mainline kernel). devel_2_6_35rc2
branch is used for up porting

the display driver.

Now if you are using Arago tree, the FB driver supports many features
compared to the obsolete

fb driver in the Kevin’s linux-davinci tree. Not sure why you are not using
this tree as your baseline.

I'm not sure to understand exactly.
My baseline is Kevin's tree now.

My requirement:
1. DVSDK compatibility with 2.6.34 or later kernel (OE or Arago based
compilation is preferred)
(needed completely tested before november included our applications)
can be assured with which kernel version?

arago = yes, but it means my all system becomes immediately OLD.
kevin's = probably never
devel_2_6_35rc2 = when?

Raffaele

Murali Karicheri
Software Design Engineer
Texas Instruments Inc.
Germantown, MD 20874
email: m-kariche...@ti.com
--

*From:* Raffaele Recalcati [mailto:lamiapost...@gmail.com]
*Sent:* Thursday, June 17, 2010 3:14 AM
*To:* Karicheri, Muralidharan; Kevin Hilman
*Cc:* davide.bonfa...@bticino.it;
davinci-linux-open-source@linux.davincidsp.com; Selvamani, Senthilnathan
*Subject:* Re: RE: [PATCH 14/14] davinci: video: davincifb Parallel RBG
LCD management

Hi Karicheri,

2010/6/16 Karicheri, Muralidharan m-kariche...@ti.com

Hi,

A snapshot of the work can be previewed at

http://git.linuxtv.org/mkaricheri/vpfe-vpbe-video.git?a=shortlog;h=refs/heads/devel_2_6_35rc2

It is based on sub device interface. Currently we have ported the v4l2
display driver and just

build tested it. The unit test is ongoing. I have copied Senthil who is
working on this to this email.

This is planned to be sent to v4l2 mailing list for review once the unit
testing is complete. Once it

is merged to the v4l2 tree, it will become part of kernel.org git tree
through upstream merge.

The fb driver will be ported next. Do you think you have some bandwidth to
up port the fbdev driver

in parallel so that we can speed up this? I have put a readme.txt

Looking at :

commit 5e01fcc3e352a6600706ba36dd0736089abb3781
Author: Murali Karicheri mkarich...@gmail.com
Date: Sun Jun 13 13:11:59 2010 -0400

some cosmetic changes added to osd and venc modules

Here my .git/config

[remote linuxtv]
url = http://linuxtv.org/git/mkaricheri/vpfe-vpbe-video.git
fetch = +refs/heads/*:refs/remotes/linuxtv/*
[branch media-master]
remote = linuxtv
merge = refs/heads/master
[branch devel_2_6_35rc2]
remote = linuxtv
merge = refs/heads/devel_2_6_35rc2

I've found :
find . -iname *readme* | grep video
...
..
./drivers/media/video/davinci/VPBE-display-design-readme.txt

it is the right file?

(under media/video/davinci) that

explains the vpbe display controller that we use (based on sub device
interface) for this. I have

added basic support for LogicPD LCD display support and your input will
help us to improve

this driver.

The 2.6.31 arago development is actually a good check for evm dm365.
The 2.6.34 Kevin Hilman instead is the actual base for our bmx board.
I sent, in June the 11, the patchset involving some easy linux general
fixes and some additions to DaVinci development, for instance fb parallel
LCD, i2s stereo, mtd-nand 16bit, ...
[PATCH 14/14] davinci: video: davincifb Parallel RBG LCD management
[PATCH 13/14] davinci: video: davincifb Added operation in order to turn
on/off hw in platform management
[PATCH 12/14] davinci: video: davincifb import fb parameters from platform
data
[PATCH 10/14] DaVinci: dm365: Added clokout2 management and set_sysclk_rate
[PATCH 05/14] mtd-nand: davinci: Added 16 bit wide bus for DaVinci bmx
board
[PATCH 03/14] davinci: dm365: Added swap between y and c data in isif port.
[PATCH 02/14] spi: davinci: Added support for chip select using gpio
[PATCH 01/14] ASoC: DaVinci: Added support for stereo I2S

The remaining work for us involve:
1. DVSDK compatibility with 2.6.34 or later kernel (OE or Arago based
compilation is preferred)
(needed completely tested before november included our applications)
1.1 deciding if to use Arago or OE .. which toolchain? (choose needed
within this month)
2. tvp5151 (maybe nothing to do..)
3. nand better tests
4. ubl for dm365 - we are starting a project in order to be included in
http://sourceforge.net/projects/dvflashutils.
5. u-boot tests

Our focus is on dm365, but we'd prefer to make changes compatible

Re: [PATCH] DM365EVM: Fix up PHY Clocksource to enable USB Host on DM365EVM

2010-06-15 Thread Raffaele Recalcati

2010/6/14 Kieran Bingham kieranbing...@gmail.com

 Hi Raffaele,

 I'm afraid I'm only using the USB in Host Mode - I have not looked at
 anything in gadget mode.

 Have you tried using the Arago Tree yet ?
 --
 Regards
 Kieran


I made a test with Arago tree and evaluation board with usb slave and worked
with ubuntu host.
Now I moved to Kevin Hilman tree and I hope to fix all bugs there.

Thx for your reply!
Raffaele
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Re: [PATCH] DM365EVM: Fix up PHY Clocksource to enable USB Host on DM365EVM

2010-06-14 Thread Raffaele Recalcati

Hi Kieran,

2010/6/8 Kieran Bingham kieranbing...@gmail.com

 From: Kieran Bingham kbing...@mpc-data.co.uk

 This patch was created by pulling in the code required from the Arago Tree.
 Checked by running on a Spectrum Digital DM365EVM Revision C.

 Signed-off-by: Kieran Bingham kbing...@mpc-data.co.uk
 ---
  arch/arm/mach-davinci/board-dm365-evm.c |   13 +
  drivers/usb/musb/davinci.c  |   12 
  drivers/usb/musb/davinci.h  |4 
  3 files changed, 29 insertions(+), 0 deletions(-)

 diff --git a/arch/arm/mach-davinci/board-dm365-evm.c
 b/arch/arm/mach-davinci/board-dm365-evm.c
 index fdb073e..c4a05fc 100644
 --- a/arch/arm/mach-davinci/board-dm365-evm.c
 +++ b/arch/arm/mach-davinci/board-dm365-evm.c
 @@ -18,6 +18,7 @@
  #include linux/i2c.h
  #include linux/io.h
  #include linux/clk.h
 +#include linux/gpio.h
  #include linux/i2c/at24.h
  #include linux/leds.h
  #include linux/mtd/mtd.h
 @@ -39,6 +40,7 @@
  #include mach/mmc.h
  #include mach/nand.h
  #include mach/keyscan.h
 +#include mach/usb.h

  #include media/tvp514x.h

 @@ -590,6 +592,15 @@ static struct spi_board_info dm365_evm_spi_info[]
 __initconst = {
},
  };

 +static void dm365evm_usb_configure(void)
 +{
 +   davinci_cfg_reg(DM365_GPIO33);
 +   gpio_request(33, usb);
 +   gpio_direction_output(33, 1);
 +   davinci_setup_usb(500, 8);
 +}
 +
 +
  static __init void dm365_evm_init(void)
  {
evm_init_i2c();
 @@ -607,6 +618,8 @@ static __init void dm365_evm_init(void)
dm365_init_rtc();
dm365_init_ks(dm365evm_ks_data);

 +   dm365evm_usb_configure();
 +
dm365_init_spi0(BIT(0), dm365_evm_spi_info,
ARRAY_SIZE(dm365_evm_spi_info));
  }
 diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
 index ce2e16f..3736792 100644
 --- a/drivers/usb/musb/davinci.c
 +++ b/drivers/usb/musb/davinci.c
 @@ -64,6 +64,16 @@ static inline void phy_on(void)
/* power everything up; start the on-chip PHY and its PLL */
phy_ctrl = ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
 +
 +   if (cpu_is_davinci_dm365()) {
 +   /*
 +* DM365 PHYCLKFREQ field [15:12] is set to 2
 +* to get clock from 24MHz crystal
 +*/
 +   phy_ctrl |= USBPHY_CLKFREQ_24MHZ;
 +   /*phy_ctrl = ~USBPHY_PHYPDWN;*/
 +   }
 +
__raw_writel(phy_ctrl, USB_PHY_CTRL);

/* wait for PLL to lock before proceeding */
 @@ -188,6 +198,8 @@ static void davinci_source_power(struct musb *musb, int
 is_on, int immediate)
if (immediate)
vbus_state = is_on;
  #endif
 +   if (cpu_is_davinci_dm365())
 +   gpio_set_value(33, is_on);
  }

  static void davinci_set_vbus(struct musb *musb, int is_on)
 diff --git a/drivers/usb/musb/davinci.h b/drivers/usb/musb/davinci.h
 index 046c844..0577ec6 100644
 --- a/drivers/usb/musb/davinci.h
 +++ b/drivers/usb/musb/davinci.h
 @@ -16,6 +16,10 @@

  /* Integrated highspeed/otg PHY */
  #define USBPHY_CTL_PADDR   (DAVINCI_SYSTEM_MODULE_BASE + 0x34)
 +#define USBPHY_NDATAPOLBIT(18)
 +#define USBPHY_SESSION_VBUSBIT(17)
 +#define USBPHY_PERI_USBID  BIT(16)
 +#define USBPHY_CLKFREQ_24MHZ   BIT(13)
  #define USBPHY_DATAPOL BIT(11) /* (dm355) switch D+/D- */
  #define USBPHY_PHYCLKGDBIT(8)
  #define USBPHY_SESNDEN BIT(7)  /* v(sess_end) comparator */
 --
 1.6.2.1

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I have applied and tested your patch.
On the target:
modprobe g_cdc
or
modprobe g_ether
ifconfig usb0 128.16.0.1 netmask 255.255.224.0

and on the ubuntu host:
ifconfig usb0 128.16.0.2 netmask 255.255.224.0

Instead the win-xp host can't do get_descriptor.
I've tested also with beagle sniffer.

With win-xp host I get only:
and the win-xp thinks to see null vid and pids.
=
musb_hdrc: version 6.0, pio, peripheral, debug=0
musb_hdrc: ConfigData=0x06 (UTMI-8, dyn FIFOs, SoftConn)
musb_hdrc: MHDRC RTL version 1.500
musb_hdrc: setup fifo_mode 2
musb_hdrc: 7/9 max ep, 2624/4096 memory
musb_hdrc musb_hdrc: USB Peripheral mode controller at fec64000 using PIO,
IRQ 12
g_ether gadget: using random self ethernet address
g_ether gadget: using random host ethernet address
usb0: MAC 82:aa:9e:2a:87:e1
usb0: HOST MAC 6a:eb:1b:a6:67:69
g_ether gadget: Ethernet Gadget, version: Memorial Day 2008
g_ether gadget: g_ether ready
musb_stage0_irq 384: == Power=f0, DevCtl=99, int_usb=0x4
musb_stage0_irq 767: BUS RESET as b_idle
musb_g_reset 2013: == B-Device addr=0 driver 'g_ether'
musb_stage0_irq 384: == Power=f0, DevCtl=99, int_usb=0x4
musb_stage0_irq 767: BUS RESET as b_peripheral

[PATCH 01/14] ASoC: DaVinci: Added support for stereo I2S

From: Raffaele Recalcati raffaele.recalc...@bticino.it

 - Frame Sync master and Clock master (internally generated)
 - Frame Sync master and Clock slave

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 sound/soc/davinci/davinci-i2s.c |  120 +++---
 1 files changed, 110 insertions(+), 10 deletions(-)

diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index adadcd3..620f977 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -68,16 +68,23 @@
 #define DAVINCI_MCBSP_RCR_RDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_RCR_RFIG (1  18)
 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_RCR_RFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_RCR_RPHASE   (1  31)
 
 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)   ((v)  5)
 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)   ((v)  8)
 #define DAVINCI_MCBSP_XCR_XDATDLY(v)   ((v)  16)
 #define DAVINCI_MCBSP_XCR_XFIG (1  18)
 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)   ((v)  21)
+#define DAVINCI_MCBSP_XCR_XFRLEN2(v)   ((v)  24)
+#define DAVINCI_MCBSP_XCR_XPHASE   (1  31)
 
+
+#define CLKGDV(v)  (v) /* Bits 0:7 */
 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v)  8)
 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v)  16)
 #define DAVINCI_MCBSP_SRGR_FSGM(1  28)
+#define DAVINCI_MCBSP_SRGR_CLKSM   (1  29)
 
 #define DAVINCI_MCBSP_PCR_CLKRP(1  0)
 #define DAVINCI_MCBSP_PCR_CLKXP(1  1)
@@ -89,6 +96,13 @@
 #define DAVINCI_MCBSP_PCR_FSRM (1  10)
 #define DAVINCI_MCBSP_PCR_FSXM (1  11)
 
+/*
+ * This define works when both clock and FS are output for the cpu
+ * and makes clock very fast (FS is not simmetrical, but sampling
+ * frequency is better approximated
+ */
+#define I2S_FAST_CLOCK
+
 enum {
DAVINCI_MCBSP_WORD_8 = 0,
DAVINCI_MCBSP_WORD_12,
@@ -146,6 +160,13 @@ struct davinci_mcbsp_dev {
unsigned enable_channel_combine:1;
 };
 
+struct davinci_mcbsp_data {
+   unsigned intfmt;
+int clk_div;
+};
+
+static struct davinci_mcbsp_data mcbsp_data;
+
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
   int reg, u32 val)
 {
@@ -257,9 +278,12 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
srgr = DAVINCI_MCBSP_SRGR_FSGM |
DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
+   /* Attention srgr is updated by hw_params! */
 
+   mcbsp_data.fmt = fmt;
/* set master/slave audio interface */
switch (fmt  SND_SOC_DAIFMT_MASTER_MASK) {
+   case SND_SOC_DAIFMT_CBS_CFM:
case SND_SOC_DAIFMT_CBS_CFS:
/* cpu is master */
pcr = DAVINCI_MCBSP_PCR_FSXM |
@@ -372,6 +396,17 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai 
*cpu_dai,
return 0;
 }
 
+static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
+   int div_id, int div)
+{
+   struct davinci_mcbsp_dev *dev = cpu_dai-private_data;
+   int srgr;
+
+   mcbsp_data.clk_div = div;
+return 0;
+}
+
+
 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 struct snd_pcm_hw_params *params,
 struct snd_soc_dai *dai)
@@ -380,11 +415,12 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
struct davinci_pcm_dma_params *dma_params =
dev-dma_params[substream-stream];
struct snd_interval *i = NULL;
-   int mcbsp_word_length;
-   unsigned int rcr, xcr, srgr;
+   int mcbsp_word_length, master;
+   unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
u32 spcr;
snd_pcm_format_t fmt;
unsigned element_cnt = 1;
+   struct clk *clk;
 
/* general line settings */
spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
@@ -396,12 +432,53 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream 
*substream,
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
}
 
-   i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
-   srgr = DAVINCI_MCBSP_SRGR_FSGM;
-   srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
+   master = mcbsp_data.fmt  SND_SOC_DAIFMT_MASTER_MASK;
+   fmt = params_format(params);
+   mcbsp_word_length = asp_word_length[fmt];
 
-   i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
-   srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
+   if (master == SND_SOC_DAIFMT_CBS_CFS) {
+   clk = clk_get(NULL, pll1_sysclk6);
+   if (clk

[PATCH 02/14] spi: davinci: Added support for chip select using gpio

From: Raffaele Recalcati raffaele.recalc...@bticino.it

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 arch/arm/mach-davinci/dm365.c |   10 ++
 drivers/spi/davinci_spi.c |   27 ++-
 2 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a146849..42fd4a4 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -677,10 +677,12 @@ void __init dm365_init_spi0(unsigned chipselect_mask,
davinci_cfg_reg(DM365_SPI0_SDO);
 
/* not all slaves will be wired up */
-   if (chipselect_mask  BIT(0))
-   davinci_cfg_reg(DM365_SPI0_SDENA0);
-   if (chipselect_mask  BIT(1))
-   davinci_cfg_reg(DM365_SPI0_SDENA1);
+   if  (!((unsigned long) info-controller_data)) {
+   if (chipselect_mask  BIT(0))
+   davinci_cfg_reg(DM365_SPI0_SDENA0);
+   if (chipselect_mask  BIT(1))
+   davinci_cfg_reg(DM365_SPI0_SDENA1);
+   }
 
spi_register_board_info(info, len);
 
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 95afb6b..621ae46 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -29,6 +29,7 @@
 #include linux/spi/spi_bitbang.h
 #include linux/slab.h
 
+#include mach/gpio.h
 #include mach/spi.h
 #include mach/edma.h
 
@@ -270,18 +271,26 @@ static void davinci_spi_chipselect(struct spi_device 
*spi, int value)
pdata = davinci_spi-pdata;
 
/*
-* Board specific chip select logic decides the polarity and cs
-* line for the controller
-*/
+   * Board specific chip select logic decides the polarity and cs
+   * line for the controller
+   */
if (value == BITBANG_CS_INACTIVE) {
-   set_io_bits(davinci_spi-base + SPIDEF, CS_DEFAULT);
-
-   data1_reg_val |= CS_DEFAULT  SPIDAT1_CSNR_SHIFT;
-   iowrite32(data1_reg_val, davinci_spi-base + SPIDAT1);
-
+   if  ((unsigned long) spi-controller_data) {
+   gpio_set_value(spi-controller_data, \
+   !(spi-mode  SPI_CS_HIGH));
+   } else {
+   set_io_bits(davinci_spi-base + SPIDEF, CS_DEFAULT);
+
+   data1_reg_val |= CS_DEFAULT  SPIDAT1_CSNR_SHIFT;
+   iowrite32(data1_reg_val, davinci_spi-base + SPIDAT1);
+   }
while ((ioread32(davinci_spi-base + SPIBUF)
-SPIBUF_RXEMPTY_MASK) == 0)
+SPIBUF_RXEMPTY_MASK) == 0)
cpu_relax();
+   } else {
+   if  ((unsigned long) spi-controller_data)
+   gpio_set_value(spi-controller_data, \
+   (spi-mode  SPI_CS_HIGH));
}
 }
 
-- 
1.7.0.4

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[PATCH 06/14] fb: Added composite sync high active mode

From: Davide Bonfanti davide.bonfa...@bticino.it

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 include/linux/fb.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/fb.h b/include/linux/fb.h
index c10163b..578a8de 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -212,6 +212,7 @@ struct fb_bitfield {
/* vtotal = 144d/288n/576i = PAL  */
/* vtotal = 121d/242n/484i = NTSC */
 #define FB_SYNC_ON_GREEN   32  /* sync on green */
+#define FB_SYNC_PIXCLOCK_HIGH_ACT  64  /* composite sync high active   
*/
 
 #define FB_VMODE_NONINTERLACED  0  /* non interlaced */
 #define FB_VMODE_INTERLACED1   /* interlaced   */
-- 
1.7.0.4

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[PATCH 04/14] ads7846: setting pen_down direction in input

From: Raffaele Recalcati raffaele.recalc...@bticino.it

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 drivers/input/touchscreen/ads7846.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/input/touchscreen/ads7846.c 
b/drivers/input/touchscreen/ads7846.c
index 532279c..226dbdc 100644
--- a/drivers/input/touchscreen/ads7846.c
+++ b/drivers/input/touchscreen/ads7846.c
@@ -872,6 +872,8 @@ static int __devinit setup_pendown(struct spi_device *spi, 
struct ads7846 *ts)
return err;
}
 
+   gpio_direction_input(pdata-gpio_pendown);
+
ts-gpio_pendown = pdata-gpio_pendown;
return 0;
 }
-- 
1.7.0.4

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[PATCH 05/14] mtd-nand: davinci: Added 16 bit wide bus for DaVinci bmx board

From: Davide Bonfanti davide.bonfa...@bticino.it

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 drivers/mtd/nand/davinci_nand.c |   42 +++
 1 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 103235e..7818dc3 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -508,6 +508,38 @@ static void __init nand_dm6446evm_flash_init(struct 
davinci_nand_info *info)
}
 }
 
+static void __init nand_bmx_flash_init(struct davinci_nand_info *info)
+{
+   uint32_t regval, a1cr;
+
+   /*
+* NAND FLASH timings @ PLL1 == 459 MHz
+*  - AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz
+*  - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns
+*/
+   regval = 0
+   | (0  31)   /* selectStrobe */
+   | (1  30)   /* extWait (never with NAND) */
+   | (0  26)   /* writeSetup  10 ns */
+   | (4  20)   /* writeStrobe 40 ns */
+   | (0  17)   /* writeHold   10 ns */
+   | (0  13)   /* readSetup   10 ns */
+   | (4  7)/* readStrobe  60 ns */
+   | (0  4)/* readHold10 ns */
+   | (1  2)/* turnAround  ?? ns */
+   | (1  0)/* asyncSize   16-bit bus */
+   ;
+   a1cr = davinci_nand_readl(info, A1CR_OFFSET);
+   if (a1cr != regval) {
+   dev_err(info-dev, Warning: NAND config: Set A1CR  \
+  reg to 0x%08x, was 0x%08x, should be done by  \
+  bootloader.\n, regval, a1cr);
+   davinci_nand_writel(info, A1CR_OFFSET, regval);
+   }
+
+}
+
+
 /*--*/
 
 /* An ECC layout for using 4-bit ECC with small-page flash, storing
@@ -697,6 +729,16 @@ static int __init nand_davinci_probe(struct 
platform_device *pdev)
 */
if (machine_is_davinci_evm())
nand_dm6446evm_flash_init(info);
+   else if (machine_is_bmx())
+   nand_bmx_flash_init(info);
+   /*
+* No reason to do this,
+* because the boot loader
+* is booting the kernel
+* that is in the nand flash
+* and so EMIF must already
+* configured
+*/
 
spin_lock_irq(davinci_nand_lock);
 
-- 
1.7.0.4

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[PATCH 03/14] davinci: dm365: Added swap between y and c data in isif port.

From: Raffaele Recalcati raffaele.recalc...@bticino.it

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 drivers/media/video/davinci/isif.c |6 +-
 include/media/davinci/isif.h   |2 ++
 include/media/davinci/vpfe_types.h |8 
 3 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/drivers/media/video/davinci/isif.c 
b/drivers/media/video/davinci/isif.c
index 29c29c6..02a8bdb 100644
--- a/drivers/media/video/davinci/isif.c
+++ b/drivers/media/video/davinci/isif.c
@@ -105,6 +105,7 @@ static struct isif_oper_config {
.hd_pol = VPFE_PINPOL_POSITIVE,
.pix_order = CCDC_PIXORDER_CBYCRY,
.buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED,
+   .ycswap = YCIN_NOT_SWP,
},
.bayer = {
.pix_fmt = CCDC_PIXFMT_RAW,
@@ -864,6 +865,7 @@ static void isif_setfbaddr(unsigned long addr)
 static int isif_set_hw_if_params(struct vpfe_hw_if_param *params)
 {
isif_cfg.if_type = params-if_type;
+   isif_cfg.ycbcr.ycswap = params-ycswap;
 
switch (params-if_type) {
case VPFE_BT656:
@@ -914,7 +916,9 @@ static int isif_config_ycbcr(void)
}
modeset |= (VPFE_PINPOL_NEGATIVE  ISIF_VD_POL_SHIFT);
regw(3, REC656IF);
-   ccdcfg = ccdcfg | ISIF_DATA_PACK8 | ISIF_YCINSWP_YCBCR;
+   ccdcfg = ccdcfg | ISIF_DATA_PACK8;
+   if (params-ycswap == YCIN_SWP)
+   ccdcfg |= ISIF_YCINSWP_YCBCR;
break;
case VPFE_BT656_10BIT:
if (params-pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
diff --git a/include/media/davinci/isif.h b/include/media/davinci/isif.h
index b0b74ad..b123f2c 100644
--- a/include/media/davinci/isif.h
+++ b/include/media/davinci/isif.h
@@ -466,6 +466,8 @@ struct isif_ycbcr_config {
enum vpfe_pin_pol hd_pol;
/* isif pix order. Only used for ycbcr capture */
enum ccdc_pixorder pix_order;
+   /* ccdc data connection. 8 bit ycbcr data bus connection */
+   enum vpfe_data_swap ycswap;
/* isif buffer type. Only used for ycbcr capture */
enum ccdc_buftype buf_type;
 };
diff --git a/include/media/davinci/vpfe_types.h 
b/include/media/davinci/vpfe_types.h
index 76fb74b..337c917 100644
--- a/include/media/davinci/vpfe_types.h
+++ b/include/media/davinci/vpfe_types.h
@@ -40,12 +40,20 @@ enum vpfe_hw_if_type {
VPFE_BT656_10BIT
 };
 
+/* 8 bit interface can be swapped */
+enum vpfe_data_swap {
+   YCIN_NOT_SWP,
+   YCIN_SWP,
+};
+
 /* interface description */
 struct vpfe_hw_if_param {
enum vpfe_hw_if_type if_type;
enum vpfe_pin_pol hdpol;
enum vpfe_pin_pol vdpol;
+   enum vpfe_data_swap ycswap;
 };
 
+
 #endif
 #endif
-- 
1.7.0.4

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[PATCH 09/14] mfd: update gfp/slab.h includes

From: Tejun Heo t...@kernel.org

Implicit slab.h inclusion via percpu.h is about to go away.  Make sure
gfp.h or slab.h is included as necessary.

Signed-off-by: Tejun Heo t...@kernel.org
Acked-by: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Mark Brown broo...@opensource.wolfsonmicro.com
---
 drivers/mfd/davinci_voicecodec.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/mfd/davinci_voicecodec.c b/drivers/mfd/davinci_voicecodec.c
index 9886aa8..3e75f02 100644
--- a/drivers/mfd/davinci_voicecodec.c
+++ b/drivers/mfd/davinci_voicecodec.c
@@ -23,6 +23,7 @@
 #include linux/init.h
 #include linux/module.h
 #include linux/device.h
+#include linux/slab.h
 #include linux/delay.h
 #include linux/io.h
 #include linux/clk.h
-- 
1.7.0.4

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[PATCH 11/14] regulator: add support for Dallas DS1803 dual digital potentiometer

From: Rodolfo Giometti giome...@linux.it

Signed-off-by: Rodolfo Giometti giome...@linux.it
Acked-by: Raffaele Recalcati raffaele.recalc...@bticino.it
Acked-by: Enrico Valtolina enrico.valtol...@bticino.it
---
 drivers/regulator/Kconfig|7 ++
 drivers/regulator/Makefile   |1 +
 drivers/regulator/ds1803.c   |  204 ++
 include/linux/regulator/ds1803.h |   41 
 4 files changed, 253 insertions(+), 0 deletions(-)
 create mode 100644 drivers/regulator/ds1803.c
 create mode 100644 include/linux/regulator/ds1803.h

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 04f2e08..ebaf09b 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -201,5 +201,12 @@ config REGULATOR_88PM8607
help
  This driver supports 88PM8607 voltage regulator chips.
 
+config REGULATOR_DS1803
+   tristate Dallas Maxim DS1803 addressable dual digital potentiometer
+   depends on I2C
+   help
+ Say Y here to support the dual digital potentiometer on
+ Dallas Maxim DS1803
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 4e7feec..c0fe050 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
 obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
 obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
 obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
+obj-$(CONFIG_REGULATOR_DS1803) += ds1803.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/ds1803.c b/drivers/regulator/ds1803.c
new file mode 100644
index 000..8621a59
--- /dev/null
+++ b/drivers/regulator/ds1803.c
@@ -0,0 +1,204 @@
+/*
+ * ds1803.c  --  Voltage regulation for the DS1803
+ *
+ * Copyright (C) 2009 Rodolfo Giometti giome...@linux.it
+ * Copyright (C) 2009 Bticino S.p.A. i...@bticino.it
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include linux/module.h
+#include linux/err.h
+#include linux/i2c.h
+#include linux/platform_device.h
+#include linux/regulator/driver.h
+#include linux/regulator/ds1803.h
+#include linux/slab.h
+
+struct ds1803_data {
+   struct i2c_client *client;
+   struct regulator_dev *rdev;
+
+   unsigned int min_uV;/* voltage for selector value 0 */
+   unsigned int max_uV;/* voltage for selector value 255 */
+   unsigned int init_uV;   /* initial voltage */
+};
+
+/*
+ * Low level functions
+ */
+
+static u8 ds1803_write_pot_lut[] = { 0xa9, 0xaa, /* both not supported */ };
+
+static int ds1803_set_voltage(struct regulator_dev *rdev,
+   int min_uV, int max_uV)
+{
+   struct ds1803_data *ds1803 = rdev_get_drvdata(rdev);
+   struct i2c_client *client = ds1803-client;
+   unsigned int id = rdev_get_id(rdev);
+   int val;
+   u8 buf[2] = { ds1803_write_pot_lut[id], 0 };
+   struct i2c_msg msgs[1] = {
+   { client-addr  , 0, 2, buf },
+   };
+   int ret;
+
+
+   val = (min_uV - ds1803-min_uV) * 255 / ds1803-max_uV;
+
+   pr_notice(%s Writing %d to pot %d\n,__func__, val,id);
+
+   if (val  0 || val  255)
+   return -EINVAL;
+   buf[1] = val;
+
+   ret = i2c_transfer(client-adapter, msgs[0], 1);
+   if (ret != 1) {
+   dev_err(client-dev, %s: write error\n, __func__);
+   return -EIO;
+   }
+
+   return 0;
+}
+
+static int ds1803_list_voltage(struct regulator_dev *rdev, unsigned index)
+{
+   struct ds1803_data *ds1803 = rdev_get_drvdata(rdev);
+
+   return (ds1803-max_uV - ds1803-min_uV) * index / 255
+   + ds1803-min_uV;
+}
+
+/*
+ * Regulator methods
+ */
+
+static struct regulator_ops ds1803_voltage_ops = {
+   .set_voltage = ds1803_set_voltage,
+   .list_voltage = ds1803_list_voltage,
+};
+
+static char *ds1803_names[] = {
+   [DS1803_100K] = trimmer_100k,
+   [DS1803_50K] = trimmer_50k,
+   [DS1803_10K] = trimmer_10k,
+};
+
+static struct regulator_desc ds1803_reg[] = {
+   {
+   .type = REGULATOR_VOLTAGE,
+   .id = 0,
+   .n_voltages = 256,
+   .ops

[PATCH 10/14] DaVinci: dm365: Added clokout2 management and set_sysclk_rate

From: Davide Bonfanti davide.bonfa...@bticino.it

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 arch/arm/mach-davinci/clock.c  |  113 +++-
 arch/arm/mach-davinci/clock.h  |   14 
 arch/arm/mach-davinci/dm365.c  |   23 +-
 arch/arm/mach-davinci/include/mach/clock.h |3 +
 4 files changed, 146 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 054c303..464c289 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -144,6 +144,69 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 }
 EXPORT_SYMBOL(clk_set_rate);
 
+int clkout2_set_rate(struct clk *clk, unsigned long rate)
+{
+   unsigned long flags;
+   int ret = -EINVAL;
+   int i, err, min_err, i_min_err;
+   u32 regval;
+   struct pll_data *pll;
+   struct clk *parent = clk;
+
+   if (clk == NULL || IS_ERR(clk))
+   return ret;
+   if (!cpu_is_davinci_dm365())
+   return -ENODEV;
+
+   while (parent-parent-parent)
+   parent = parent-parent;
+
+   parent = clk-parent;
+
+   if (parent == clk)
+   return -EPERM;
+
+   pll = parent-pll_data;
+   regval = __raw_readl(IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE +
+   PERI_CLKCTL));
+
+   i_min_err = min_err = INT_MAX;
+   for (i = 0x0F; i  0; i--) {
+   if (clk-set_rate) {
+   ret = clk_set_rate(clk, rate * i) ;
+   err = clk_get_rate(clk) - rate * i;
+   if (abs(min_err)  abs(err)) {
+   min_err = err;
+   i_min_err = i;
+   }
+   }
+   }
+   i = i_min_err;
+   ret = clk-set_rate(clk, rate * i) ;
+
+   regval = ~(0x0F  3);
+   regval |= (i-1)  3;
+   regval |= 1  CLOCKOUT2EN;
+   __raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE +
+   PERI_CLKCTL));
+   rate *= i;
+
+   spin_lock_irqsave(clockfw_lock, flags);
+   if (ret == 0) {
+   if (clk-recalc)
+   clk-rate = clk-recalc(clk);
+   propagate_rate(clk);
+   regval = ~(1  CLOCKOUT2EN);
+   __raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE +
+   PERI_CLKCTL));
+   } else
+   return -EINVAL;
+   spin_unlock_irqrestore(clockfw_lock, flags);
+
+   return ret;
+}
+EXPORT_SYMBOL(clkout2_set_rate);
+
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
unsigned long flags;
@@ -254,7 +317,15 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
u32 v, plldiv;
struct pll_data *pll;
unsigned long rate = clk-rate;
+   struct clk *parent = clk;
+
+   if (clk == NULL || IS_ERR(clk))
+   return -EINVAL;
+   while (parent-parent-parent)
+   parent = parent-parent;
 
+   if (parent == clk)
+   return -EPERM;
/* If this is the PLL base clock, no more calculations needed */
if (clk-pll_data)
return rate;
@@ -262,13 +333,13 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
if (WARN_ON(!clk-parent))
return rate;
 
-   rate = clk-parent-rate;
+   rate = parent-rate;
+
 
/* Otherwise, the parent must be a PLL */
-   if (WARN_ON(!clk-parent-pll_data))
+   if (WARN_ON(!parent-pll_data))
return rate;
-
-   pll = clk-parent-pll_data;
+   pll = parent-pll_data;
 
/* If pre-PLL, source clock is before the multiplier and divider(s) */
if (clk-flags  PRE_PLL)
@@ -286,6 +357,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
 
return rate;
 }
+EXPORT_SYMBOL(clk_sysclk_recalc);
 
 static unsigned long clk_leafclk_recalc(struct clk *clk)
 {
@@ -433,6 +505,39 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int 
prediv,
 }
 EXPORT_SYMBOL(davinci_set_pllrate);
 
+int set_sysclk_rate(struct clk *clk, unsigned long rate)
+{
+   u32 clk_freq_min, clk_freq_max, plldiv;
+   struct pll_data *pll;
+   struct clk *parent = clk;
+
+   while (parent-parent-parent)
+   parent = parent-parent;
+   if (parent == clk)
+   return -EPERM;
+
+   clk_freq_max = parent-rate;
+   pll = parent-pll_data;
+   if (clk-flags  PRE_PLL)
+   clk_freq_max = pll-input_rate;
+
+   if (!clk-div_reg)
+   return -EPERM;
+
+   clk_freq_min = clk_freq_max / 0x20;
+   if ((rate  clk_freq_min) || (rate  clk_freq_max))
+   return -EINVAL;
+
+   plldiv = clk_freq_max / rate ;
+   if ((clk_freq_max % rate)  (rate  1))
+   plldiv--;
+   __raw_writel(plldiv

[PATCH 08/14] drivers: mfd: Kconfig Adding comment to MFD_DAVINCI_VOICECODEC

From: Raffaele Recalcati raffaele.recalc...@bticino.it

It makes more clear the selection.

Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 drivers/mfd/Kconfig |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index dfbd03f..bf584f0 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -54,7 +54,7 @@ config MFD_SH_MOBILE_SDHI
  SuperH Mobile SoCs.
 
 config MFD_DAVINCI_VOICECODEC
-   tristate
+   tristate DaVinci VoiceCodec
select MFD_CORE
 
 config MFD_DM355EVM_MSP
-- 
1.7.0.4

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[PATCH 13/14] davinci: video: davincifb Added operation in order to turn on/off hw in platform management

From: Davide Bonfanti davide.bonfa...@bticino.it

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Racalcati raffaele.recalc...@bticino.it
---
 drivers/video/davincifb.c |   22 ++
 include/video/davincifb.h |   11 +++
 2 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/drivers/video/davincifb.c b/drivers/video/davincifb.c
index dabee4d..2a7b2c9 100644
--- a/drivers/video/davincifb.c
+++ b/drivers/video/davincifb.c
@@ -904,6 +904,19 @@ static int davincifb_pan_display(struct fb_var_screeninfo 
*var,
  */
 static int davincifb_blank(int blank_mode, struct fb_info *info)
 {
+   if (blank_mode == 4) {
+   dm-output_device_config(0);
+   dm-ops-davincifb_power(dm-osd0-info, 0);
+   dm-ops-davincifb_power(dm-osd1-info, 0);
+   dm-ops-davincifb_power(dm-vid0-info, 0);
+   dm-ops-davincifb_power(dm-vid1-info, 0);
+   } else if (!blank_mode) {
+   dm-output_device_config(1);
+   dm-ops-davincifb_power(dm-osd0-info, 1);
+   dm-ops-davincifb_power(dm-osd1-info, 1);
+   dm-ops-davincifb_power(dm-vid0-info, 1);
+   dm-ops-davincifb_power(dm-vid1-info, 1);
+   }
return 0;
 }
 
@@ -1416,6 +1429,10 @@ static int davincifb_remove(struct platform_device *pdev)
 
/* Turn OFF the output device */
dm-output_device_config(0);
+   dm-ops-davincifb_power(dm-osd0-info, 0);
+   dm-ops-davincifb_power(dm-osd1-info, 0);
+   dm-ops-davincifb_power(dm-vid0-info, 0);
+   dm-ops-davincifb_power(dm-vid1-info, 0);
 
if (dm-mmio_base)
iounmap((void *)dm-mmio_base);
@@ -1445,6 +1462,7 @@ static int davincifb_probe(struct platform_device *pdev)
}
 
pdata = pdev-dev.platform_data;
+   dm-ops = pdata-ops;
/* map the regions */
dm-mmio_base =
(unsigned long)ioremap(dm-mmio_base_phys, dm-mmio_size);
@@ -1676,6 +1694,10 @@ static int davincifb_probe(struct platform_device *pdev)
 
/* Turn ON the output device */
dm-output_device_config(1);
+   dm-ops-davincifb_power(dm-osd0-info, 1);
+   dm-ops-davincifb_power(dm-osd1-info, 1);
+   dm-ops-davincifb_power(dm-vid0-info, 1);
+   dm-ops-davincifb_power(dm-vid1-info, 1);
 
return (0);
 
diff --git a/include/video/davincifb.h b/include/video/davincifb.h
index 7e4f216..c3ecdd8 100644
--- a/include/video/davincifb.h
+++ b/include/video/davincifb.h
@@ -439,6 +439,17 @@ struct zoom_params
 };
 #define FBIO_SETZOOM   _IOW('F', 0x24, struct zoom_params)
 
+/*
+ * davincifb operations
+ *
+ * This functions are used in order to manage external hw that is platform
+ * dependent according to what is done on the framebuffer (turn LCD on/off,
+ * manage backlight, ...)
+ */
+
+struct davincifb_ops {
+   int (*davincifb_power)(struct fb_info *info, int on);
+};
 
 struct davincifb_platform_data {
u32 xres;
-- 
1.7.0.4

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[PATCH 14/14] davinci: video: davincifb Parallel RBG LCD management

From: Davide Bonfanti davide.bonfa...@bticino.it

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
---
 drivers/video/davincifb.c |  167 +
 include/video/davincifb.h |   17 -
 2 files changed, 165 insertions(+), 19 deletions(-)

diff --git a/drivers/video/davincifb.c b/drivers/video/davincifb.c
index 2a7b2c9..24d1424 100644
--- a/drivers/video/davincifb.c
+++ b/drivers/video/davincifb.c
@@ -29,12 +29,15 @@
 #include linux/interrupt.h
 #include linux/platform_device.h
 
+#include media/davinci/vpss.h
 #include asm/irq.h
 #include asm/uaccess.h
 
 #include video/davincifb.h
 #include asm/system.h
 
+#include mach/dm365.h
+#include mach/cputype.h
 #define MODULE_NAME davincifb
 
 /* Output Format Selection  */
@@ -286,6 +289,10 @@ static irqreturn_t davincifb_isr(int irq, void *arg)
 dm-vid1-info.fix.line_length);
dm-vid1-sdram_address = 0;
}
+   if (dm-osd0-info.var.vmode == FB_VMODE_NONINTERLACED) {
+   ++dm-vsync_cnt;
+   wake_up_interruptible(dm-vsync_wait);
+   }
return IRQ_HANDLED;
} else {
++dm-vsync_cnt;
@@ -631,21 +638,29 @@ static void set_sdram_params(char *id, u32 addr, u32 
line_length)
/* The parameters to be written to the registers should be in
 * multiple of 32 bytes
 */
-   addr = addr;/* div by 32 */
-   line_length = line_length / 32;
+   addr = (addr - DAVINCI_DDR_BASE)  5;  /* div by 32 */
+   line_length = line_length  5;
 
if (is_win(id, VID0)) {
-   dispc_reg_out(OSD_VIDWIN0ADR, addr);
-   dispc_reg_out(OSD_VIDWIN0OFST, line_length);
+   dispc_reg_out(OSD_VIDWIN0ADR, addr  0x);
+   dispc_reg_merge(OSD_VIDWINADH, (addr  0x7F)  16, 0x7F);
+   dispc_reg_out(OSD_VIDWIN0OFST, line_length | 0x1000);
+   /* From docs it's not clear why bit12 is needed */
} else if (is_win(id, VID1)) {
-   dispc_reg_out(OSD_VIDWIN1ADR, addr);
-   dispc_reg_out(OSD_VIDWIN1OFST, line_length);
+   dispc_reg_out(OSD_VIDWIN1ADR, addr  0x);
+   dispc_reg_merge(OSD_VIDWINADH, (addr  0x7F)  8, 0x7F00);
+   dispc_reg_out(OSD_VIDWIN1OFST, line_length | 0x1000);
+   /* From docs it's not clear why bit12 is needed */
} else if (is_win(id, OSD0)) {
-   dispc_reg_out(OSD_OSDWIN0ADR, addr);
-   dispc_reg_out(OSD_OSDWIN0OFST, line_length);
+   dispc_reg_out(OSD_OSDWIN0ADR, addr  0x);
+   dispc_reg_out(OSD_OSDWIN0OFST, line_length | 0x1000);
+   dispc_reg_merge(OSD_OSDWINADH, (addr  0x7F)  16, 0x7F);
+   /* From docs it's not clear why bit12 is needed */
} else if (is_win(id, OSD1)) {
-   dispc_reg_out(OSD_OSDWIN1ADR, addr);
-   dispc_reg_out(OSD_OSDWIN1OFST, line_length);
+   dispc_reg_out(OSD_OSDWIN1ADR, addr  0x);
+   dispc_reg_merge(OSD_OSDWINADH, (addr  0x7F)  8, 0x7F00);
+   dispc_reg_out(OSD_OSDWIN1OFST, line_length | 0x1000);
+   /* From docs it's not clear why bit12 is needed */
}
 }
 
@@ -980,14 +995,12 @@ int __init davincifb_setup(char *options)
if (!strncmp(this_opt, output=, 7)) {
if (!strncmp(this_opt + 7, lcd, 3)) {
dmparams.output = LCD;
-   dmparams.format = 0;
+   dmparams.format = RGB;
} else if (!strncmp(this_opt + 7, ntsc, 4))
dmparams.output = NTSC;
else if (!strncmp(this_opt + 7, pal, 3))
dmparams.output = PAL;
} else if (!strncmp(this_opt, format=, 7)) {
-   if (dmparams.output == LCD)
-   continue;
if (!strncmp(this_opt + 7, composite, 9))
dmparams.format = COMPOSITE;
else if (!strncmp(this_opt + 7, s-video, 7))
@@ -1060,7 +1073,9 @@ int __init davincifb_setup(char *options)
format_yres = 480;
} else if (dmparams.output == PAL) {
format_yres = 576;
-   } else {
+   } else if (dmparams.output == LCD)
+   format_yres = dmparams.osd0_yres;
+   else {
printk(KERN_INFO
   DaVinci:invalid format..defaulting width to 480\n);
}
@@ -1180,7 +1195,10 @@ static struct fb_info *init_fb_info(struct dm_win_info 
*w,
struct dm_info *dm = w-dm;
 
/* initialize the fb_info structure */
-   info-flags = FBINFO_DEFAULT;
+

[PATCH 07/14] davinci: dm365: Fix UART0,1 register addresses

From: Davide Bonfanti davide.bonfa...@bticino.it

Signed-off-by: Davide Bonfanti davide.bonfa...@bticino.it
Signed-off-by: Raffaele Recalcati raffaele.recalc...@bticino.it
---
 arch/arm/mach-davinci/dm365.c   |4 ++--
 arch/arm/mach-davinci/include/mach/serial.h |3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 42fd4a4..e4ead0a 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1024,7 +1024,7 @@ static struct davinci_timer_info dm365_timer_info = {
 
 static struct plat_serial8250_port dm365_serial_platform_data[] = {
{
-   .mapbase= DAVINCI_UART0_BASE,
+   .mapbase= DM365_UART0_BASE,
.irq= IRQ_UARTINT0,
.flags  = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  UPF_IOREMAP,
@@ -1032,7 +1032,7 @@ static struct plat_serial8250_port 
dm365_serial_platform_data[] = {
.regshift   = 2,
},
{
-   .mapbase= DAVINCI_UART1_BASE,
+   .mapbase= DM365_UART1_BASE,
.irq= IRQ_UARTINT1,
.flags  = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  UPF_IOREMAP,
diff --git a/arch/arm/mach-davinci/include/mach/serial.h 
b/arch/arm/mach-davinci/include/mach/serial.h
index f6c4f34..dd69cd3 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -17,6 +17,9 @@
 #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
 
+#define DM365_UART0_BASE   0x01C2
+#define DM365_UART1_BASE   0x01D06000
+
 #define DA8XX_UART0_BASE   (IO_PHYS + 0x042000)
 #define DA8XX_UART1_BASE   (IO_PHYS + 0x10c000)
 #define DA8XX_UART2_BASE   (IO_PHYS + 0x10d000)
-- 
1.7.0.4

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[PATCH 12/14] davinci: video: davincifb import fb parameters from platform data