Re: Better FPGA support on NuttX //was Re: [OT] Projects for GSoC 2024

[Victor Suarez Rovere]

Hi Andrew
I'm aware of that development, the idea is to expand them.
I wrote C and micropython drivers for many FPGA-implemented peripherals,
including high resolution graphics, USB mouse/keyboard, audio, etc.
The idea is to maintain that and to support as much peripherals/boards as
possible



On Wed, Feb 28, 2024 at 7:00 AM Andrew Dennison <
andrew.denni...@motec.com.au> wrote:

> There is a litex (https://github.com/enjoy-digital/litex) target for nuttx
> and litex supports generating a soc for many fpga Dev boards. While the
> nuttx docs focus on using diligent arty, none of this is arty specific.
>
> We are actively moving the litex support forward, with both flat and kernel
> targets available and there are an expanding list of drivers for litex
> peripherals.
>
> On Tue, 20 Feb 2024, 12:35 pm Victor Suarez Rovere, <
> suarezvic...@gmail.com>
> wrote:
>
> > Reference to cheap FPGA boards (< $20) were added to the new repo, more
> > docs will follow there: https://github.com/cederom/nuttx-fpga
> > So, FPGA is not strictly related to $$$
> >
>
> --
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>
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> Croydon South 3136
> Victoria Australia
> *T: *61 3 9761 5050
> *W: *www.motec.com.au 
>
>
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>  
> 
> 
> 
>
>
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>  
>
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> and
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Re: Better FPGA support on NuttX //was Re: [OT] Projects for GSoC 2024

[Andrew Dennison]

There is a litex (https://github.com/enjoy-digital/litex) target for nuttx
and litex supports generating a soc for many fpga Dev boards. While the
nuttx docs focus on using diligent arty, none of this is arty specific.

We are actively moving the litex support forward, with both flat and kernel
targets available and there are an expanding list of drivers for litex
peripherals.

On Tue, 20 Feb 2024, 12:35 pm Victor Suarez Rovere, 
wrote:

> Reference to cheap FPGA boards (< $20) were added to the new repo, more
> docs will follow there: https://github.com/cederom/nuttx-fpga
> So, FPGA is not strictly related to $$$
>

-- 
*MoTeC Pty Ltd*

121 Merrindale Drive
Croydon South 3136
Victoria Australia
*T: *61 3 9761 5050
*W: *www.motec.com.au 


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Disclaimer Notice: This message, including any attachments, contains 
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is protected by law. If you are not the intended recipient you should 
delete this message. Any disclosure, copying, or distribution of this 
message or the taking of any action based on it is strictly prohibited.

Re: Better FPGA support on NuttX //was Re: [OT] Projects for GSoC 2024

[Victor Suarez Rovere]

You have many options for LED control and some of them are not small...
The colorlight i9 has a 45K device that's medium size in my view
then you have the ones that were used for bitcoin mining that have large
devices like the Zynq models, and are super cheap nowadays since those
boards were superseded by ASICs and nobody want them


On Tue, Feb 20, 2024 at 1:21 PM Alan C. Assis  wrote:

> Hi Victor, thank you very much for this information and this link.
>
> I found a nice project using that board:
>
> https://github.com/lucysrausch/colorlight-led-cube
>
> I remember also seeing some FPGA board to control LEDs panel that
> could be used as ordinary FPGA dev tool. But I think these boards
> don't have much LE internally, right?
>
> Best Regards,
>
> Alan
>
> On 2/19/24, Victor Suarez Rovere  wrote:
> > Reference to cheap FPGA boards (< $20) were added to the new repo, more
> > docs will follow there: https://github.com/cederom/nuttx-fpga
> > So, FPGA is not strictly related to $$$
> >
>

Re: Better FPGA support on NuttX //was Re: [OT] Projects for GSoC 2024

[Alan C. Assis]

Hi Victor, thank you very much for this information and this link.

I found a nice project using that board:

https://github.com/lucysrausch/colorlight-led-cube

I remember also seeing some FPGA board to control LEDs panel that
could be used as ordinary FPGA dev tool. But I think these boards
don't have much LE internally, right?

Best Regards,

Alan

On 2/19/24, Victor Suarez Rovere  wrote:
> Reference to cheap FPGA boards (< $20) were added to the new repo, more
> docs will follow there: https://github.com/cederom/nuttx-fpga
> So, FPGA is not strictly related to $$$
>

Re: Better FPGA support on NuttX //was Re: [OT] Projects for GSoC 2024

[Victor Suarez Rovere]

Reference to cheap FPGA boards (< $20) were added to the new repo, more
docs will follow there: https://github.com/cederom/nuttx-fpga
So, FPGA is not strictly related to $$$

Re: [OT] Projects for GSoC 2024

[Victor Suarez Rovere]

FPGA development boards are indeed not cheap, as the chips themselves are
expensive. But those of us who are in the field know some solutions. Indeed
I'm working on designing a low cost FPGA board right now.
Until mine is ready, a useful alternative is to reuse some mass marketed
products that are cheap, like LED controllers boards. This one for example
cost $11.50 and includes SDRAM and ethernet:

https://www.ledcontrollercard.com/english/colorlight-n6-led-mini-receiving-card.html

Best,
Victor

Re: [OT] Projects for GSoC 2024

[Tomek CEDRO]

Okay, this may be too complex and too early, true I also had lots of
issues and was not able to work on my FreeBSD with Open-Source only
tools, lets start step by step from simple things first then more
complex ones, will try again with NuttX+FPGA funding next round, thank
you guys, I will be in touch with Victor he does amazing things with
FPGA it would be really nice to have him in our team :-)

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

On Mon, Feb 19, 2024 at 5:09 PM Alan C. Assis  wrote:
>
> Hi Victor,
>
> Yes, as I said before I also think this is a very important field, but at
> least for this chinese board I realized that things are not there yet.
>
> Maybe using a Lattice FPGA could work better, but anyway, a good FPGA board
> to run a RISC-V is not too low cost.
>
> Tang Primer 20K is lower cost, but the open-source tools are not that great.
>
> I found a good discussion here:
> https://www.reddit.com/r/RISCV/comments/z9v6f8/which_fpga_for_getting_into_riscv/
>
> Someone suggested ULX3S as a good board to work with open-source tools, but
> the board version with Lattice ECP5 85F costs more than U$ 300 on
> Aliexpress.
>
> That is not a low cost for someone that just wants to try an FPGA.
>
> Best Regards,
>
> Alan
>
> On Mon, Feb 19, 2024 at 12:08 PM Victor Suarez Rovere <
> suarezvic...@gmail.com> wrote:
>
> > Hi
> > I have experience doing FPGA development including graphics (micropython
> > port, ImGUI port, USB mouse/keyboard etc.)
> > I think the open-source tool ecosystem for FPGA development is mature
> > enough not to depend on proprietary tools and IP, mainly related to Lattice
> > devices but also for most Xilinx devices.
> > And I fully agree with what Tomek said in every aspect with regards to the
> > convenience of mailined FPGA support.
> >
> > Best,
> > Victor.
> >
> >
> >
> > On Mon, Feb 19, 2024 at 11:50 AM Alan C. Assis  wrote:
> >
> > > No, as we pointed out, it is a long term project that needs to be well
> > > thought out.
> > >
> > > You listed many possibilities, we need to define a goal and focus on it.
> > >
> > > Let me share my (bad) experience with FPGA:
> > > Sometime ago I bought a low cost Tang Primer 20K board expecting to start
> > > using open-source tools to program it (many places said it was
> > supported).
> > >
> > > Then when I installed the software I discovered that I need to download
> > the
> > > proprietary SDK and copy many files from it to get things working.
> > >
> > > It was a show stopper for me!
> > >
> > > Imagine if you wanted to compile NuttX and had to download the vendor SDK
> > > and copy their files to inside NuttX.
> > >
> > > Best Regards,
> > >
> > > Alan
> > >
> > > On Sun, Feb 18, 2024 at 8:02 PM Tomek CEDRO  wrote:
> > >
> > > > Closed, okay, and the FPGA part did not get in?
> > > >
> > > > --
> > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > > >
> > > > On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis 
> > > wrote:
> > > > >
> > > > > Hi Tomek,
> > > > > Thank you for raising these concerns.
> > > > >
> > > > > BTW, I suggest you change the Subject to something related to NuttX
> > and
> > > > > FPGA, since the GSoC 2024 proposal is already closed (on Feb 6).
> > > > >
> > > > > Best Regards,
> > > > >
> > > > > Alan
> > > > >
> > > > > On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO 
> > wrote:
> > > > >
> > > > > > After some more considerations I am pro this "generic" NuttX@FPGA
> > > > > > Reference Design on GSoC proposal, 10 resons below :-)
> > > > > >
> > > > > > I kindly ask to add this one to the proposals list :-)
> > > > > >
> > > > > > 1. We do not have a reference FPGA design for NuttX.
> > > > > > 2. We do not have a reference fully Open-Source toolchain for
> > > > FPGA+NuttX.
> > > > > > 3. Yes someone did that before, and anyone can do that, but we can
> > > > > > provide generic out-of-the-box solution that most people are
> > looking
> > > > > > for. Creating / repeating one yourself costs time.
> > > > > > 4. We can gather smart community around NuttX that way (i.e.
> > Victor).
> > > > > > 5. FPGA are getting smaller and cheaper close to a price range of
> > MCU
> > > > > > (i.e. $5+) [1][2].
> > > > > > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO
> > > > > > nMHz vs nnnMHz). I can see unique benefit for having custom
> > > > > > peripherals created that way. I once did an R on new type of ADC
> > > > > > where MCU GPIO was not fast enough and I have to switch to FPGA +
> > > > > > external control MCU board.
> > > > > > 7. Using propietary tools was quite painful because I had to use
> > big
> > > > > > Xilinx Vivado while there are fully Open-Source toolchains already
> > > out
> > > > > > there we can use like Yosys / OSS CAD Suite [3] etc.
> > > > > > 8. Scaling to bigger FPGA gives more possibilities like new
> > > > > > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of
> > cores)
> > > > > > [4], emulation [5], machine learning, etc.
> > > > > > 9. My initial 

Better FPGA support on NuttX //was Re: [OT] Projects for GSoC 2024

[Alan C. Assis]

Let's follow the discussion here to avoid polluting the previous thread.

On 2/18/24, Tomek CEDRO  wrote:
> Closed, okay, and the FPGA part did not get in?
>
> --
> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
>
> On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis  wrote:
>>
>> Hi Tomek,
>> Thank you for raising these concerns.
>>
>> BTW, I suggest you change the Subject to something related to NuttX and
>> FPGA, since the GSoC 2024 proposal is already closed (on Feb 6).
>>
>> Best Regards,
>>
>> Alan
>>
>> On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO  wrote:
>>
>> > After some more considerations I am pro this "generic" NuttX@FPGA
>> > Reference Design on GSoC proposal, 10 resons below :-)
>> >
>> > I kindly ask to add this one to the proposals list :-)
>> >
>> > 1. We do not have a reference FPGA design for NuttX.
>> > 2. We do not have a reference fully Open-Source toolchain for
>> > FPGA+NuttX.
>> > 3. Yes someone did that before, and anyone can do that, but we can
>> > provide generic out-of-the-box solution that most people are looking
>> > for. Creating / repeating one yourself costs time.
>> > 4. We can gather smart community around NuttX that way (i.e. Victor).
>> > 5. FPGA are getting smaller and cheaper close to a price range of MCU
>> > (i.e. $5+) [1][2].
>> > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO
>> > nMHz vs nnnMHz). I can see unique benefit for having custom
>> > peripherals created that way. I once did an R on new type of ADC
>> > where MCU GPIO was not fast enough and I have to switch to FPGA +
>> > external control MCU board.
>> > 7. Using propietary tools was quite painful because I had to use big
>> > Xilinx Vivado while there are fully Open-Source toolchains already out
>> > there we can use like Yosys / OSS CAD Suite [3] etc.
>> > 8. Scaling to bigger FPGA gives more possibilities like new
>> > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores)
>> > [4], emulation [5], machine learning, etc.
>> > 9. My initial proposal was highly experimental and could easily fail.
>> > Victor's proposal is merit and result based. It will for sure serve
>> > many people out there for bigger and smaller projects.
>> > 10. Other ideas like Xorg port could be tested on FPGA implementation
>> > too.. I already saw Victor's working windows manager with
>> > chip-mod-player running on FPGA :-)
>> >
>> > I can be mentor of that project because I would like to grow in that
>> > field too as I have some ideas to test :-)
>> >
>> > Thanks for considering :-)
>> > Tomek
>> >
>> > [1] https://tinyfpga.com/
>> > [2]
>> > https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/
>> > [3] https://github.com/YosysHQ/oss-cad-suite-build
>> > [4]
>> > https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/
>> > [5] https://www.retrorgb.com/mister.html
>> >
>> > --
>> > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
>> >
>> > On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere
>> >  wrote:
>> > >
>> > > The innovation won't be to run NuttX in a RISC-V (soft-core or not)
>> > > but
>> > > using a FPGA for its flexibility to add any kind of peripherals, one
>> > > of
>> > the
>> > > main ones to be useful in my view will be a high-resolution
>> > > framebuffer
>> > and
>> > > USB mouse/keyboard for a complete UI
>> > >
>> > > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt 
>> > wrote:
>> > >
>> > > > Aren't most CPUs available as soft cores?  Certainly Xtensa was
>> > intended
>> > > > for that purpose.  ARM and MIPS have been common soft cores in
>> > > > ASICs
>> > for
>> > > > more than a decade. As is RISC-V soft core in FPGAs.
>> > > > https://en.wikipedia.org/wiki/Soft_microprocessor
>> > > >
>> > > > In the past, there was some interest in ports of NuttX to
>> > > > softcore's
>> > > > like MicroBlaze.  But there hasn't been that kind of interest in
>> > > > recent
>> > > > times.
>> > > >
>> > > > This would have been an innovation a decade or so ago, but I wonder
>> > > > about that now.
>> > > >
>> > > >
>> > > >
>> > > > On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote:
>> > > > > Tomek, as I clarified, porting NuttX to a FPGA will require a
>> > soft-core
>> > > > > CPU. I don't envision an opertaing system without a CPU, I see
>> > > > > that
>> > like
>> > > > a
>> > > > > bad design choice if possible at all
>> > > > > Using a soft core and custom peripherals seems more valuable,
>> > > > > even
>> > > > > including video output and USB host for mouse/keyboard handling.
>> > > > > I've
>> > > > done
>> > > > > that for Micropython
>> > > > >
>> > > > > El sáb., 27 ene. 2024 13:23, Tomek CEDRO 
>> > escribió:
>> > > > >
>> > > > >> Okay Victor, I was thinking about toolchain that you present in
>> > > > >> "Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA
>> > > > >> conversion
>> > > > >> without a CPU design.. could you please send your full detailed
>> > > 

Re: [OT] Projects for GSoC 2024

[Alan C. Assis]

Hi Victor,

Yes, as I said before I also think this is a very important field, but at
least for this chinese board I realized that things are not there yet.

Maybe using a Lattice FPGA could work better, but anyway, a good FPGA board
to run a RISC-V is not too low cost.

Tang Primer 20K is lower cost, but the open-source tools are not that great.

I found a good discussion here:
https://www.reddit.com/r/RISCV/comments/z9v6f8/which_fpga_for_getting_into_riscv/

Someone suggested ULX3S as a good board to work with open-source tools, but
the board version with Lattice ECP5 85F costs more than U$ 300 on
Aliexpress.

That is not a low cost for someone that just wants to try an FPGA.

Best Regards,

Alan

On Mon, Feb 19, 2024 at 12:08 PM Victor Suarez Rovere <
suarezvic...@gmail.com> wrote:

> Hi
> I have experience doing FPGA development including graphics (micropython
> port, ImGUI port, USB mouse/keyboard etc.)
> I think the open-source tool ecosystem for FPGA development is mature
> enough not to depend on proprietary tools and IP, mainly related to Lattice
> devices but also for most Xilinx devices.
> And I fully agree with what Tomek said in every aspect with regards to the
> convenience of mailined FPGA support.
>
> Best,
> Victor.
>
>
>
> On Mon, Feb 19, 2024 at 11:50 AM Alan C. Assis  wrote:
>
> > No, as we pointed out, it is a long term project that needs to be well
> > thought out.
> >
> > You listed many possibilities, we need to define a goal and focus on it.
> >
> > Let me share my (bad) experience with FPGA:
> > Sometime ago I bought a low cost Tang Primer 20K board expecting to start
> > using open-source tools to program it (many places said it was
> supported).
> >
> > Then when I installed the software I discovered that I need to download
> the
> > proprietary SDK and copy many files from it to get things working.
> >
> > It was a show stopper for me!
> >
> > Imagine if you wanted to compile NuttX and had to download the vendor SDK
> > and copy their files to inside NuttX.
> >
> > Best Regards,
> >
> > Alan
> >
> > On Sun, Feb 18, 2024 at 8:02 PM Tomek CEDRO  wrote:
> >
> > > Closed, okay, and the FPGA part did not get in?
> > >
> > > --
> > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > >
> > > On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis 
> > wrote:
> > > >
> > > > Hi Tomek,
> > > > Thank you for raising these concerns.
> > > >
> > > > BTW, I suggest you change the Subject to something related to NuttX
> and
> > > > FPGA, since the GSoC 2024 proposal is already closed (on Feb 6).
> > > >
> > > > Best Regards,
> > > >
> > > > Alan
> > > >
> > > > On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO 
> wrote:
> > > >
> > > > > After some more considerations I am pro this "generic" NuttX@FPGA
> > > > > Reference Design on GSoC proposal, 10 resons below :-)
> > > > >
> > > > > I kindly ask to add this one to the proposals list :-)
> > > > >
> > > > > 1. We do not have a reference FPGA design for NuttX.
> > > > > 2. We do not have a reference fully Open-Source toolchain for
> > > FPGA+NuttX.
> > > > > 3. Yes someone did that before, and anyone can do that, but we can
> > > > > provide generic out-of-the-box solution that most people are
> looking
> > > > > for. Creating / repeating one yourself costs time.
> > > > > 4. We can gather smart community around NuttX that way (i.e.
> Victor).
> > > > > 5. FPGA are getting smaller and cheaper close to a price range of
> MCU
> > > > > (i.e. $5+) [1][2].
> > > > > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO
> > > > > nMHz vs nnnMHz). I can see unique benefit for having custom
> > > > > peripherals created that way. I once did an R on new type of ADC
> > > > > where MCU GPIO was not fast enough and I have to switch to FPGA +
> > > > > external control MCU board.
> > > > > 7. Using propietary tools was quite painful because I had to use
> big
> > > > > Xilinx Vivado while there are fully Open-Source toolchains already
> > out
> > > > > there we can use like Yosys / OSS CAD Suite [3] etc.
> > > > > 8. Scaling to bigger FPGA gives more possibilities like new
> > > > > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of
> cores)
> > > > > [4], emulation [5], machine learning, etc.
> > > > > 9. My initial proposal was highly experimental and could easily
> fail.
> > > > > Victor's proposal is merit and result based. It will for sure serve
> > > > > many people out there for bigger and smaller projects.
> > > > > 10. Other ideas like Xorg port could be tested on FPGA
> implementation
> > > > > too.. I already saw Victor's working windows manager with
> > > > > chip-mod-player running on FPGA :-)
> > > > >
> > > > > I can be mentor of that project because I would like to grow in
> that
> > > > > field too as I have some ideas to test :-)
> > > > >
> > > > > Thanks for considering :-)
> > > > > Tomek
> > > > >
> > > > > [1] https://tinyfpga.com/
> > > > > [2]
> > > > >
> > >
> >
> 

Re: [OT] Projects for GSoC 2024

[Victor Suarez Rovere]

Hi
I have experience doing FPGA development including graphics (micropython
port, ImGUI port, USB mouse/keyboard etc.)
I think the open-source tool ecosystem for FPGA development is mature
enough not to depend on proprietary tools and IP, mainly related to Lattice
devices but also for most Xilinx devices.
And I fully agree with what Tomek said in every aspect with regards to the
convenience of mailined FPGA support.

Best,
Victor.



On Mon, Feb 19, 2024 at 11:50 AM Alan C. Assis  wrote:

> No, as we pointed out, it is a long term project that needs to be well
> thought out.
>
> You listed many possibilities, we need to define a goal and focus on it.
>
> Let me share my (bad) experience with FPGA:
> Sometime ago I bought a low cost Tang Primer 20K board expecting to start
> using open-source tools to program it (many places said it was supported).
>
> Then when I installed the software I discovered that I need to download the
> proprietary SDK and copy many files from it to get things working.
>
> It was a show stopper for me!
>
> Imagine if you wanted to compile NuttX and had to download the vendor SDK
> and copy their files to inside NuttX.
>
> Best Regards,
>
> Alan
>
> On Sun, Feb 18, 2024 at 8:02 PM Tomek CEDRO  wrote:
>
> > Closed, okay, and the FPGA part did not get in?
> >
> > --
> > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> >
> > On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis 
> wrote:
> > >
> > > Hi Tomek,
> > > Thank you for raising these concerns.
> > >
> > > BTW, I suggest you change the Subject to something related to NuttX and
> > > FPGA, since the GSoC 2024 proposal is already closed (on Feb 6).
> > >
> > > Best Regards,
> > >
> > > Alan
> > >
> > > On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO  wrote:
> > >
> > > > After some more considerations I am pro this "generic" NuttX@FPGA
> > > > Reference Design on GSoC proposal, 10 resons below :-)
> > > >
> > > > I kindly ask to add this one to the proposals list :-)
> > > >
> > > > 1. We do not have a reference FPGA design for NuttX.
> > > > 2. We do not have a reference fully Open-Source toolchain for
> > FPGA+NuttX.
> > > > 3. Yes someone did that before, and anyone can do that, but we can
> > > > provide generic out-of-the-box solution that most people are looking
> > > > for. Creating / repeating one yourself costs time.
> > > > 4. We can gather smart community around NuttX that way (i.e. Victor).
> > > > 5. FPGA are getting smaller and cheaper close to a price range of MCU
> > > > (i.e. $5+) [1][2].
> > > > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO
> > > > nMHz vs nnnMHz). I can see unique benefit for having custom
> > > > peripherals created that way. I once did an R on new type of ADC
> > > > where MCU GPIO was not fast enough and I have to switch to FPGA +
> > > > external control MCU board.
> > > > 7. Using propietary tools was quite painful because I had to use big
> > > > Xilinx Vivado while there are fully Open-Source toolchains already
> out
> > > > there we can use like Yosys / OSS CAD Suite [3] etc.
> > > > 8. Scaling to bigger FPGA gives more possibilities like new
> > > > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores)
> > > > [4], emulation [5], machine learning, etc.
> > > > 9. My initial proposal was highly experimental and could easily fail.
> > > > Victor's proposal is merit and result based. It will for sure serve
> > > > many people out there for bigger and smaller projects.
> > > > 10. Other ideas like Xorg port could be tested on FPGA implementation
> > > > too.. I already saw Victor's working windows manager with
> > > > chip-mod-player running on FPGA :-)
> > > >
> > > > I can be mentor of that project because I would like to grow in that
> > > > field too as I have some ideas to test :-)
> > > >
> > > > Thanks for considering :-)
> > > > Tomek
> > > >
> > > > [1] https://tinyfpga.com/
> > > > [2]
> > > >
> >
> https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/
> > > > [3] https://github.com/YosysHQ/oss-cad-suite-build
> > > > [4]
> > > >
> >
> https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/
> > > > [5] https://www.retrorgb.com/mister.html
> > > >
> > > > --
> > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > > >
> > > > On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere
> > > >  wrote:
> > > > >
> > > > > The innovation won't be to run NuttX in a RISC-V (soft-core or not)
> > but
> > > > > using a FPGA for its flexibility to add any kind of peripherals,
> one
> > of
> > > > the
> > > > > main ones to be useful in my view will be a high-resolution
> > framebuffer
> > > > and
> > > > > USB mouse/keyboard for a complete UI
> > > > >
> > > > > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt 
> > > > wrote:
> > > > >
> > > > > > Aren't most CPUs available as soft cores?  Certainly Xtensa was
> > > > intended
> > > > > > for that purpose.  ARM and 

Re: [OT] Projects for GSoC 2024

[Alan C. Assis]

Tomek,

The list with all GSoC 2024 from Apache Foundation is here:

https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list

Until now we have two contributors interested in participating, but we
proposed 6 projects.

Best Regards,

Alan

On Sun, Feb 18, 2024 at 8:02 PM Tomek CEDRO  wrote:

> Closed, okay, and the FPGA part did not get in?
>
> --
> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
>
> On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis  wrote:
> >
> > Hi Tomek,
> > Thank you for raising these concerns.
> >
> > BTW, I suggest you change the Subject to something related to NuttX and
> > FPGA, since the GSoC 2024 proposal is already closed (on Feb 6).
> >
> > Best Regards,
> >
> > Alan
> >
> > On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO  wrote:
> >
> > > After some more considerations I am pro this "generic" NuttX@FPGA
> > > Reference Design on GSoC proposal, 10 resons below :-)
> > >
> > > I kindly ask to add this one to the proposals list :-)
> > >
> > > 1. We do not have a reference FPGA design for NuttX.
> > > 2. We do not have a reference fully Open-Source toolchain for
> FPGA+NuttX.
> > > 3. Yes someone did that before, and anyone can do that, but we can
> > > provide generic out-of-the-box solution that most people are looking
> > > for. Creating / repeating one yourself costs time.
> > > 4. We can gather smart community around NuttX that way (i.e. Victor).
> > > 5. FPGA are getting smaller and cheaper close to a price range of MCU
> > > (i.e. $5+) [1][2].
> > > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO
> > > nMHz vs nnnMHz). I can see unique benefit for having custom
> > > peripherals created that way. I once did an R on new type of ADC
> > > where MCU GPIO was not fast enough and I have to switch to FPGA +
> > > external control MCU board.
> > > 7. Using propietary tools was quite painful because I had to use big
> > > Xilinx Vivado while there are fully Open-Source toolchains already out
> > > there we can use like Yosys / OSS CAD Suite [3] etc.
> > > 8. Scaling to bigger FPGA gives more possibilities like new
> > > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores)
> > > [4], emulation [5], machine learning, etc.
> > > 9. My initial proposal was highly experimental and could easily fail.
> > > Victor's proposal is merit and result based. It will for sure serve
> > > many people out there for bigger and smaller projects.
> > > 10. Other ideas like Xorg port could be tested on FPGA implementation
> > > too.. I already saw Victor's working windows manager with
> > > chip-mod-player running on FPGA :-)
> > >
> > > I can be mentor of that project because I would like to grow in that
> > > field too as I have some ideas to test :-)
> > >
> > > Thanks for considering :-)
> > > Tomek
> > >
> > > [1] https://tinyfpga.com/
> > > [2]
> > >
> https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/
> > > [3] https://github.com/YosysHQ/oss-cad-suite-build
> > > [4]
> > >
> https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/
> > > [5] https://www.retrorgb.com/mister.html
> > >
> > > --
> > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > >
> > > On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere
> > >  wrote:
> > > >
> > > > The innovation won't be to run NuttX in a RISC-V (soft-core or not)
> but
> > > > using a FPGA for its flexibility to add any kind of peripherals, one
> of
> > > the
> > > > main ones to be useful in my view will be a high-resolution
> framebuffer
> > > and
> > > > USB mouse/keyboard for a complete UI
> > > >
> > > > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt 
> > > wrote:
> > > >
> > > > > Aren't most CPUs available as soft cores?  Certainly Xtensa was
> > > intended
> > > > > for that purpose.  ARM and MIPS have been common soft cores in
> ASICs
> > > for
> > > > > more than a decade. As is RISC-V soft core in FPGAs.
> > > > > https://en.wikipedia.org/wiki/Soft_microprocessor
> > > > >
> > > > > In the past, there was some interest in ports of NuttX to
> softcore's
> > > > > like MicroBlaze.  But there hasn't been that kind of interest in
> recent
> > > > > times.
> > > > >
> > > > > This would have been an innovation a decade or so ago, but I wonder
> > > > > about that now.
> > > > >
> > > > >
> > > > >
> > > > > On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote:
> > > > > > Tomek, as I clarified, porting NuttX to a FPGA will require a
> > > soft-core
> > > > > > CPU. I don't envision an opertaing system without a CPU, I see
> that
> > > like
> > > > > a
> > > > > > bad design choice if possible at all
> > > > > > Using a soft core and custom peripherals seems more valuable,
> even
> > > > > > including video output and USB host for mouse/keyboard handling.
> I've
> > > > > done
> > > > > > that for Micropython
> > > > > >
> > > > > > El sáb., 27 ene. 2024 13:23, Tomek CEDRO 
> > > escribió:
> > > > > >
> > 

Re: [OT] Projects for GSoC 2024

[Alan C. Assis]

No, as we pointed out, it is a long term project that needs to be well
thought out.

You listed many possibilities, we need to define a goal and focus on it.

Let me share my (bad) experience with FPGA:
Sometime ago I bought a low cost Tang Primer 20K board expecting to start
using open-source tools to program it (many places said it was supported).

Then when I installed the software I discovered that I need to download the
proprietary SDK and copy many files from it to get things working.

It was a show stopper for me!

Imagine if you wanted to compile NuttX and had to download the vendor SDK
and copy their files to inside NuttX.

Best Regards,

Alan

On Sun, Feb 18, 2024 at 8:02 PM Tomek CEDRO  wrote:

> Closed, okay, and the FPGA part did not get in?
>
> --
> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
>
> On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis  wrote:
> >
> > Hi Tomek,
> > Thank you for raising these concerns.
> >
> > BTW, I suggest you change the Subject to something related to NuttX and
> > FPGA, since the GSoC 2024 proposal is already closed (on Feb 6).
> >
> > Best Regards,
> >
> > Alan
> >
> > On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO  wrote:
> >
> > > After some more considerations I am pro this "generic" NuttX@FPGA
> > > Reference Design on GSoC proposal, 10 resons below :-)
> > >
> > > I kindly ask to add this one to the proposals list :-)
> > >
> > > 1. We do not have a reference FPGA design for NuttX.
> > > 2. We do not have a reference fully Open-Source toolchain for
> FPGA+NuttX.
> > > 3. Yes someone did that before, and anyone can do that, but we can
> > > provide generic out-of-the-box solution that most people are looking
> > > for. Creating / repeating one yourself costs time.
> > > 4. We can gather smart community around NuttX that way (i.e. Victor).
> > > 5. FPGA are getting smaller and cheaper close to a price range of MCU
> > > (i.e. $5+) [1][2].
> > > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO
> > > nMHz vs nnnMHz). I can see unique benefit for having custom
> > > peripherals created that way. I once did an R on new type of ADC
> > > where MCU GPIO was not fast enough and I have to switch to FPGA +
> > > external control MCU board.
> > > 7. Using propietary tools was quite painful because I had to use big
> > > Xilinx Vivado while there are fully Open-Source toolchains already out
> > > there we can use like Yosys / OSS CAD Suite [3] etc.
> > > 8. Scaling to bigger FPGA gives more possibilities like new
> > > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores)
> > > [4], emulation [5], machine learning, etc.
> > > 9. My initial proposal was highly experimental and could easily fail.
> > > Victor's proposal is merit and result based. It will for sure serve
> > > many people out there for bigger and smaller projects.
> > > 10. Other ideas like Xorg port could be tested on FPGA implementation
> > > too.. I already saw Victor's working windows manager with
> > > chip-mod-player running on FPGA :-)
> > >
> > > I can be mentor of that project because I would like to grow in that
> > > field too as I have some ideas to test :-)
> > >
> > > Thanks for considering :-)
> > > Tomek
> > >
> > > [1] https://tinyfpga.com/
> > > [2]
> > >
> https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/
> > > [3] https://github.com/YosysHQ/oss-cad-suite-build
> > > [4]
> > >
> https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/
> > > [5] https://www.retrorgb.com/mister.html
> > >
> > > --
> > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > >
> > > On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere
> > >  wrote:
> > > >
> > > > The innovation won't be to run NuttX in a RISC-V (soft-core or not)
> but
> > > > using a FPGA for its flexibility to add any kind of peripherals, one
> of
> > > the
> > > > main ones to be useful in my view will be a high-resolution
> framebuffer
> > > and
> > > > USB mouse/keyboard for a complete UI
> > > >
> > > > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt 
> > > wrote:
> > > >
> > > > > Aren't most CPUs available as soft cores?  Certainly Xtensa was
> > > intended
> > > > > for that purpose.  ARM and MIPS have been common soft cores in
> ASICs
> > > for
> > > > > more than a decade. As is RISC-V soft core in FPGAs.
> > > > > https://en.wikipedia.org/wiki/Soft_microprocessor
> > > > >
> > > > > In the past, there was some interest in ports of NuttX to
> softcore's
> > > > > like MicroBlaze.  But there hasn't been that kind of interest in
> recent
> > > > > times.
> > > > >
> > > > > This would have been an innovation a decade or so ago, but I wonder
> > > > > about that now.
> > > > >
> > > > >
> > > > >
> > > > > On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote:
> > > > > > Tomek, as I clarified, porting NuttX to a FPGA will require a
> > > soft-core
> > > > > > CPU. I don't envision an opertaing system 

Re: [OT] Projects for GSoC 2024

[Tomek CEDRO]

Closed, okay, and the FPGA part did not get in?

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis  wrote:
>
> Hi Tomek,
> Thank you for raising these concerns.
>
> BTW, I suggest you change the Subject to something related to NuttX and
> FPGA, since the GSoC 2024 proposal is already closed (on Feb 6).
>
> Best Regards,
>
> Alan
>
> On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO  wrote:
>
> > After some more considerations I am pro this "generic" NuttX@FPGA
> > Reference Design on GSoC proposal, 10 resons below :-)
> >
> > I kindly ask to add this one to the proposals list :-)
> >
> > 1. We do not have a reference FPGA design for NuttX.
> > 2. We do not have a reference fully Open-Source toolchain for FPGA+NuttX.
> > 3. Yes someone did that before, and anyone can do that, but we can
> > provide generic out-of-the-box solution that most people are looking
> > for. Creating / repeating one yourself costs time.
> > 4. We can gather smart community around NuttX that way (i.e. Victor).
> > 5. FPGA are getting smaller and cheaper close to a price range of MCU
> > (i.e. $5+) [1][2].
> > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO
> > nMHz vs nnnMHz). I can see unique benefit for having custom
> > peripherals created that way. I once did an R on new type of ADC
> > where MCU GPIO was not fast enough and I have to switch to FPGA +
> > external control MCU board.
> > 7. Using propietary tools was quite painful because I had to use big
> > Xilinx Vivado while there are fully Open-Source toolchains already out
> > there we can use like Yosys / OSS CAD Suite [3] etc.
> > 8. Scaling to bigger FPGA gives more possibilities like new
> > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores)
> > [4], emulation [5], machine learning, etc.
> > 9. My initial proposal was highly experimental and could easily fail.
> > Victor's proposal is merit and result based. It will for sure serve
> > many people out there for bigger and smaller projects.
> > 10. Other ideas like Xorg port could be tested on FPGA implementation
> > too.. I already saw Victor's working windows manager with
> > chip-mod-player running on FPGA :-)
> >
> > I can be mentor of that project because I would like to grow in that
> > field too as I have some ideas to test :-)
> >
> > Thanks for considering :-)
> > Tomek
> >
> > [1] https://tinyfpga.com/
> > [2]
> > https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/
> > [3] https://github.com/YosysHQ/oss-cad-suite-build
> > [4]
> > https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/
> > [5] https://www.retrorgb.com/mister.html
> >
> > --
> > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> >
> > On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere
> >  wrote:
> > >
> > > The innovation won't be to run NuttX in a RISC-V (soft-core or not) but
> > > using a FPGA for its flexibility to add any kind of peripherals, one of
> > the
> > > main ones to be useful in my view will be a high-resolution framebuffer
> > and
> > > USB mouse/keyboard for a complete UI
> > >
> > > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt 
> > wrote:
> > >
> > > > Aren't most CPUs available as soft cores?  Certainly Xtensa was
> > intended
> > > > for that purpose.  ARM and MIPS have been common soft cores in ASICs
> > for
> > > > more than a decade. As is RISC-V soft core in FPGAs.
> > > > https://en.wikipedia.org/wiki/Soft_microprocessor
> > > >
> > > > In the past, there was some interest in ports of NuttX to softcore's
> > > > like MicroBlaze.  But there hasn't been that kind of interest in recent
> > > > times.
> > > >
> > > > This would have been an innovation a decade or so ago, but I wonder
> > > > about that now.
> > > >
> > > >
> > > >
> > > > On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote:
> > > > > Tomek, as I clarified, porting NuttX to a FPGA will require a
> > soft-core
> > > > > CPU. I don't envision an opertaing system without a CPU, I see that
> > like
> > > > a
> > > > > bad design choice if possible at all
> > > > > Using a soft core and custom peripherals seems more valuable, even
> > > > > including video output and USB host for mouse/keyboard handling. I've
> > > > done
> > > > > that for Micropython
> > > > >
> > > > > El sáb., 27 ene. 2024 13:23, Tomek CEDRO 
> > escribió:
> > > > >
> > > > >> Okay Victor, I was thinking about toolchain that you present in
> > > > >> "Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA conversion
> > > > >> without a CPU design.. could you please send your full detailed
> > > > >> proposal then? :-)
> > > > >>
> > > > >> [1] https://www.youtube.com/watch?v=hn3sr3VMJQU
> > > > >>
> > > > >> --
> > > > >> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > > > >>
> > > > >> On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere
> > > > >>  wrote:
> > > > >>> Just clarifying, the idea to run NuttX on 

Re: [OT] Projects for GSoC 2024

[Alan C. Assis]

Hi Tomek,
Thank you for raising these concerns.

BTW, I suggest you change the Subject to something related to NuttX and
FPGA, since the GSoC 2024 proposal is already closed (on Feb 6).

Best Regards,

Alan

On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO  wrote:

> After some more considerations I am pro this "generic" NuttX@FPGA
> Reference Design on GSoC proposal, 10 resons below :-)
>
> I kindly ask to add this one to the proposals list :-)
>
> 1. We do not have a reference FPGA design for NuttX.
> 2. We do not have a reference fully Open-Source toolchain for FPGA+NuttX.
> 3. Yes someone did that before, and anyone can do that, but we can
> provide generic out-of-the-box solution that most people are looking
> for. Creating / repeating one yourself costs time.
> 4. We can gather smart community around NuttX that way (i.e. Victor).
> 5. FPGA are getting smaller and cheaper close to a price range of MCU
> (i.e. $5+) [1][2].
> 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO
> nMHz vs nnnMHz). I can see unique benefit for having custom
> peripherals created that way. I once did an R on new type of ADC
> where MCU GPIO was not fast enough and I have to switch to FPGA +
> external control MCU board.
> 7. Using propietary tools was quite painful because I had to use big
> Xilinx Vivado while there are fully Open-Source toolchains already out
> there we can use like Yosys / OSS CAD Suite [3] etc.
> 8. Scaling to bigger FPGA gives more possibilities like new
> architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores)
> [4], emulation [5], machine learning, etc.
> 9. My initial proposal was highly experimental and could easily fail.
> Victor's proposal is merit and result based. It will for sure serve
> many people out there for bigger and smaller projects.
> 10. Other ideas like Xorg port could be tested on FPGA implementation
> too.. I already saw Victor's working windows manager with
> chip-mod-player running on FPGA :-)
>
> I can be mentor of that project because I would like to grow in that
> field too as I have some ideas to test :-)
>
> Thanks for considering :-)
> Tomek
>
> [1] https://tinyfpga.com/
> [2]
> https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/
> [3] https://github.com/YosysHQ/oss-cad-suite-build
> [4]
> https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/
> [5] https://www.retrorgb.com/mister.html
>
> --
> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
>
> On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere
>  wrote:
> >
> > The innovation won't be to run NuttX in a RISC-V (soft-core or not) but
> > using a FPGA for its flexibility to add any kind of peripherals, one of
> the
> > main ones to be useful in my view will be a high-resolution framebuffer
> and
> > USB mouse/keyboard for a complete UI
> >
> > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt 
> wrote:
> >
> > > Aren't most CPUs available as soft cores?  Certainly Xtensa was
> intended
> > > for that purpose.  ARM and MIPS have been common soft cores in ASICs
> for
> > > more than a decade. As is RISC-V soft core in FPGAs.
> > > https://en.wikipedia.org/wiki/Soft_microprocessor
> > >
> > > In the past, there was some interest in ports of NuttX to softcore's
> > > like MicroBlaze.  But there hasn't been that kind of interest in recent
> > > times.
> > >
> > > This would have been an innovation a decade or so ago, but I wonder
> > > about that now.
> > >
> > >
> > >
> > > On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote:
> > > > Tomek, as I clarified, porting NuttX to a FPGA will require a
> soft-core
> > > > CPU. I don't envision an opertaing system without a CPU, I see that
> like
> > > a
> > > > bad design choice if possible at all
> > > > Using a soft core and custom peripherals seems more valuable, even
> > > > including video output and USB host for mouse/keyboard handling. I've
> > > done
> > > > that for Micropython
> > > >
> > > > El sáb., 27 ene. 2024 13:23, Tomek CEDRO 
> escribió:
> > > >
> > > >> Okay Victor, I was thinking about toolchain that you present in
> > > >> "Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA conversion
> > > >> without a CPU design.. could you please send your full detailed
> > > >> proposal then? :-)
> > > >>
> > > >> [1] https://www.youtube.com/watch?v=hn3sr3VMJQU
> > > >>
> > > >> --
> > > >> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > > >>
> > > >> On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere
> > > >>  wrote:
> > > >>> Just clarifying, the idea to run NuttX on a FPGA is to instantiate
> a
> > > CPU
> > > >>> and peripherals on the FPGA and then run normally as if it were a
> MCU
> > > >>> Good thing is that you can change the CPU, add/remove peripherals,
> etc.
> > > >>>
> > > >>> On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO 
> wrote:
> > > >>>
> > >  Hey there Victor! Thanks for your interest in NuttX port to
> FPGA!! :-)
> > > 

Re: [OT] Projects for GSoC 2024

[Tomek CEDRO]

After some more considerations I am pro this "generic" NuttX@FPGA
Reference Design on GSoC proposal, 10 resons below :-)

I kindly ask to add this one to the proposals list :-)

1. We do not have a reference FPGA design for NuttX.
2. We do not have a reference fully Open-Source toolchain for FPGA+NuttX.
3. Yes someone did that before, and anyone can do that, but we can
provide generic out-of-the-box solution that most people are looking
for. Creating / repeating one yourself costs time.
4. We can gather smart community around NuttX that way (i.e. Victor).
5. FPGA are getting smaller and cheaper close to a price range of MCU
(i.e. $5+) [1][2].
6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO
nMHz vs nnnMHz). I can see unique benefit for having custom
peripherals created that way. I once did an R on new type of ADC
where MCU GPIO was not fast enough and I have to switch to FPGA +
external control MCU board.
7. Using propietary tools was quite painful because I had to use big
Xilinx Vivado while there are fully Open-Source toolchains already out
there we can use like Yosys / OSS CAD Suite [3] etc.
8. Scaling to bigger FPGA gives more possibilities like new
architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores)
[4], emulation [5], machine learning, etc.
9. My initial proposal was highly experimental and could easily fail.
Victor's proposal is merit and result based. It will for sure serve
many people out there for bigger and smaller projects.
10. Other ideas like Xorg port could be tested on FPGA implementation
too.. I already saw Victor's working windows manager with
chip-mod-player running on FPGA :-)

I can be mentor of that project because I would like to grow in that
field too as I have some ideas to test :-)

Thanks for considering :-)
Tomek

[1] https://tinyfpga.com/
[2] 
https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/
[3] https://github.com/YosysHQ/oss-cad-suite-build
[4] 
https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/
[5] https://www.retrorgb.com/mister.html

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere
 wrote:
>
> The innovation won't be to run NuttX in a RISC-V (soft-core or not) but
> using a FPGA for its flexibility to add any kind of peripherals, one of the
> main ones to be useful in my view will be a high-resolution framebuffer and
> USB mouse/keyboard for a complete UI
>
> On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt  wrote:
>
> > Aren't most CPUs available as soft cores?  Certainly Xtensa was intended
> > for that purpose.  ARM and MIPS have been common soft cores in ASICs for
> > more than a decade. As is RISC-V soft core in FPGAs.
> > https://en.wikipedia.org/wiki/Soft_microprocessor
> >
> > In the past, there was some interest in ports of NuttX to softcore's
> > like MicroBlaze.  But there hasn't been that kind of interest in recent
> > times.
> >
> > This would have been an innovation a decade or so ago, but I wonder
> > about that now.
> >
> >
> >
> > On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote:
> > > Tomek, as I clarified, porting NuttX to a FPGA will require a soft-core
> > > CPU. I don't envision an opertaing system without a CPU, I see that like
> > a
> > > bad design choice if possible at all
> > > Using a soft core and custom peripherals seems more valuable, even
> > > including video output and USB host for mouse/keyboard handling. I've
> > done
> > > that for Micropython
> > >
> > > El sáb., 27 ene. 2024 13:23, Tomek CEDRO  escribió:
> > >
> > >> Okay Victor, I was thinking about toolchain that you present in
> > >> "Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA conversion
> > >> without a CPU design.. could you please send your full detailed
> > >> proposal then? :-)
> > >>
> > >> [1] https://www.youtube.com/watch?v=hn3sr3VMJQU
> > >>
> > >> --
> > >> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > >>
> > >> On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere
> > >>  wrote:
> > >>> Just clarifying, the idea to run NuttX on a FPGA is to instantiate a
> > CPU
> > >>> and peripherals on the FPGA and then run normally as if it were a MCU
> > >>> Good thing is that you can change the CPU, add/remove peripherals, etc.
> > >>>
> > >>> On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO  wrote:
> > >>>
> >  Hey there Victor! Thanks for your interest in NuttX port to FPGA!! :-)
> > 
> >  No there is no such design yet.. you would have to create everything
> >  from scratch.. so there is some serious amount of work to do.. but
> >  imagine the results.. there will be just one step to ASIC!! :-)
> > 
> >  I could  reconsider my mentor position in this kind of project because
> >  I would really love to see the internals first hand.. with a help of
> >  more experienced NuttX'er for sure as second mentor :-) :-)
> > 
> >  I did 

Re: [OT] Projects for GSoC 2024

[Tomek CEDRO]

I have played with Wayland on FreeBSD and its NOT compatible with X11.
Its something >>>new<<<, a constantly fancy pancy moving target. Also
it is not network friendly (no client-server architecture) you need to
use VNC and this sux because of latency. I even tried to port some
stuff to Wayland@FBSD (i.e. Enlightenment WM) but I failed there is
too much Linux hardcoded stuff. So I still use Xorg myself :-) :-)

I can understand minimal port of Xorg it has strong merit to port
existing applications to NuttX. We even have display server - client
examples!

FB + LVGL is enough for us at that level and quite equivalent :-)

Over Wayland I would prefer to see native SDL implementation on NuttX
but that is another story :-)

We could think of Wayland on NuttX when it gets stable and mature
enough on a desktop.. and there would be good reason to invest time
into that work :-)

My 12 cents :D

Have a good weekend folks :-)
Tomek

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

On Fri, Feb 2, 2024 at 3:53 PM Alan C. Assis  wrote:
>
> Hi Tomek,
>
> Thank you for raising these good points and thank YF for suggesting it.
>
> I also don't know much details about it, maybe I think at list on Linux we
> have some other libs working between X11 and Wayland to make "legacy" code
> work correctly.
>
> I'm CC Nicolas Caramelli who recently added support to DirectFB2 (
> https://github.com/directfb2/DirectFB2) on NuttX, maybe (or maybe not) he
> could help us to get a better vision of it.
>
> Another advantage when thinking about X11 port to NuttX is because
> nanox/microwindows is an implementation that does exactly that.
>
> Also keep in mind that what RT-Thread did was just add support to use
> weston in the host, something NuttX has more than 3 years ago and works on
> X11 and Wayland.
>
> Their weston port (AFAIK) doesn't support any embedded board directly.
>
> BR,
>
> Alan
>
> On Fri, Feb 2, 2024 at 1:35 AM Tomek CEDRO  wrote:
>
> > On Fri, Feb 2, 2024 at 1:42 AM yfliu2008 wrote:
> > > How about adding Wayland instead of X11? It seems RT-Thread can run
> > weston now.
> >
> > * Wayland is basically a framebuffer.
> > * What are advantages of Wayland over X11 here?
> > * How would that support porting known libraries and applications to NuttX?
> > * What would be estimated workload and result?
> > * Would you like to port Wayland to NuttX?
> >
> > --
> > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> >

Re: [OT] Projects for GSoC 2024

[Alan C. Assis]

Hi Tomek,

Thank you for raising these good points and thank YF for suggesting it.

I also don't know much details about it, maybe I think at list on Linux we
have some other libs working between X11 and Wayland to make "legacy" code
work correctly.

I'm CC Nicolas Caramelli who recently added support to DirectFB2 (
https://github.com/directfb2/DirectFB2) on NuttX, maybe (or maybe not) he
could help us to get a better vision of it.

Another advantage when thinking about X11 port to NuttX is because
nanox/microwindows is an implementation that does exactly that.

Also keep in mind that what RT-Thread did was just add support to use
weston in the host, something NuttX has more than 3 years ago and works on
X11 and Wayland.

Their weston port (AFAIK) doesn't support any embedded board directly.

BR,

Alan

On Fri, Feb 2, 2024 at 1:35 AM Tomek CEDRO  wrote:

> On Fri, Feb 2, 2024 at 1:42 AM yfliu2008 wrote:
> > How about adding Wayland instead of X11? It seems RT-Thread can run
> weston now.
>
> * Wayland is basically a framebuffer.
> * What are advantages of Wayland over X11 here?
> * How would that support porting known libraries and applications to NuttX?
> * What would be estimated workload and result?
> * Would you like to port Wayland to NuttX?
>
> --
> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
>

Re: [OT] Projects for GSoC 2024

[Tomek CEDRO]

On Fri, Feb 2, 2024 at 1:42 AM yfliu2008 wrote:
> How about adding Wayland instead of X11? It seems RT-Thread can run weston 
> now.

* Wayland is basically a framebuffer.
* What are advantages of Wayland over X11 here?
* How would that support porting known libraries and applications to NuttX?
* What would be estimated workload and result?
* Would you like to port Wayland to NuttX?

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

Re: [OT] Projects for GSoC 2024

[Victor Suarez Rovere]

Yes! exactly like that. But with better maintenance, being able to run on
many boards, and more interesting peripherals (video, mouse, etc.)


On Sat, Jan 27, 2024 at 7:11 PM Gregory Nutt  wrote:

> Like
>
>   *
> https://riscv.org/blog/2023/02/porting-nuttx-real-time-operating-system-on-polarfire-soc-fpga/
>   *
> https://www.hackster.io/lupyuen/8-risc-v-sbc-on-a-real-time-operating-system-ox64-nuttx-474358
>   * https://twitter.com/btashton/status/1243699309117235200
>
> On 1/27/2024 3:58 PM, Victor Suarez Rovere wrote:
> > The innovation won't be to run NuttX in a RISC-V (soft-core or not) but
> > using a FPGA for its flexibility to add any kind of peripherals, one of
> the
> > main ones to be useful in my view will be a high-resolution framebuffer
> and
> > USB mouse/keyboard for a complete UI
> >
> > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt
> wrote:
> >
> >> Aren't most CPUs available as soft cores?  Certainly Xtensa was intended
> >> for that purpose.  ARM and MIPS have been common soft cores in ASICs for
> >> more than a decade. As is RISC-V soft core in FPGAs.
> >> https://en.wikipedia.org/wiki/Soft_microprocessor
> >>
> >> In the past, there was some interest in ports of NuttX to softcore's
> >> like MicroBlaze.  But there hasn't been that kind of interest in recent
> >> times.
> >>
> >> This would have been an innovation a decade or so ago, but I wonder
> >> about that now.
> >>
> >>
> >>
> >> On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote:
> >>> Tomek, as I clarified, porting NuttX to a FPGA will require a soft-core
> >>> CPU. I don't envision an opertaing system without a CPU, I see that
> like
> >> a
> >>> bad design choice if possible at all
> >>> Using a soft core and custom peripherals seems more valuable, even
> >>> including video output and USB host for mouse/keyboard handling. I've
> >> done
> >>> that for Micropython
> >>>
> >>> El sáb., 27 ene. 2024 13:23, Tomek CEDRO  escribió:
> >>>
>  Okay Victor, I was thinking about toolchain that you present in
>  "Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA conversion
>  without a CPU design.. could you please send your full detailed
>  proposal then? :-)
> 
>  [1]https://www.youtube.com/watch?v=hn3sr3VMJQU
> 
>  --
>  CeDeROM, SQ7MHZ,http://www.tomek.cedro.info
> 
>  On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere
>    wrote:
> > Just clarifying, the idea to run NuttX on a FPGA is to instantiate a
> >> CPU
> > and peripherals on the FPGA and then run normally as if it were a MCU
> > Good thing is that you can change the CPU, add/remove peripherals,
> etc.
> >
> > On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO
> wrote:
> >
> >> Hey there Victor! Thanks for your interest in NuttX port to FPGA!!
> :-)
> >>
> >> No there is no such design yet.. you would have to create everything
> >> from scratch.. so there is some serious amount of work to do.. but
> >> imagine the results.. there will be just one step to ASIC!! :-)
> >>
> >> I could  reconsider my mentor position in this kind of project
> because
> >> I would really love to see the internals first hand.. with a help of
> >> more experienced NuttX'er for sure as second mentor :-) :-)
> >>
> >> I did a PONG on FPGA over 10 years ago but I would never dare to run
> >> CPU-less-program directly on FPGA.. then RTOS.. then lets say Atari
> >> emulator.. chip module player.. open source smart debug probe.. a
> >> neural interface.. who knows.. would that even fit into the FPGA?
> :-)
> >> :-)
> >>
> >> I have a strong feeling this may be important.. but I leave the
> whole
> >> decision to the PMC :-)
> >>
> >> Have a good weekend my friends :-)
> >> Tomek
> >>
> >> --
> >> CeDeROM, SQ7MHZ,http://www.tomek.cedro.info
> >>
> >> On Sat, Jan 27, 2024 at 2:55 AM Victor Suarez Rovere
> >>   wrote:
> >>> I can certainly port NuttX to run on some FPGA boards too
> >>> Is any board already supported?
> >>>
> >>> On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis
>  wrote:
>  Hi Tomek,
> 
>  His toolchain is focused on FPGA, but he is interested in
> >> participating in
>  other projects for GSoC.
> 
>  Also we need NuttX mentors, I will participate, but for each
>  project we
>  need two mentors, please let me know who could be interested to
>  help.
>  Best Regards,
> 
>  Alan
> 
>  On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO
>  wrote:
> > On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:
> >> Dear NuttXers,
> >> Please find below some ideas of projects to improve NuttX
>  during
> >> the
> >> GSoC2024:
> >>
> 
> https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list
> >> If you have some other ideas, please 

Re: [OT] Projects for GSoC 2024

[Gregory Nutt]

Like

 * 
https://riscv.org/blog/2023/02/porting-nuttx-real-time-operating-system-on-polarfire-soc-fpga/
 * 
https://www.hackster.io/lupyuen/8-risc-v-sbc-on-a-real-time-operating-system-ox64-nuttx-474358
 * https://twitter.com/btashton/status/1243699309117235200

On 1/27/2024 3:58 PM, Victor Suarez Rovere wrote:

The innovation won't be to run NuttX in a RISC-V (soft-core or not) but
using a FPGA for its flexibility to add any kind of peripherals, one of the
main ones to be useful in my view will be a high-resolution framebuffer and
USB mouse/keyboard for a complete UI

On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt  wrote:


Aren't most CPUs available as soft cores?  Certainly Xtensa was intended
for that purpose.  ARM and MIPS have been common soft cores in ASICs for
more than a decade. As is RISC-V soft core in FPGAs.
https://en.wikipedia.org/wiki/Soft_microprocessor

In the past, there was some interest in ports of NuttX to softcore's
like MicroBlaze.  But there hasn't been that kind of interest in recent
times.

This would have been an innovation a decade or so ago, but I wonder
about that now.



On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote:

Tomek, as I clarified, porting NuttX to a FPGA will require a soft-core
CPU. I don't envision an opertaing system without a CPU, I see that like

a

bad design choice if possible at all
Using a soft core and custom peripherals seems more valuable, even
including video output and USB host for mouse/keyboard handling. I've

done

that for Micropython

El sáb., 27 ene. 2024 13:23, Tomek CEDRO  escribió:


Okay Victor, I was thinking about toolchain that you present in
"Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA conversion
without a CPU design.. could you please send your full detailed
proposal then? :-)

[1]https://www.youtube.com/watch?v=hn3sr3VMJQU

--
CeDeROM, SQ7MHZ,http://www.tomek.cedro.info

On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere
  wrote:

Just clarifying, the idea to run NuttX on a FPGA is to instantiate a

CPU

and peripherals on the FPGA and then run normally as if it were a MCU
Good thing is that you can change the CPU, add/remove peripherals, etc.

On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO  wrote:


Hey there Victor! Thanks for your interest in NuttX port to FPGA!! :-)

No there is no such design yet.. you would have to create everything
from scratch.. so there is some serious amount of work to do.. but
imagine the results.. there will be just one step to ASIC!! :-)

I could  reconsider my mentor position in this kind of project because
I would really love to see the internals first hand.. with a help of
more experienced NuttX'er for sure as second mentor :-) :-)

I did a PONG on FPGA over 10 years ago but I would never dare to run
CPU-less-program directly on FPGA.. then RTOS.. then lets say Atari
emulator.. chip module player.. open source smart debug probe.. a
neural interface.. who knows.. would that even fit into the FPGA? :-)
:-)

I have a strong feeling this may be important.. but I leave the whole
decision to the PMC :-)

Have a good weekend my friends :-)
Tomek

--
CeDeROM, SQ7MHZ,http://www.tomek.cedro.info

On Sat, Jan 27, 2024 at 2:55 AM Victor Suarez Rovere
  wrote:

I can certainly port NuttX to run on some FPGA boards too
Is any board already supported?

On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis

wrote:

Hi Tomek,

His toolchain is focused on FPGA, but he is interested in

participating in

other projects for GSoC.

Also we need NuttX mentors, I will participate, but for each

project we

need two mentors, please let me know who could be interested to

help.

Best Regards,

Alan

On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO

wrote:

On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:

Dear NuttXers,
Please find below some ideas of projects to improve NuttX

during

the

GSoC2024:


https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list

If you have some other ideas, please let me know.

I would like to propose Victor Suarez (CC) idea for porting

toolchain

NuttX RTOS directly to FPGA :-)




https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip

Tomek

--
CeDeROM, SQ7MHZ,http://www.tomek.cedro.info

Re: [OT] Projects for GSoC 2024

[Tomek CEDRO]

Roger that :-) I was thinking about experiment like in "Sphery vs.
Shapes" to convert NuttX code to FPGA LUT directly with no CPU.. but
if that makes no sense then probably Open-Source RISC-V would be the
best choice and there are some ready to use implementations that could
constitute our reference NuttX@FPGA design.. the goal here probably
would be to run on smallest possible LUT count or something with
amazingly better performance than out-of-the-box hardware? :-)

Let Victor / PMC decide on the task specifics and priorities, sorry
for the noise folks :-)

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

On Sat, Jan 27, 2024 at 8:18 PM Victor Suarez Rovere
 wrote:
>
> Tomek, as I clarified, porting NuttX to a FPGA will require a soft-core
> CPU. I don't envision an opertaing system without a CPU, I see that like a
> bad design choice if possible at all
> Using a soft core and custom peripherals seems more valuable, even
> including video output and USB host for mouse/keyboard handling. I've done
> that for Micropython
>
> El sáb., 27 ene. 2024 13:23, Tomek CEDRO  escribió:
>
> > Okay Victor, I was thinking about toolchain that you present in
> > "Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA conversion
> > without a CPU design.. could you please send your full detailed
> > proposal then? :-)
> >
> > [1] https://www.youtube.com/watch?v=hn3sr3VMJQU
> >
> > --
> > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> >
> > On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere
> >  wrote:
> > >
> > > Just clarifying, the idea to run NuttX on a FPGA is to instantiate a CPU
> > > and peripherals on the FPGA and then run normally as if it were a MCU
> > > Good thing is that you can change the CPU, add/remove peripherals, etc.
> > >
> > > On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO  wrote:
> > >
> > > > Hey there Victor! Thanks for your interest in NuttX port to FPGA!! :-)
> > > >
> > > > No there is no such design yet.. you would have to create everything
> > > > from scratch.. so there is some serious amount of work to do.. but
> > > > imagine the results.. there will be just one step to ASIC!! :-)
> > > >
> > > > I could  reconsider my mentor position in this kind of project because
> > > > I would really love to see the internals first hand.. with a help of
> > > > more experienced NuttX'er for sure as second mentor :-) :-)
> > > >
> > > > I did a PONG on FPGA over 10 years ago but I would never dare to run
> > > > CPU-less-program directly on FPGA.. then RTOS.. then lets say Atari
> > > > emulator.. chip module player.. open source smart debug probe.. a
> > > > neural interface.. who knows.. would that even fit into the FPGA? :-)
> > > > :-)
> > > >
> > > > I have a strong feeling this may be important.. but I leave the whole
> > > > decision to the PMC :-)
> > > >
> > > > Have a good weekend my friends :-)
> > > > Tomek
> > > >
> > > > --
> > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > > >
> > > > On Sat, Jan 27, 2024 at 2:55 AM Victor Suarez Rovere
> > > >  wrote:
> > > > >
> > > > > I can certainly port NuttX to run on some FPGA boards too
> > > > > Is any board already supported?
> > > > >
> > > > > On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis 
> > wrote:
> > > > >
> > > > > > Hi Tomek,
> > > > > >
> > > > > > His toolchain is focused on FPGA, but he is interested in
> > > > participating in
> > > > > > other projects for GSoC.
> > > > > >
> > > > > > Also we need NuttX mentors, I will participate, but for each
> > project we
> > > > > > need two mentors, please let me know who could be interested to
> > help.
> > > > > >
> > > > > > Best Regards,
> > > > > >
> > > > > > Alan
> > > > > >
> > > > > > On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO 
> > wrote:
> > > > > >
> > > > > > > On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:
> > > > > > > > Dear NuttXers,
> > > > > > > > Please find below some ideas of projects to improve NuttX
> > during
> > > > the
> > > > > > > > GSoC2024:
> > > > > > > >
> > > > > >
> > > >
> > https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list
> > > > > > > > If you have some other ideas, please let me know.
> > > > > > >
> > > > > > > I would like to propose Victor Suarez (CC) idea for porting
> > toolchain
> > > > > > > NuttX RTOS directly to FPGA :-)
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > >
> > > >
> > https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip
> > > > > > >
> > > > > > > Tomek
> > > > > > >
> > > > > > > --
> > > > > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > > > > > >
> > > > > >
> > > >
> >

Re: [OT] Projects for GSoC 2024

[Victor Suarez Rovere]

The innovation won't be to run NuttX in a RISC-V (soft-core or not) but
using a FPGA for its flexibility to add any kind of peripherals, one of the
main ones to be useful in my view will be a high-resolution framebuffer and
USB mouse/keyboard for a complete UI

On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt  wrote:

> Aren't most CPUs available as soft cores?  Certainly Xtensa was intended
> for that purpose.  ARM and MIPS have been common soft cores in ASICs for
> more than a decade. As is RISC-V soft core in FPGAs.
> https://en.wikipedia.org/wiki/Soft_microprocessor
>
> In the past, there was some interest in ports of NuttX to softcore's
> like MicroBlaze.  But there hasn't been that kind of interest in recent
> times.
>
> This would have been an innovation a decade or so ago, but I wonder
> about that now.
>
>
>
> On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote:
> > Tomek, as I clarified, porting NuttX to a FPGA will require a soft-core
> > CPU. I don't envision an opertaing system without a CPU, I see that like
> a
> > bad design choice if possible at all
> > Using a soft core and custom peripherals seems more valuable, even
> > including video output and USB host for mouse/keyboard handling. I've
> done
> > that for Micropython
> >
> > El sáb., 27 ene. 2024 13:23, Tomek CEDRO  escribió:
> >
> >> Okay Victor, I was thinking about toolchain that you present in
> >> "Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA conversion
> >> without a CPU design.. could you please send your full detailed
> >> proposal then? :-)
> >>
> >> [1] https://www.youtube.com/watch?v=hn3sr3VMJQU
> >>
> >> --
> >> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> >>
> >> On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere
> >>  wrote:
> >>> Just clarifying, the idea to run NuttX on a FPGA is to instantiate a
> CPU
> >>> and peripherals on the FPGA and then run normally as if it were a MCU
> >>> Good thing is that you can change the CPU, add/remove peripherals, etc.
> >>>
> >>> On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO  wrote:
> >>>
>  Hey there Victor! Thanks for your interest in NuttX port to FPGA!! :-)
> 
>  No there is no such design yet.. you would have to create everything
>  from scratch.. so there is some serious amount of work to do.. but
>  imagine the results.. there will be just one step to ASIC!! :-)
> 
>  I could  reconsider my mentor position in this kind of project because
>  I would really love to see the internals first hand.. with a help of
>  more experienced NuttX'er for sure as second mentor :-) :-)
> 
>  I did a PONG on FPGA over 10 years ago but I would never dare to run
>  CPU-less-program directly on FPGA.. then RTOS.. then lets say Atari
>  emulator.. chip module player.. open source smart debug probe.. a
>  neural interface.. who knows.. would that even fit into the FPGA? :-)
>  :-)
> 
>  I have a strong feeling this may be important.. but I leave the whole
>  decision to the PMC :-)
> 
>  Have a good weekend my friends :-)
>  Tomek
> 
>  --
>  CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> 
>  On Sat, Jan 27, 2024 at 2:55 AM Victor Suarez Rovere
>   wrote:
> > I can certainly port NuttX to run on some FPGA boards too
> > Is any board already supported?
> >
> > On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis 
> >> wrote:
> >> Hi Tomek,
> >>
> >> His toolchain is focused on FPGA, but he is interested in
>  participating in
> >> other projects for GSoC.
> >>
> >> Also we need NuttX mentors, I will participate, but for each
> >> project we
> >> need two mentors, please let me know who could be interested to
> >> help.
> >> Best Regards,
> >>
> >> Alan
> >>
> >> On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO 
> >> wrote:
> >>> On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:
>  Dear NuttXers,
>  Please find below some ideas of projects to improve NuttX
> >> during
>  the
>  GSoC2024:
> 
> >> https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list
>  If you have some other ideas, please let me know.
> >>> I would like to propose Victor Suarez (CC) idea for porting
> >> toolchain
> >>> NuttX RTOS directly to FPGA :-)
> >>>
> >>>
> >>>
> >>
> https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip
> >>> Tomek
> >>>
> >>> --
> >>> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> >>>
>
>

Re: [OT] Projects for GSoC 2024

[Gregory Nutt]

Aren't most CPUs available as soft cores?  Certainly Xtensa was intended 
for that purpose.  ARM and MIPS have been common soft cores in ASICs for 
more than a decade. As is RISC-V soft core in FPGAs. 
https://en.wikipedia.org/wiki/Soft_microprocessor


In the past, there was some interest in ports of NuttX to softcore's 
like MicroBlaze.  But there hasn't been that kind of interest in recent 
times.


This would have been an innovation a decade or so ago, but I wonder 
about that now.




On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote:

Tomek, as I clarified, porting NuttX to a FPGA will require a soft-core
CPU. I don't envision an opertaing system without a CPU, I see that like a
bad design choice if possible at all
Using a soft core and custom peripherals seems more valuable, even
including video output and USB host for mouse/keyboard handling. I've done
that for Micropython

El sáb., 27 ene. 2024 13:23, Tomek CEDRO  escribió:


Okay Victor, I was thinking about toolchain that you present in
"Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA conversion
without a CPU design.. could you please send your full detailed
proposal then? :-)

[1] https://www.youtube.com/watch?v=hn3sr3VMJQU

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere
 wrote:

Just clarifying, the idea to run NuttX on a FPGA is to instantiate a CPU
and peripherals on the FPGA and then run normally as if it were a MCU
Good thing is that you can change the CPU, add/remove peripherals, etc.

On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO  wrote:


Hey there Victor! Thanks for your interest in NuttX port to FPGA!! :-)

No there is no such design yet.. you would have to create everything
from scratch.. so there is some serious amount of work to do.. but
imagine the results.. there will be just one step to ASIC!! :-)

I could  reconsider my mentor position in this kind of project because
I would really love to see the internals first hand.. with a help of
more experienced NuttX'er for sure as second mentor :-) :-)

I did a PONG on FPGA over 10 years ago but I would never dare to run
CPU-less-program directly on FPGA.. then RTOS.. then lets say Atari
emulator.. chip module player.. open source smart debug probe.. a
neural interface.. who knows.. would that even fit into the FPGA? :-)
:-)

I have a strong feeling this may be important.. but I leave the whole
decision to the PMC :-)

Have a good weekend my friends :-)
Tomek

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

On Sat, Jan 27, 2024 at 2:55 AM Victor Suarez Rovere
 wrote:

I can certainly port NuttX to run on some FPGA boards too
Is any board already supported?

On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis 

wrote:

Hi Tomek,

His toolchain is focused on FPGA, but he is interested in

participating in

other projects for GSoC.

Also we need NuttX mentors, I will participate, but for each

project we

need two mentors, please let me know who could be interested to

help.

Best Regards,

Alan

On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO 

wrote:

On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:

Dear NuttXers,
Please find below some ideas of projects to improve NuttX

during

the

GSoC2024:


https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list

If you have some other ideas, please let me know.

I would like to propose Victor Suarez (CC) idea for porting

toolchain

NuttX RTOS directly to FPGA :-)




https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip

Tomek

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

Re: [OT] Projects for GSoC 2024

[Victor Suarez Rovere]

Tomek, as I clarified, porting NuttX to a FPGA will require a soft-core
CPU. I don't envision an opertaing system without a CPU, I see that like a
bad design choice if possible at all
Using a soft core and custom peripherals seems more valuable, even
including video output and USB host for mouse/keyboard handling. I've done
that for Micropython

El sáb., 27 ene. 2024 13:23, Tomek CEDRO  escribió:

> Okay Victor, I was thinking about toolchain that you present in
> "Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA conversion
> without a CPU design.. could you please send your full detailed
> proposal then? :-)
>
> [1] https://www.youtube.com/watch?v=hn3sr3VMJQU
>
> --
> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
>
> On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere
>  wrote:
> >
> > Just clarifying, the idea to run NuttX on a FPGA is to instantiate a CPU
> > and peripherals on the FPGA and then run normally as if it were a MCU
> > Good thing is that you can change the CPU, add/remove peripherals, etc.
> >
> > On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO  wrote:
> >
> > > Hey there Victor! Thanks for your interest in NuttX port to FPGA!! :-)
> > >
> > > No there is no such design yet.. you would have to create everything
> > > from scratch.. so there is some serious amount of work to do.. but
> > > imagine the results.. there will be just one step to ASIC!! :-)
> > >
> > > I could  reconsider my mentor position in this kind of project because
> > > I would really love to see the internals first hand.. with a help of
> > > more experienced NuttX'er for sure as second mentor :-) :-)
> > >
> > > I did a PONG on FPGA over 10 years ago but I would never dare to run
> > > CPU-less-program directly on FPGA.. then RTOS.. then lets say Atari
> > > emulator.. chip module player.. open source smart debug probe.. a
> > > neural interface.. who knows.. would that even fit into the FPGA? :-)
> > > :-)
> > >
> > > I have a strong feeling this may be important.. but I leave the whole
> > > decision to the PMC :-)
> > >
> > > Have a good weekend my friends :-)
> > > Tomek
> > >
> > > --
> > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > >
> > > On Sat, Jan 27, 2024 at 2:55 AM Victor Suarez Rovere
> > >  wrote:
> > > >
> > > > I can certainly port NuttX to run on some FPGA boards too
> > > > Is any board already supported?
> > > >
> > > > On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis 
> wrote:
> > > >
> > > > > Hi Tomek,
> > > > >
> > > > > His toolchain is focused on FPGA, but he is interested in
> > > participating in
> > > > > other projects for GSoC.
> > > > >
> > > > > Also we need NuttX mentors, I will participate, but for each
> project we
> > > > > need two mentors, please let me know who could be interested to
> help.
> > > > >
> > > > > Best Regards,
> > > > >
> > > > > Alan
> > > > >
> > > > > On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO 
> wrote:
> > > > >
> > > > > > On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:
> > > > > > > Dear NuttXers,
> > > > > > > Please find below some ideas of projects to improve NuttX
> during
> > > the
> > > > > > > GSoC2024:
> > > > > > >
> > > > >
> > >
> https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list
> > > > > > > If you have some other ideas, please let me know.
> > > > > >
> > > > > > I would like to propose Victor Suarez (CC) idea for porting
> toolchain
> > > > > > NuttX RTOS directly to FPGA :-)
> > > > > >
> > > > > >
> > > > > >
> > > > >
> > >
> https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip
> > > > > >
> > > > > > Tomek
> > > > > >
> > > > > > --
> > > > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > > > > >
> > > > >
> > >
>

Re: [OT] Projects for GSoC 2024

[Alan C. Assis]

Hi Tomek,

AFAIK, compiling the NuttX to run inside an FPGA is not a kind of task to
be done in a GSoC project, it should be a long term effort (if John Keynes
allows us).

Also keep in mind that currently NuttX RTOS is supposed to run on top of a
processing unit (Microcontroller, Microprocessor, etc), it is not a simple
state machine that can be emulated easily in FPGA.
So, it should be something completely different. But of course, maybe there
are some shortcuts that I'm not aware of.

BTW, Victor is also interested in participating in other projects that are
related to other areas of interest (i.e. Graphics, like X11 support to let
NuttX run Unix/Linux graphics applications).

Best Regards,

Alan


On Sat, Jan 27, 2024 at 1:23 PM Tomek CEDRO  wrote:

> Okay Victor, I was thinking about toolchain that you present in
> "Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA conversion
> without a CPU design.. could you please send your full detailed
> proposal then? :-)
>
> [1] https://www.youtube.com/watch?v=hn3sr3VMJQU
>
> --
> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
>
> On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere
>  wrote:
> >
> > Just clarifying, the idea to run NuttX on a FPGA is to instantiate a CPU
> > and peripherals on the FPGA and then run normally as if it were a MCU
> > Good thing is that you can change the CPU, add/remove peripherals, etc.
> >
> > On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO  wrote:
> >
> > > Hey there Victor! Thanks for your interest in NuttX port to FPGA!! :-)
> > >
> > > No there is no such design yet.. you would have to create everything
> > > from scratch.. so there is some serious amount of work to do.. but
> > > imagine the results.. there will be just one step to ASIC!! :-)
> > >
> > > I could  reconsider my mentor position in this kind of project because
> > > I would really love to see the internals first hand.. with a help of
> > > more experienced NuttX'er for sure as second mentor :-) :-)
> > >
> > > I did a PONG on FPGA over 10 years ago but I would never dare to run
> > > CPU-less-program directly on FPGA.. then RTOS.. then lets say Atari
> > > emulator.. chip module player.. open source smart debug probe.. a
> > > neural interface.. who knows.. would that even fit into the FPGA? :-)
> > > :-)
> > >
> > > I have a strong feeling this may be important.. but I leave the whole
> > > decision to the PMC :-)
> > >
> > > Have a good weekend my friends :-)
> > > Tomek
> > >
> > > --
> > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > >
> > > On Sat, Jan 27, 2024 at 2:55 AM Victor Suarez Rovere
> > >  wrote:
> > > >
> > > > I can certainly port NuttX to run on some FPGA boards too
> > > > Is any board already supported?
> > > >
> > > > On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis 
> wrote:
> > > >
> > > > > Hi Tomek,
> > > > >
> > > > > His toolchain is focused on FPGA, but he is interested in
> > > participating in
> > > > > other projects for GSoC.
> > > > >
> > > > > Also we need NuttX mentors, I will participate, but for each
> project we
> > > > > need two mentors, please let me know who could be interested to
> help.
> > > > >
> > > > > Best Regards,
> > > > >
> > > > > Alan
> > > > >
> > > > > On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO 
> wrote:
> > > > >
> > > > > > On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:
> > > > > > > Dear NuttXers,
> > > > > > > Please find below some ideas of projects to improve NuttX
> during
> > > the
> > > > > > > GSoC2024:
> > > > > > >
> > > > >
> > >
> https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list
> > > > > > > If you have some other ideas, please let me know.
> > > > > >
> > > > > > I would like to propose Victor Suarez (CC) idea for porting
> toolchain
> > > > > > NuttX RTOS directly to FPGA :-)
> > > > > >
> > > > > >
> > > > > >
> > > > >
> > >
> https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip
> > > > > >
> > > > > > Tomek
> > > > > >
> > > > > > --
> > > > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > > > > >
> > > > >
> > >
>

Re: [OT] Projects for GSoC 2024

[Tomek CEDRO]

Okay Victor, I was thinking about toolchain that you present in
"Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA conversion
without a CPU design.. could you please send your full detailed
proposal then? :-)

[1] https://www.youtube.com/watch?v=hn3sr3VMJQU

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere
 wrote:
>
> Just clarifying, the idea to run NuttX on a FPGA is to instantiate a CPU
> and peripherals on the FPGA and then run normally as if it were a MCU
> Good thing is that you can change the CPU, add/remove peripherals, etc.
>
> On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO  wrote:
>
> > Hey there Victor! Thanks for your interest in NuttX port to FPGA!! :-)
> >
> > No there is no such design yet.. you would have to create everything
> > from scratch.. so there is some serious amount of work to do.. but
> > imagine the results.. there will be just one step to ASIC!! :-)
> >
> > I could  reconsider my mentor position in this kind of project because
> > I would really love to see the internals first hand.. with a help of
> > more experienced NuttX'er for sure as second mentor :-) :-)
> >
> > I did a PONG on FPGA over 10 years ago but I would never dare to run
> > CPU-less-program directly on FPGA.. then RTOS.. then lets say Atari
> > emulator.. chip module player.. open source smart debug probe.. a
> > neural interface.. who knows.. would that even fit into the FPGA? :-)
> > :-)
> >
> > I have a strong feeling this may be important.. but I leave the whole
> > decision to the PMC :-)
> >
> > Have a good weekend my friends :-)
> > Tomek
> >
> > --
> > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> >
> > On Sat, Jan 27, 2024 at 2:55 AM Victor Suarez Rovere
> >  wrote:
> > >
> > > I can certainly port NuttX to run on some FPGA boards too
> > > Is any board already supported?
> > >
> > > On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis  wrote:
> > >
> > > > Hi Tomek,
> > > >
> > > > His toolchain is focused on FPGA, but he is interested in
> > participating in
> > > > other projects for GSoC.
> > > >
> > > > Also we need NuttX mentors, I will participate, but for each project we
> > > > need two mentors, please let me know who could be interested to help.
> > > >
> > > > Best Regards,
> > > >
> > > > Alan
> > > >
> > > > On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO  wrote:
> > > >
> > > > > On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:
> > > > > > Dear NuttXers,
> > > > > > Please find below some ideas of projects to improve NuttX during
> > the
> > > > > > GSoC2024:
> > > > > >
> > > >
> > https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list
> > > > > > If you have some other ideas, please let me know.
> > > > >
> > > > > I would like to propose Victor Suarez (CC) idea for porting toolchain
> > > > > NuttX RTOS directly to FPGA :-)
> > > > >
> > > > >
> > > > >
> > > >
> > https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip
> > > > >
> > > > > Tomek
> > > > >
> > > > > --
> > > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > > > >
> > > >
> >

Re: [OT] Projects for GSoC 2024

[Victor Suarez Rovere]

Just clarifying, the idea to run NuttX on a FPGA is to instantiate a CPU
and peripherals on the FPGA and then run normally as if it were a MCU
Good thing is that you can change the CPU, add/remove peripherals, etc.

On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO  wrote:

> Hey there Victor! Thanks for your interest in NuttX port to FPGA!! :-)
>
> No there is no such design yet.. you would have to create everything
> from scratch.. so there is some serious amount of work to do.. but
> imagine the results.. there will be just one step to ASIC!! :-)
>
> I could  reconsider my mentor position in this kind of project because
> I would really love to see the internals first hand.. with a help of
> more experienced NuttX'er for sure as second mentor :-) :-)
>
> I did a PONG on FPGA over 10 years ago but I would never dare to run
> CPU-less-program directly on FPGA.. then RTOS.. then lets say Atari
> emulator.. chip module player.. open source smart debug probe.. a
> neural interface.. who knows.. would that even fit into the FPGA? :-)
> :-)
>
> I have a strong feeling this may be important.. but I leave the whole
> decision to the PMC :-)
>
> Have a good weekend my friends :-)
> Tomek
>
> --
> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
>
> On Sat, Jan 27, 2024 at 2:55 AM Victor Suarez Rovere
>  wrote:
> >
> > I can certainly port NuttX to run on some FPGA boards too
> > Is any board already supported?
> >
> > On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis  wrote:
> >
> > > Hi Tomek,
> > >
> > > His toolchain is focused on FPGA, but he is interested in
> participating in
> > > other projects for GSoC.
> > >
> > > Also we need NuttX mentors, I will participate, but for each project we
> > > need two mentors, please let me know who could be interested to help.
> > >
> > > Best Regards,
> > >
> > > Alan
> > >
> > > On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO  wrote:
> > >
> > > > On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:
> > > > > Dear NuttXers,
> > > > > Please find below some ideas of projects to improve NuttX during
> the
> > > > > GSoC2024:
> > > > >
> > >
> https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list
> > > > > If you have some other ideas, please let me know.
> > > >
> > > > I would like to propose Victor Suarez (CC) idea for porting toolchain
> > > > NuttX RTOS directly to FPGA :-)
> > > >
> > > >
> > > >
> > >
> https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip
> > > >
> > > > Tomek
> > > >
> > > > --
> > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > > >
> > >
>

Re: [OT] Projects for GSoC 2024

[Tomek CEDRO]

Hey there Victor! Thanks for your interest in NuttX port to FPGA!! :-)

No there is no such design yet.. you would have to create everything
from scratch.. so there is some serious amount of work to do.. but
imagine the results.. there will be just one step to ASIC!! :-)

I could  reconsider my mentor position in this kind of project because
I would really love to see the internals first hand.. with a help of
more experienced NuttX'er for sure as second mentor :-) :-)

I did a PONG on FPGA over 10 years ago but I would never dare to run
CPU-less-program directly on FPGA.. then RTOS.. then lets say Atari
emulator.. chip module player.. open source smart debug probe.. a
neural interface.. who knows.. would that even fit into the FPGA? :-)
:-)

I have a strong feeling this may be important.. but I leave the whole
decision to the PMC :-)

Have a good weekend my friends :-)
Tomek

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

On Sat, Jan 27, 2024 at 2:55 AM Victor Suarez Rovere
 wrote:
>
> I can certainly port NuttX to run on some FPGA boards too
> Is any board already supported?
>
> On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis  wrote:
>
> > Hi Tomek,
> >
> > His toolchain is focused on FPGA, but he is interested in participating in
> > other projects for GSoC.
> >
> > Also we need NuttX mentors, I will participate, but for each project we
> > need two mentors, please let me know who could be interested to help.
> >
> > Best Regards,
> >
> > Alan
> >
> > On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO  wrote:
> >
> > > On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:
> > > > Dear NuttXers,
> > > > Please find below some ideas of projects to improve NuttX during the
> > > > GSoC2024:
> > > >
> > https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list
> > > > If you have some other ideas, please let me know.
> > >
> > > I would like to propose Victor Suarez (CC) idea for porting toolchain
> > > NuttX RTOS directly to FPGA :-)
> > >
> > >
> > >
> > https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip
> > >
> > > Tomek
> > >
> > > --
> > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> > >
> >

Re: [OT] Projects for GSoC 2024

[Victor Suarez Rovere]

I can certainly port NuttX to run on some FPGA boards too
Is any board already supported?

On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis  wrote:

> Hi Tomek,
>
> His toolchain is focused on FPGA, but he is interested in participating in
> other projects for GSoC.
>
> Also we need NuttX mentors, I will participate, but for each project we
> need two mentors, please let me know who could be interested to help.
>
> Best Regards,
>
> Alan
>
> On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO  wrote:
>
> > On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:
> > > Dear NuttXers,
> > > Please find below some ideas of projects to improve NuttX during the
> > > GSoC2024:
> > >
> https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list
> > > If you have some other ideas, please let me know.
> >
> > I would like to propose Victor Suarez (CC) idea for porting toolchain
> > NuttX RTOS directly to FPGA :-)
> >
> >
> >
> https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip
> >
> > Tomek
> >
> > --
> > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
> >
>

Re: [OT] Projects for GSoC 2024

[Tomek CEDRO]

On Fri, Jan 26, 2024 at 8:40 PM Alan C. Assis wrote:
> His toolchain is focused on FPGA, but he is interested in participating in
> other projects for GSoC.

Yes, and that toolchain could be used to cross-build NuttX ROTS to
FPGA without a CPU with amazing efficiency as proved on x86
architecture! This is something unique and soon technology will
probably enable rapid ASIC prototyping we could have a working
solution like no one else. Look at NeuraLink their only way because of
energy and size is the ASIC way. More companies will follow in
upcoming years because everything becomes smaller and more energy
efficient.. soon it will probably harvest power from the air. I think
this is worth considering and Victor is keen to use his experience in
this area :-)

By the way what is this GSOC about? Do they provide a funding for a
given research? Do all proposals are accepted? What is the timeline? I
always wanted to make smart debug probe fully open-source now I know
it will be done on NuttX.. maybe OpenOCD could be ported here and run
from ESP32-S3 (it is cheap, has USB-JTAG, WIFI, BLE, and fast GPIO)?
:-)

I just give ideas as requested :D

> Also we need NuttX mentors, I will participate, but for each project we
> need two mentors, please let me know who could be interested to help.

I would gladly help but my experience is still to small to mentor sorry :-(

I think Lup would be a great mentor.. if that does not prevent him
from taking part in the projects??

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

Re: [OT] Projects for GSoC 2024

[Alan C. Assis]

Hi Tomek,

His toolchain is focused on FPGA, but he is interested in participating in
other projects for GSoC.

Also we need NuttX mentors, I will participate, but for each project we
need two mentors, please let me know who could be interested to help.

Best Regards,

Alan

On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO  wrote:

> On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:
> > Dear NuttXers,
> > Please find below some ideas of projects to improve NuttX during the
> > GSoC2024:
> > https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list
> > If you have some other ideas, please let me know.
>
> I would like to propose Victor Suarez (CC) idea for porting toolchain
> NuttX RTOS directly to FPGA :-)
>
>
> https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip
>
> Tomek
>
> --
> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
>

Re: [OT] Projects for GSoC 2024

[Tomek CEDRO]

On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote:
> Dear NuttXers,
> Please find below some ideas of projects to improve NuttX during the
> GSoC2024:
> https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list
> If you have some other ideas, please let me know.

I would like to propose Victor Suarez (CC) idea for porting toolchain
NuttX RTOS directly to FPGA :-)

https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip

Tomek

--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info