Re: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC.
On Mon, Jun 07, 2021 at 03:25:06PM -0500, Segher Boessenkool wrote:
> On Tue, May 18, 2021 at 04:26:06PM -0400, Michael Meissner wrote:
> > This patch adds the support for the IEEE 128-bit floating point C minimum
> > and
> > maximum instructions.
>
> > gcc/
> > 2021-05-18 Michael Meissner
> >
> > * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
> > 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp
> > instructions.
>
> 3.1 fits on the previous line (it is better to not split numbers to a
> new line). What is up with the weird multiple spaces? We don't align
> the right border in changelogs :-)
>
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
> > @@ -0,0 +1,15 @@
> > +/* { dg-require-effective-target ppc_float128_hw } */
> > +/* { dg-require-effective-target power10_ok } */
>
> Is this needed? And, why is ppc_float128_hw needed? That combination
> does not seem to make sense.
Basically it is there to make sure that we are actually generating IEEE 128-bit
instructions.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
Re: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC.
On Tue, May 18, 2021 at 04:26:06PM -0400, Michael Meissner wrote:
> This patch adds the support for the IEEE 128-bit floating point C minimum and
> maximum instructions.
> gcc/
> 2021-05-18 Michael Meissner
>
> * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
> 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp
> instructions.
3.1 fits on the previous line (it is better to not split numbers to a
new line). What is up with the weird multiple spaces? We don't align
the right border in changelogs :-)
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
> @@ -0,0 +1,15 @@
> +/* { dg-require-effective-target ppc_float128_hw } */
> +/* { dg-require-effective-target power10_ok } */
Is this needed? And, why is ppc_float128_hw needed? That combination
does not seem to make sense.
> --- a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
> +++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
> @@ -3,6 +3,13 @@
> /* { dg-require-effective-target float128 } */
> /* { dg-options "-mpower9-vector -O2 -ffast-math" } */
>
> +/* If the compiler was configured to automatically generate power10 support
> with
> + --with-cpu=power10, turn it off. Otherwise, it will generate XXMAXCQP and
> + XXMINCQP instructions. */
> +#ifdef _ARCH_PWR10
> +#pragma GCC target ("cpu=power9")
> +#endif
Yeah, don't. Add a dg-skip-if if that is what you want. That
-mpower9-vector shouldn't be there either.
Segher
Re: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC.
Hi! On Thu, May 20, 2021 at 09:38:49PM -0400, Michael Meissner wrote: > Basically for code generation tests, I see the following cases: > > 1) Test code targetting precisley power8 (or power9, power10), etc. Hopefully > these are rare. -mdejagnu-cpu= works perfectly for this. You may need a *_ok or a *_hw as well (and/or other selectors). > 2) Test code targetting at least power8. But as these tests show, that a lot > of the code won't generate the appropriate instructions on power10. This is > what we have now. It relies on undocumented switches like -mpower9-vector to > add the necessary support. You should simply not run this test on too new systems. You can use dg-skip-if or similar. > 3) Test code targetting at least power8 but go to power9 at the maximum. But why? We will keep testing all interesting CPU / OS combos as long as they are interesting. Segher
Re: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC.
On Thu, May 20, 2021 at 02:25:58PM -0500, will schmidt wrote: > I'd throw the ternary term in there, easier to search for later. > s/?: operations/ternary (?:) operations / Thanks. > So, presumably the float128-minmax-2.c test adds/replaces the power10 > code gen tests that were removed or disabled from float128-minmax.c. Yes. > Probably fine.. It's good to exercise the pragma target stuff, thoguh > I wonder if it would be better to just specify -mcpu=power9 in the > options since we are already specifying (redundant?) -mpower9-vector. > > I see similar changes in a later patch, probably OK there since those > tests do not appear to be specifying -mcpu=foo options that are already > pointed at power9 features... I think we really want a better solution than #pragma, since some systems (AIX if memory serves) might not support #pragma to change code generation models, because they don't have the assembler/linker support for it. Basically for code generation tests, I see the following cases: 1) Test code targetting precisley power8 (or power9, power10), etc. Hopefully these are rare. 2) Test code targetting at least power8. But as these tests show, that a lot of the code won't generate the appropriate instructions on power10. This is what we have now. It relies on undocumented switches like -mpower9-vector to add the necessary support. 3) Test code targetting at least power8 but go to power9 at the maximum. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
Re: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC.
On Tue, 2021-05-18 at 16:26 -0400, Michael Meissner wrote:
> [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC.
>
Hi,
> This patch adds the support for the IEEE 128-bit floating point C minimum and
> maximum instructions. The next patch will add the support for using the
> compare and set mask instruction to implement conditional moves.
>
> This patch does not try to re-use the code used for SF/DF min/max
> support. It defines a separate insn for the IEEE 128-bit support. It
> uses the code iterator to simplify adding both operations.
>
> GCC will not convert ?: operations into using min/max instructions provided in
I'd throw the ternary term in there, easier to search for later.
s/?: operations/ternary (?:) operations /
> this patch unless the user uses -Ofast or similar switches due to issues with
> NaNs. The next patch that adds conditional move instructions will enable the
> ?: conversion in many cases.
>
> I have done bootstrap builds with this patch on the following 3 systems:
> 1)power9 running LE Linux using --with-cpu=power9
> 2)power8 running BE Linux using --with-cpu=power8, testing both
> 32/64-bit.
> 3)power10 prototype running LE Linux using --with-cpu=power10.
>
> There were no regressions to the tests, and the new test added passed. Can I
> check these patches into trunk branch for GCC 12?
>
> I would like to check these patches into GCC 11 after a cooling off period,
> but
> I can also not do the backport if desired.
>
> gcc/
> 2021-05-18 Michael Meissner
>
> * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
> 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp
> instructions.
> * config/rs6000/rs6000.md (s3, IEEE128 iterator):
> New insns.
ok
>
> gcc/testsuite/
> 2021-05-18 Michael Meissner
>
> * gcc.target/powerpc/float128-minmax-2.c: New test.
> * gcc.target/powerpc/float128-minmax.c: Turn off power10 code
> generation.
So, presumably the float128-minmax-2.c test adds/replaces the power10
code gen tests that were removed or disabled from float128-minmax.c.
> ---
> gcc/config/rs6000/rs6000.c| 3 ++-
> gcc/config/rs6000/rs6000.md | 11 +++
> .../gcc.target/powerpc/float128-minmax-2.c| 15 +++
> .../gcc.target/powerpc/float128-minmax.c | 7 +++
> 4 files changed, 35 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
>
> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> index 0d05956..fdaf12aeda0 100644
> --- a/gcc/config/rs6000/rs6000.c
> +++ b/gcc/config/rs6000/rs6000.c
> @@ -16111,7 +16111,8 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx
> op0, rtx op1)
>/* VSX/altivec have direct min/max insns. */
>if ((code == SMAX || code == SMIN)
>&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
> - || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode
> + || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
> + || (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode
> {
>emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
>return;
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 0bfeb24d9e8..3a1bc1f8547 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -5196,6 +5196,17 @@ (define_insn "*s3_vsx"
> }
>[(set_attr "type" "fp")])
>
> +;; Min/max for ISA 3.1 IEEE 128-bit floating point
> +(define_insn "s3"
> + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
> + (fp_minmax:IEEE128
> + (match_operand:IEEE128 1 "altivec_register_operand" "v")
> + (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
> + "TARGET_POWER10"
> + "xscqp %0,%1,%2"
> + [(set_attr "type" "vecfloat")
> + (set_attr "size" "128")])
> +
> ;; The conditional move instructions allow us to perform max and min
> operations
> ;; even when we don't have the appropriate max/min instruction using the FSEL
> ;; instruction.
ok
> diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
> b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
> new file mode 100644
> index 000..c71ba08c9f8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
> @@ -0,0 +1,15 @@
> +/* { dg-require-effective-target ppc_float128_hw } */
> +/* { dg-require-effective-target power10_ok } */
> +/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
> +
> +#ifndef TYPE
> +#define TYPE _Float128
> +#endif
> +
> +/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
> + call. */
> +TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
> +TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
> +
> +/* { dg-final { scan-assembler {\mxsmaxcqp\M}
Re: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC
On Wed, Apr 14, 2021 at 02:15:47PM -0500, Segher Boessenkool wrote: > On Wed, Apr 14, 2021 at 03:09:13PM -0400, Michael Meissner wrote: > > On Tue, Apr 13, 2021 at 05:19:12PM -0500, Segher Boessenkool wrote: > > > > * config/rs6000/rs6.h (FLOAT128_MIN_MAX_FPMASK_P): New > > > > macro. > > > > > > As said in the other mail, don't do the macro; just write its expansion > > > in the single place it is used. > > > > Note, in the first patch it is only used 1 time, but in the second patch it > > is > > used 5 times (4 times in mode iterators in rs6000.md, 1 other use in > > rs6000.c). > > But I will eliminate it, and replicate it in each of the 6 places it is > > used. > > The alternative is to come up with a much better name :-/ I dunno, given the what the macro is used for (i.e. whether we have the IEEE 128-bit minimum, maximum, and floating point compare mask) FLOAT128_MIN_MAX_FPMASK_P meets the definition. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
Re: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC
On Wed, Apr 14, 2021 at 03:09:13PM -0400, Michael Meissner wrote: > On Tue, Apr 13, 2021 at 05:19:12PM -0500, Segher Boessenkool wrote: > > > * config/rs6000/rs6.h (FLOAT128_MIN_MAX_FPMASK_P): New macro. > > > > As said in the other mail, don't do the macro; just write its expansion > > in the single place it is used. > > Note, in the first patch it is only used 1 time, but in the second patch it is > used 5 times (4 times in mode iterators in rs6000.md, 1 other use in > rs6000.c). > But I will eliminate it, and replicate it in each of the 6 places it is used. The alternative is to come up with a much better name :-/ Segher
Re: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC
On Tue, Apr 13, 2021 at 05:19:12PM -0500, Segher Boessenkool wrote: > Hi! > > On Fri, Apr 09, 2021 at 10:42:50AM -0400, Michael Meissner wrote: > > Since then the patch seems to have gone into a limbo state. > > Patches I cannot immediately handle take time, and if they aren't > pinged, they can fall off the map. So a) ping your patches, once a week > for example; and b) write patches that are simpler to review (do not > cost many hours each). > > > gcc/ > > 2021-04-09 Michael Meissner > > > > * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA > > 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions. > > * config/rs6000/rs6.h (FLOAT128_MIN_MAX_FPMASK_P): New macro. > > As said in the other mail, don't do the macro; just write its expansion > in the single place it is used. Note, in the first patch it is only used 1 time, but in the second patch it is used 5 times (4 times in mode iterators in rs6000.md, 1 other use in rs6000.c). But I will eliminate it, and replicate it in each of the 6 places it is used. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
Re: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC
Hi! On Fri, Apr 09, 2021 at 10:42:50AM -0400, Michael Meissner wrote: > Since then the patch seems to have gone into a limbo state. Patches I cannot immediately handle take time, and if they aren't pinged, they can fall off the map. So a) ping your patches, once a week for example; and b) write patches that are simpler to review (do not cost many hours each). > gcc/ > 2021-04-09 Michael Meissner > > * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA > 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions. > * config/rs6000/rs6.h (FLOAT128_MIN_MAX_FPMASK_P): New macro. As said in the other mail, don't do the macro; just write its expansion in the single place it is used. > * config/rs6000/rs6000.md (s3): Add support for the > ISA 3.1 IEEE 128-bit minimum and maximum instructions. And rephrase this, just "New" something. So please resend, taking into account all comments. Segher
Re: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC
Hi! On Fri, Apr 09, 2021 at 11:54:57AM -0500, will schmidt wrote: > On Fri, 2021-04-09 at 10:42 -0400, Michael Meissner wrote: > > * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA > > 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions. > > I don't see any direct reference to xsmaxcqp or xsmincqp with respect > to this change below. > > It looks like this change adds the FLOAT128_MIN_MAX_FPMASK_P (mode) > check > as criteria for emitting some form of a SET instruction. >emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1))); > > Ok, I see it now, the instructions are mildly obfuscated by > "xscqp" as part of the rs6000.md change below. Yeah, that is the downside of using iterators and the like in the machine description. But the upsides of that far outweigh these downsides :-) > > * config/rs6000/rs6.h (FLOAT128_MIN_MAX_FPMASK_P): New macro. > > which is > #define FLOAT128_MIN_MAX_FPMASK_P(MODE) \ > (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (MODE)) > > Are there any non MIN_MAX scenarios that will require the combination > of POWER10,FLOAT128_HW,FLOAT128_IEEE(mode)? I'd wonder if there is a name > not specific to *_MIN_MAX_* that would be a better naming choice. > But, naming is hard. :-) Yes, and for every new macro, the reader will have to understand what it does, what it is for. If you cannot come up with a good name for it (one for which it is immediately obvious to the reader what it *means*), often a good tradeoff is to not make a macro at all, just write out the few words where you need them. > > * config/rs6000/rs6000.md (s3): Add support for the > > ISA 3.1 IEEE 128-bit minimum and maximum instructions. > > I'd move the "xsmaxcqp,xsmincqp" instruction references from the rs6000.c > changelog blurb to this changelog blurb. It should say "New." or "New define_insns." or "New instructions." or similar. The changelog says *what*, not *why*. And it is important that you can find stuff in it using grep or similar. Here it should say "s3 for IEEE128". We actually have some patterns that just say "3", not too useful in a changelog if you do not say what code and mode are! (In this case, it does not help to say what "minmax" is from, it stand for just "min" and "max" after all :-) ) Segher
Re: [PATCH 1/2] Add IEEE 128-bit min/max support on PowerPC
On Fri, 2021-04-09 at 10:42 -0400, Michael Meissner wrote:
> Add IEEE 128-bit min/max support on PowerPC.
>
> This patch has been posted various times in the past. My memory is the last
> time I changed the patch, I addressed the concerns posted at that time. Since
> then the patch seems to have gone into a limbo state.
Hi,
I'll throw some comments at this below, and see if it will trigger more
follow-up.
>
> This patch adds the support for the IEEE 128-bit floating point C minimum and
> maximum instructions. The next patch will add the support for using the
> compare and set mask instruction to implement conditional moves.
>
> Rather than trying to overload the current SF/DF min/max support, it was
> simpler to just provide the new instructions as a separate insn.
>
> I have tested this patch in various little endian and big endian PowerPC
> builds
> since I've posted. It has no regressions, and it adds the instructions if
> -mcpu=power10 is used.
>
> gcc/
> 2021-04-09 Michael Meissner
>
> * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
> 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions.
I don't see any direct reference to xsmaxcqp or xsmincqp with respect
to this change below.
It looks like this change adds the FLOAT128_MIN_MAX_FPMASK_P (mode)
check
as criteria for emitting some form of a SET instruction.
emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
Ok, I see it now, the instructions are mildly obfuscated by
"xscqp" as part of the rs6000.md change below.
> * config/rs6000/rs6.h (FLOAT128_MIN_MAX_FPMASK_P): New macro.
which is
#define FLOAT128_MIN_MAX_FPMASK_P(MODE) \
(TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (MODE))
Are there any non MIN_MAX scenarios that will require the combination
of POWER10,FLOAT128_HW,FLOAT128_IEEE(mode)? I'd wonder if there is a name
not specific to *_MIN_MAX_* that would be a better naming choice.
But, naming is hard. :-)
> * config/rs6000/rs6000.md (s3): Add support for the
> ISA 3.1 IEEE 128-bit minimum and maximum instructions.
I'd move the "xsmaxcqp,xsmincqp" instruction references from the rs6000.c
changelog blurb to this changelog blurb.
I've looked over the rest, no further relevant comments below.
thanks
-Will
>
> gcc/testsuite/
> 2021-04-09 Michael Meissner
>
> * gcc.target/powerpc/float128-minmax-2.c: New test.
> ---
> gcc/config/rs6000/rs6000.c| 3 ++-
> gcc/config/rs6000/rs6000.h| 5 +
> gcc/config/rs6000/rs6000.md | 11 +++
> .../gcc.target/powerpc/float128-minmax-2.c| 15 +++
> 4 files changed, 33 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
>
> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> index 35f5c332c41..e87686c1c4d 100644
> --- a/gcc/config/rs6000/rs6000.c
> +++ b/gcc/config/rs6000/rs6000.c
> @@ -16111,7 +16111,8 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx
> op0, rtx op1)
>/* VSX/altivec have direct min/max insns. */
>if ((code == SMAX || code == SMIN)
>&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
> - || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode
> + || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
> + || FLOAT128_MIN_MAX_FPMASK_P (mode)))
> {
>emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
>return;
ok
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index 233a92baf3c..e3fb0798622 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -345,6 +345,11 @@ extern const char *host_detect_local_cpu (int argc,
> const char **argv);
> || ((MODE) == TDmode) \
> || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
>
> +/* Macro whether the float128 minimum, maximum, and set compare mask
> + instructions are enabled. */
> +#define FLOAT128_MIN_MAX_FPMASK_P(MODE)
> \
> + (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (MODE))
> +
> /* Return true for floating point that does not use a vector register. */
> #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
>(SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
ok
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index c8cdc42533c..17b2fdc1cdd 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -5194,6 +5194,17 @@ (define_insn "*s3_vsx"
> }
>[(set_attr "type" "fp")])
>
> +;; Min/max for ISA 3.1 IEEE 128-bit floating point
> +(define_insn "s3"
> + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
> + (fp_minmax:IEEE128
> + (match_operand:IEEE128 1 "altivec_register_operand" "v")
> +
