Re: gEDA-user: verilog -> gschem
On Jul 8, 2011, at 12:26 PM, Mike Jarabek wrote: > No autorouter is needed... Just place the generated symbols on a grid, so > they don't touch, and add wire stubs to each pin. Each wire should have a > netname attribute attached. No need even for that. No graphics at all are required when you use net= attributes. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: verilog -> gschem
On Jul 8, 2011, at 2:47 PM, wrote: > I have been looking at the gschem file format, seems very > straight forward and I created the symbols for the standard cells in the > verilog netlists. A rats nest is fine, will never edit the schematic of > any file created from the verilog file. I set a message yesterday that's relevant to your approach, but it appears not to have made it to the list. So, I'm resending it to the list and to you. > On Jul 7, 2011, at 4:31 PM, > wrote: > >> I've looked at the mailing list archives and seen people ask but >> haven't seen if anyone has code to take a verilog netlist and create a >> gschem file from it. I don't care about what the schematic looks like, >> can be ugly. I just need to get it into gschem format to run through >> gnetlist to a different netlist format. >> >> Why? Well, I'm getting files from different tools (gschem along with >> tools from other sites) and the common format I can generate is verilog >> which works out well because I'm using icarus verilog for simulation. >> The next step in the process requires running the design through >> gnetlist but since gnetlist only reads gschem files as input I need to >> get the verilog files to gschem to feed gnetlist. > > Well, the back end is easy. See > http://www.gedasymbols.org/user/john_doty/tools/pins2gsch.html. > > This script generates a .sch file that contains connectivity data, but no > useful graphics. The input is a trivial TSV representation of a netlist. > > Given a parser for the input netlist format(s), the same approach could be > used to merge netlists from other sources. Of course, the parser is the > difficult part. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: verilog -> gschem
Hi, (Sorry for the top post) No autorouter is needed... Just place the generated symbols on a grid, so they don't touch, and add wire stubs to each pin. Each wire should have a netname attribute attached. The netlister will connect all similarly named nets together. Any reason you can't just instantiate the verilog from the external sources directly? Or do you desire a flattened netlist for some reason? Thanks, Mike -Original Message- From: Ouabache Designworks Sender: geda-user-boun...@moria.seul.org Date: Fri, 8 Jul 2011 09:43:02 To: Reply-To: gEDA user mailing list Subject: Re: gEDA-user: verilog -> gschem ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: verilog -> gschem
On Jul 7, 2011, at 4:31 PM, wrote: > I've looked at the mailing list archives and seen people ask but > haven't seen if anyone has code to take a verilog netlist and create a > gschem file from it. I don't care about what the schematic looks like, > can be ugly. I just need to get it into gschem format to run through > gnetlist to a different netlist format. > > Why? Well, I'm getting files from different tools (gschem along with > tools from other sites) and the common format I can generate is verilog > which works out well because I'm using icarus verilog for simulation. > The next step in the process requires running the design through > gnetlist but since gnetlist only reads gschem files as input I need to > get the verilog files to gschem to feed gnetlist. Well, the back end is easy. See http://www.gedasymbols.org/user/john_doty/tools/pins2gsch.html. This script generates a .sch file that contains connectivity data, but no useful graphics. The input is a trivial TSV representation of a netlist. Given a parser for the input netlist format(s), the same approach could be used to merge netlists from other sources. Of course, the parser is the difficult part. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: verilog -> gschem
> Original Message > Subject: Re: gEDA-user: verilog -> gschem > From: Steven Michalske > Date: Fri, July 08, 2011 1:46 pm > To: gEDA user mailing list > Will the gentlest backend for verilog accept symbols with the source > attribute set, like hierarchy symbols, but > making them point to Verilog > source not a sch source? > > Steve I could see that being useful, doesn't solve my issue as I need to have the final netlist in bdnet format but the ability to synthesize a block into verilog and reference it in a schematic...actually you can basically do that. Set the 'device' attribute of the symbol to the name of the .v file and make sure the file can be found by icarus or that the device exists in a library file. The verilog netlister (at least when using the geda_hier_tools.bsh script I found in the mailing list archives) will produce a nice verilog file and any symbol with a 'device' attribute is assumed to have a verilog source associated with it as I understand it. I'm doing a standard cell design so I got the verilog library from the fab, I created symbols for the library parts and set 'device' to the cell name as it exists in the library file, 'pinnumber's are set to the port names of each device and it netlists properly (netlist by name, not port order). In icarus I include the library file and UDP file with the verilog netlist from geda_hier_tools.bsh and it runs great. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: verilog -> gschem
> Original Message > Subject: Re: gEDA-user: verilog -> gschem > From: Ouabache Designworks > Date: Fri, July 08, 2011 9:43 am > To: geda-user@moria.seul.org > > > The only difference between that and and PCB layout program is that you > don't care about trace width and you can cross lines without connecting > them. > What you need is a symbol generator ( trivial script) , and autoplacer ( > trivial > unless you want your result to be understandable and easily routed) and > a autorouter ( PHD project and maybe a career). > > You should be able to do a script that generates a graphical rats nest that > had all the correct connections. That should work. > > > John Eaton I can probably do the script but as I am not a s/w guy I was hoping that either someone had one or had started one I could use as a starting point. I have been looking at the gschem file format, seems very straight forward and I created the symbols for the standard cells in the verilog netlists. A rats nest is fine, will never edit the schematic of any file created from the verilog file. As no one seems to have done this I'll have to take a crack at it, seem useful for people combining schematic & verilog and needing to pull it all together to create a final netlist. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: verilog -> gschem
Will the gentlest backend for verilog accept symbols with the source attribute set, like hierarchy symbols, but making them point to Verilog source not a sch source? Steve On Jul 8, 2011, at 1:29 PM, wrote: >> Original Message >> Subject: Re: gEDA-user: verilog -> gschem >> From: John Griessen >> Date: Fri, July 08, 2011 9:27 am >> To: gEDA user mailing list >> >> On 07/07/11 17:31, fr...@frankthomson.net wrote: >>> I just need to get it into gschem format to run through >>> gnetlist to a different netlist format. >> >> There is a gnetlist backend for verilog-ams. >> You don't need to make schematics, just learn >> enough scheme/guile to fix up the exiting >> gnetlist backends for verilog. > > I do not need to generate a verilog netlist, they are already in > verilog, I need to combine circuits from differnt sources for the final > design and as gnetlist doesn't read verilog I need to get everything > into gscheme format. This is basically the path: > > Circuit elements are coming from different sources, software, etc. The > common format we can all use is verilog so we are using that and use > icarus verilog for logic simulation. If we can get the verilog into > gscheme format files I can use gscheme to combine the blocks at the top > level (which also gives us a nice top level drawing) and run the design > through gnetlist to create a bdnet format netllist (I've got the > gnetlist backend mostly working to generate the bdnet format netlist). > > I don't care what the schematics of the files created from the verilog > files looks like, I can create symbols for the top level and we never > need to decend into them. I do have a library of symbols for the > standard cells that will be used in the verilog files and can generate > flat verilog files so I was hoping someone had or had started a script > that can read in a flat verilog file, refer to a directory of symbols to > reference pin locations and create a gscheme file that is correct from a > netlist perspective. I could try to write this but am a h/w guy and only > fair at s/w (which is real obvious when you look at my gnetlist bdnet > backend). > > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: verilog -> gschem
> Original Message > Subject: Re: gEDA-user: verilog -> gschem > From: John Griessen > Date: Fri, July 08, 2011 9:27 am > To: gEDA user mailing list > > On 07/07/11 17:31, fr...@frankthomson.net wrote: >> I just need to get it into gschem format to run through >> gnetlist to a different netlist format. > > There is a gnetlist backend for verilog-ams. > You don't need to make schematics, just learn > enough scheme/guile to fix up the exiting > gnetlist backends for verilog. I do not need to generate a verilog netlist, they are already in verilog, I need to combine circuits from differnt sources for the final design and as gnetlist doesn't read verilog I need to get everything into gscheme format. This is basically the path: Circuit elements are coming from different sources, software, etc. The common format we can all use is verilog so we are using that and use icarus verilog for logic simulation. If we can get the verilog into gscheme format files I can use gscheme to combine the blocks at the top level (which also gives us a nice top level drawing) and run the design through gnetlist to create a bdnet format netllist (I've got the gnetlist backend mostly working to generate the bdnet format netlist). I don't care what the schematics of the files created from the verilog files looks like, I can create symbols for the top level and we never need to decend into them. I do have a library of symbols for the standard cells that will be used in the verilog files and can generate flat verilog files so I was hoping someone had or had started a script that can read in a flat verilog file, refer to a directory of symbols to reference pin locations and create a gscheme file that is correct from a netlist perspective. I could try to write this but am a h/w guy and only fair at s/w (which is real obvious when you look at my gnetlist bdnet backend). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: verilog -> gschem
Message: 1 Date: Thu, 07 Jul 2011 15:31:44 -0700 From: <[1]fr...@frankthomson.net> Subject: gEDA-user: verilog -> gschem To: [2]geda-user@moria.seul.org Message-ID: <[3]20110707153144.97bc9b90117a8175dad249389209a753.5acdf95b97.wbe@e mail04.secureserver.net> Content-Type: text/plain; charset="utf-8" I've looked at the mailing list archives and seen people ask but haven't seen if anyone has code to take a verilog netlist and create a gschem file from it. I don't care about what the schematic looks like, can be ugly. I just need to get it into gschem format to run through gnetlist to a different netlist format. Why? Well, I'm getting files from different tools (gschem along with tools from other sites) and the common format I can generate is verilog which works out well because I'm using icarus verilog for simulation. The next step in the process requires running the design through gnetlist but since gnetlist only reads gschem files as input I need to get the verilog files to gschem to feed gnetlist. -Frank -- The only difference between that and and PCB layout program is that you don't care about trace width and you can cross lines without connecting them. What you need is a symbol generator ( trivial script) , and autoplacer ( trivial unless you want your result to be understandable and easily routed) and a autorouter ( PHD project and maybe a career). You should be able to do a script that generates a graphical rats nest that had all the correct connections. That should work. John Eaton References 1. mailto:fr...@frankthomson.net 2. mailto:geda-user@moria.seul.org 3. mailto:20110707153144.97bc9b90117a8175dad249389209a753.5acdf95b97@email04.secureserver.net ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: verilog -> gschem
On 07/07/11 17:31, fr...@frankthomson.net wrote: I just need to get it into gschem format to run through gnetlist to a different netlist format. There is a gnetlist backend for verilog-ams. You don't need to make schematics, just learn enough scheme/guile to fix up the exiting gnetlist backends for verilog. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
