[gem5-dev] Change in gem5/gem5[master]: arch-riscv: set MaxMiscDestRegs to 2
Alec Roelke has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/23220 ) Change subject: arch-riscv: set MaxMiscDestRegs to 2 .. arch-riscv: set MaxMiscDestRegs to 2 In an earlier patch, the FCSR was split into its two components, FRM and FFLAGS, causing explicit writes to FCSR to incur two CSR writes. With the O3 CPU model, which defers them both to later, this creates a bug where an assertion that the number of CSR writes must be less than MaxMiscDestRegs fails because that constant is 1. This patch sets it to 2 so the O3 CPU is compatible with this scheme. Change-Id: Ic3413738c4eebe9f127980d0d0af5033d18468e7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23220 Reviewed-by: Alec Roelke Maintainer: Alec Roelke Tested-by: kokoro --- M src/arch/riscv/registers.hh 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Alec Roelke: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index 582a6c5..352c600 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -67,7 +67,7 @@ using RiscvISAInst::MaxInstSrcRegs; using RiscvISAInst::MaxInstDestRegs; -const int MaxMiscDestRegs = 1; +const int MaxMiscDestRegs = 2; // Not applicable to RISC-V using VecElem = ::DummyVecElem; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/23220 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic3413738c4eebe9f127980d0d0af5033d18468e7 Gerrit-Change-Number: 23220 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: set MaxMiscDestRegs to 2
Alec Roelke has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/23220 ) Change subject: arch-riscv: set MaxMiscDestRegs to 2 .. arch-riscv: set MaxMiscDestRegs to 2 In an earlier patch, the FCSR was split into its two components, FRM and FFLAGS, causing explicit writes to FCSR to incur two CSR writes. With the O3 CPU model, which defers them both to later, this creates a bug where an assertion that the number of CSR writes must be less than MaxMiscDestRegs fails because that constant is 1. This patch sets it to 2 so the O3 CPU is compatible with this scheme. Change-Id: Ic3413738c4eebe9f127980d0d0af5033d18468e7 --- M src/arch/riscv/registers.hh 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index 582a6c5..352c600 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -67,7 +67,7 @@ using RiscvISAInst::MaxInstSrcRegs; using RiscvISAInst::MaxInstDestRegs; -const int MaxMiscDestRegs = 1; +const int MaxMiscDestRegs = 2; // Not applicable to RISC-V using VecElem = ::DummyVecElem; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/23220 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic3413738c4eebe9f127980d0d0af5033d18468e7 Gerrit-Change-Number: 23220 Gerrit-PatchSet: 1 Gerrit-Owner: Alec Roelke Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: fix GDB register cache
Alec Roelke has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/20028 )
Change subject: arch-riscv: fix GDB register cache
..
arch-riscv: fix GDB register cache
Fixes the definition of the RISC-V GDB register cache. The latest
version, of RISC-V gdb, commit c3eb4078520dad8234ffd7fbf893ac0da23ad3c8,
appears to only accept the 32 integer registers + the PC in the 'g'
packet.
This functions with the Linux toolchain (riscv64-unknown-linux-gnu-*),
but works best with the Newlib toolchain (riscv64-unknown-elf-*).
Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20028
Reviewed-by: Alec Roelke
Reviewed-by: Jason Lowe-Power
Maintainer: Alec Roelke
Tested-by: kokoro
---
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
2 files changed, 5 insertions(+), 27 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Alec Roelke: Looks good to me, but someone else must approve; Looks good
to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index fe339ff..15d47e2 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -167,15 +167,6 @@
for (int i = 0; i < NumIntArchRegs; i++)
r.gpr[i] = context->readIntReg(i);
r.pc = context->pcState().pc();
-for (int i = 0; i < NumFloatRegs; i++)
-r.fpr[i] = context->readFloatReg(i);
-
-r.csr_base = context->readMiscReg(0);
-r.fflags = context->readMiscReg(CSR_FFLAGS);
-r.frm = context->readMiscReg(CSR_FRM);
-r.fcsr = context->readMiscReg(CSR_FCSR);
-for (int i = ExplicitCSRs; i < NumMiscRegs; i++)
-r.csr[i - ExplicitCSRs] = context->readMiscReg(i);
}
void
@@ -185,15 +176,6 @@
for (int i = 0; i < NumIntArchRegs; i++)
context->setIntReg(i, r.gpr[i]);
context->pcState(r.pc);
-for (int i = 0; i < NumFloatRegs; i++)
-context->setFloatReg(i, r.fpr[i]);
-
-context->setMiscReg(0, r.csr_base);
-context->setMiscReg(CSR_FFLAGS, r.fflags);
-context->setMiscReg(CSR_FRM, r.frm);
-context->setMiscReg(CSR_FCSR, r.fcsr);
-for (int i = ExplicitCSRs; i < NumMiscRegs; i++)
-context->setMiscReg(i, r.csr[i - ExplicitCSRs]);
}
BaseGdbRegCache*
diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index 7fcb28d..02f68d2 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -50,9 +50,12 @@
class RemoteGDB : public BaseRemoteGDB
{
protected:
-static const int ExplicitCSRs = 4;
+static const int NumGDBRegs = 4162;
+static const int NumCSRs = 4096;
bool acc(Addr addr, size_t len);
+// A breakpoint will be 2 bytes if it is compressed and 4 if not
+bool checkBpLen(size_t len) override { return len == 2 || len == 4; }
class RiscvGdbRegCache : public BaseGdbRegCache
{
@@ -61,14 +64,7 @@
struct {
uint64_t gpr[NumIntArchRegs];
uint64_t pc;
-uint64_t fpr[NumFloatRegs];
-
-uint64_t csr_base;
-uint32_t fflags;
-uint32_t frm;
-uint32_t fcsr;
-uint64_t csr[NumMiscRegs - ExplicitCSRs];
-} __attribute__((__packed__)) r;
+} r;
public:
char *data() const { return (char *)&r; }
size_t size() const { return sizeof(r); }
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41
Gerrit-Change-Number: 20028
Gerrit-PatchSet: 4
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: fix GDB register cache
Hello kokoro, Alec Roelke, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/20028 to look at the new patch set (#3). Change subject: arch-riscv: fix GDB register cache .. arch-riscv: fix GDB register cache Fixes the definition of the RISC-V GDB register cache. The latest version, of RISC-V gdb, commit c3eb4078520dad8234ffd7fbf893ac0da23ad3c8, appears to only accept the 32 integer registers + the PC in the 'g' packet. This functions with the Linux toolchain (riscv64-unknown-linux-gnu-*), but works best with the Newlib toolchain (riscv64-unknown-elf-*). Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41 --- M src/arch/riscv/remote_gdb.cc M src/arch/riscv/remote_gdb.hh 2 files changed, 5 insertions(+), 27 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/20028 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41 Gerrit-Change-Number: 20028 Gerrit-PatchSet: 3 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: kokoro Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: fix GDB register cache
Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/20028 ) Change subject: arch-riscv: fix GDB register cache .. arch-riscv: fix GDB register cache Fixes the definition of the RISC-V GDB register cache. The latest version, of RISC-V gdb, commit c3eb4078520dad8234ffd7fbf893ac0da23ad3c8, appears to only accept the 32 integer registers + the PC in the 'g' packet. This functions with the Linux toolchain (riscv64-unknown-linux-gnu-*), but works best with the Newlib toolchain (riscv64-unknown-elf-*). Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41 --- M src/arch/riscv/remote_gdb.cc M src/arch/riscv/remote_gdb.hh 2 files changed, 10 insertions(+), 25 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/20028 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41 Gerrit-Change-Number: 20028 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: fix GDB register cache
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/20028 )
Change subject: arch-riscv: fix GDB register cache
..
arch-riscv: fix GDB register cache
Fixes the definition of the RISC-V GDB register cache. The latest
version, commit c3eb4078520dad8234ffd7fbf893ac0da23ad3c8, appears to
only accept the 32 integer registers + the PC in the 'g' packet.
Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41
---
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
2 files changed, 13 insertions(+), 22 deletions(-)
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index fe339ff..be93dc4 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -169,13 +169,11 @@
r.pc = context->pcState().pc();
for (int i = 0; i < NumFloatRegs; i++)
r.fpr[i] = context->readFloatReg(i);
-
-r.csr_base = context->readMiscReg(0);
-r.fflags = context->readMiscReg(CSR_FFLAGS);
-r.frm = context->readMiscReg(CSR_FRM);
-r.fcsr = context->readMiscReg(CSR_FCSR);
-for (int i = ExplicitCSRs; i < NumMiscRegs; i++)
-r.csr[i - ExplicitCSRs] = context->readMiscReg(i);
+for (int i = 0; i < NumCSRs; i++)
+r.csr[i] = 0;
+for (auto&& csrdata : CSRData)
+r.csr[csrdata.first] =
context->readMiscReg(csrdata.second.physIndex);
+r.priv = context->readMiscReg(MISCREG_PRV);
}
void
@@ -187,13 +185,9 @@
context->pcState(r.pc);
for (int i = 0; i < NumFloatRegs; i++)
context->setFloatReg(i, r.fpr[i]);
-
-context->setMiscReg(0, r.csr_base);
-context->setMiscReg(CSR_FFLAGS, r.fflags);
-context->setMiscReg(CSR_FRM, r.frm);
-context->setMiscReg(CSR_FCSR, r.fcsr);
-for (int i = ExplicitCSRs; i < NumMiscRegs; i++)
-context->setMiscReg(i, r.csr[i - ExplicitCSRs]);
+for (auto&& csrdata : CSRData)
+context->setMiscReg(csrdata.second.physIndex,
r.csr[csrdata.first]);
+context->setMiscReg(MISCREG_PRV, r.priv);
}
BaseGdbRegCache*
diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index 7fcb28d..c4e018b 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -50,7 +50,8 @@
class RemoteGDB : public BaseRemoteGDB
{
protected:
-static const int ExplicitCSRs = 4;
+static const int NumGDBRegs = 4162;
+static const int NumCSRs = 4096;
bool acc(Addr addr, size_t len);
@@ -62,13 +63,9 @@
uint64_t gpr[NumIntArchRegs];
uint64_t pc;
uint64_t fpr[NumFloatRegs];
-
-uint64_t csr_base;
-uint32_t fflags;
-uint32_t frm;
-uint32_t fcsr;
-uint64_t csr[NumMiscRegs - ExplicitCSRs];
-} __attribute__((__packed__)) r;
+uint64_t csr[NumCSRs];
+uint64_t priv;
+} r;
public:
char *data() const { return (char *)&r; }
size_t size() const { return sizeof(r); }
--
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Gerrit-Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41
Gerrit-Change-Number: 20028
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Implement MHARTID CSR
Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16988 )
Change subject: arch-riscv: Implement MHARTID CSR
..
arch-riscv: Implement MHARTID CSR
This patch implements the MHARTID CSR by intercepting attempts to access
it, similar to the way accesses to the performance counters are
intercepted, to return the thread's context ID.
Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16988
Reviewed-by: Alec Roelke
Reviewed-by: Jason Lowe-Power
Maintainer: Alec Roelke
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/isa.cc
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Alec Roelke: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 4e36d55..cc86752 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -112,6 +112,8 @@
ISA::readMiscReg(int misc_reg, ThreadContext *tc)
{
switch (misc_reg) {
+ case MISCREG_HARTID:
+return tc->contextId();
case MISCREG_CYCLE:
if (hpmCounterEnabled(MISCREG_CYCLE)) {
DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",
--
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Gerrit-Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d
Gerrit-Change-Number: 16988
Gerrit-PatchSet: 4
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Implement MHARTID CSR
Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/16988 ) Change subject: arch-riscv: Implement MHARTID CSR .. arch-riscv: Implement MHARTID CSR This patch implements the MHARTID CSR by intercepting attempts to access it, similar to the way accesses to the performance counters are intercepted, to return the thread's context ID. Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d --- M src/arch/riscv/isa.cc 1 file changed, 2 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16988 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d Gerrit-Change-Number: 16988 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Implement MHARTID CSR
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16988
Change subject: arch-riscv: Implement MHARTID CSR
..
arch-riscv: Implement MHARTID CSR
This patch implements the MHARTID CSR by intercepting attempts to access
it, similar to the way accesses to the performance counters are
intercepted, to return the thread's ID.
Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d
---
M src/arch/riscv/isa.cc
1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 4e36d55..c95a8e9 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -112,6 +112,8 @@
ISA::readMiscReg(int misc_reg, ThreadContext *tc)
{
switch (misc_reg) {
+ case MISCREG_HARTID:
+return tc->threadId();
case MISCREG_CYCLE:
if (hpmCounterEnabled(MISCREG_CYCLE)) {
DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",
--
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Gerrit-Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d
Gerrit-Change-Number: 16988
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add interrupt handling
ding HPM counters
// As a placeholder, all HPM counters are just cycle counters
@@ -175,7 +181,16 @@
// Ignore writes to HPM counters for now
warn("Ignoring write to %s.\n", CSRData.at(misc_reg).name);
} else {
-setMiscRegNoEffect(misc_reg, val);
+switch (misc_reg) {
+ case MISCREG_IP:
+return tc->getCpuPtr()->getInterruptController(tc->threadId())
+ ->setIP(val);
+ case MISCREG_IE:
+return tc->getCpuPtr()->getInterruptController(tc->threadId())
+ ->setIE(val);
+ default:
+setMiscRegNoEffect(misc_reg, val);
+}
}
}
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index e9539fe..b2f8ee4 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -256,11 +256,25 @@
} else {
DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n",
data,
CSRData.at(csr).name);
+INTERRUPT oldinterrupt = olddata;
+INTERRUPT newinterrupt = data;
switch (csr) {
case CSR_FCSR:
xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4,
0));
xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
break;
+ case CSR_MIP: case CSR_MIE:
+if (oldinterrupt.mei == newinterrupt.mei &&
+oldinterrupt.mti == newinterrupt.mti &&
+oldinterrupt.msi == newinterrupt.msi) {
+
xc->setMiscReg(CSRData.at(csr).physIndex,data);
+} else {
+std::string error = "Interrupt m bits are "
+"read-only\n";
+fault =
make_shared(error,
+
machInst);
+}
+break;
default:
xc->setMiscReg(CSRData.at(csr).physIndex,
data);
break;
--
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Gerrit-Change-Number: 14377
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Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Robert Scheffel
Gerrit-Reviewer: Tuan Ta
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Fix reset function and style
Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/14376 )
Change subject: arch-riscv: Fix reset function and style
..
arch-riscv: Fix reset function and style
In addition to fixing some style issues with resetting, this patch fixes
what happens on reset. The RISC-V privileged ISA reference manual says
that,
on reset:
1. Privilege mode is set to M
2. mstatus.mie <- 0; mstatus.mprv <- 0
3. PC <- reset vector
4. mcause <- reset cause (0 if there is no distinguishing causes)
5. Everything else is undefined
Because of 5, everything else will be left alone
Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8
Reviewed-on: https://gem5-review.googlesource.com/c/14376
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
2 files changed, 14 insertions(+), 16 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index b5f3d07..a151334 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -131,6 +131,13 @@
tc->clearArchRegs();
}
+tc->setMiscReg(MISCREG_PRV, PRV_M);
+STATUS status = tc->readMiscReg(MISCREG_STATUS);
+status.mie = 0;
+status.mprv = 0;
+tc->setMiscReg(MISCREG_STATUS, status);
+tc->setMiscReg(MISCREG_MCAUSE, 0);
+
// Advance the PC to the implementation-defined reset vector
PCState pc = static_cast*>(tc->getSystemPtr())->resetVect();
tc->pcState(pc);
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index d9cb44c..2176f88 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -95,24 +95,15 @@
class Reset : public FaultBase
{
+ private:
+const FaultName _name;
-public:
-Reset()
-: _name("reset")
-{}
+ public:
+Reset() : _name("reset") {}
+FaultName name() const override { return _name; }
-FaultName
-name() const override
-{
-return _name;
-}
-
-void
-invoke(ThreadContext *tc, const StaticInstPtr &inst =
-StaticInst::nullStaticInstPtr) override;
-
-private:
-const FaultName _name;
+void invoke(ThreadContext *tc, const StaticInstPtr &inst =
+StaticInst::nullStaticInstPtr) override;
};
class InstFault : public RiscvFault
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8
Gerrit-Change-Number: 14376
Gerrit-PatchSet: 3
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Robert Scheffel
Gerrit-Reviewer: Tuan Ta
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Fix reset function and style
Hello Tuan Ta, Alec Roelke, Robert Scheffel, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14376 to look at the new patch set (#2). Change subject: arch-riscv: Fix reset function and style .. arch-riscv: Fix reset function and style In addition to fixing some style issues with resetting, this patch fixes what happens on reset. The RISC-V privileged ISA reference manual says that, on reset: 1. Privilege mode is set to M 2. mstatus.mie <- 0; mstatus.mprv <- 0 3. PC <- reset vector 4. mcause <- reset cause (0 if there is no distinguishing causes) 5. Everything else is undefined Because of 5, everything else will be left alone Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8 --- M src/arch/riscv/faults.cc M src/arch/riscv/faults.hh 2 files changed, 14 insertions(+), 16 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14376 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8 Gerrit-Change-Number: 14376 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add interrupt handling
Hello Gabe Black, Tuan Ta, Jason Lowe-Power, Robert Scheffel, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14377 to look at the new patch set (#2). Change subject: arch-riscv: Add interrupt handling .. arch-riscv: Add interrupt handling Implement the Interrupts SimObject for RISC-V. This basically just handles setting and getting the values of the interrupt-pending and interrupt-enable CSRs according to the privileged ISA reference chapter 3.1.14. Note that it does NOT implement the PLIC as defined in chapter 7, as that is used for handling external interrupts which are defined based on peripherals that are available. Change-Id: Ia1321430f870ff5a3950217266fde0511332485b --- M src/arch/riscv/faults.cc M src/arch/riscv/faults.hh M src/arch/riscv/interrupts.hh M src/arch/riscv/isa.cc M src/arch/riscv/isa/formats/standard.isa 5 files changed, 146 insertions(+), 47 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14377 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ia1321430f870ff5a3950217266fde0511332485b Gerrit-Change-Number: 14377 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Fix reset function and style
Hello Alec Roelke,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/14376
to review the following change.
Change subject: arch-riscv: Fix reset function and style
..
arch-riscv: Fix reset function and style
In addition to fixing some style issues with resetting, this patch fixes
what happens on reset. The RISC-V privileged ISA reference manual says that,
on reset:
1. Privilege mode is set to M
2. mstatus.mie <- 0; mstatus.mprv <- 0
3. PC <- reset vector
4. mcause <- reset cause (0 if there is no distinguishing causes)
5. Everything else is undefined
Because of 5, everything else will be left alone
Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8
---
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/interrupts.hh
3 files changed, 41 insertions(+), 51 deletions(-)
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index b5f3d07..5f949b3 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -126,10 +126,12 @@
void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
-if (FullSystem) {
-tc->getCpuPtr()->clearInterrupts(tc->threadId());
-tc->clearArchRegs();
-}
+tc->setMiscReg(MISCREG_PRV, PRV_M);
+STATUS status = tc->readMiscReg(MISCREG_STATUS);
+status.mie = 0;
+status.mprv = 0;
+tc->setMiscReg(MISCREG_STATUS, status);
+tc->setMiscReg(MISCREG_MCAUSE, 0);
// Advance the PC to the implementation-defined reset vector
PCState pc = static_cast*>(tc->getSystemPtr())->resetVect();
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index d9cb44c..2176f88 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -95,24 +95,15 @@
class Reset : public FaultBase
{
+ private:
+const FaultName _name;
-public:
-Reset()
-: _name("reset")
-{}
+ public:
+Reset() : _name("reset") {}
+FaultName name() const override { return _name; }
-FaultName
-name() const override
-{
-return _name;
-}
-
-void
-invoke(ThreadContext *tc, const StaticInstPtr &inst =
-StaticInst::nullStaticInstPtr) override;
-
-private:
-const FaultName _name;
+void invoke(ThreadContext *tc, const StaticInstPtr &inst =
+StaticInst::nullStaticInstPtr) override;
};
class InstFault : public RiscvFault
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index 60a5b5b..f593eb6 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -55,36 +55,34 @@
return dynamic_cast(_params);
}
-Interrupts(Params * p) : SimObject(p), cpu(nullptr)
-{}
+Interrupts(Params * p) : SimObject(p), cpu(nullptr) {}
-void
-setCPU(BaseCPU * _cpu)
-{
-cpu = _cpu;
-}
-
-void
-post(int int_num, int index)
-{
-panic("Interrupts::post not implemented.\n");
-}
-
-void
-clear(int int_num, int index)
-{
-panic("Interrupts::clear not implemented.\n");
-}
-
-void
-clearAll()
-{
-warn_once("Interrupts::clearAll not implemented.\n");
-}
+void setCPU(BaseCPU * _cpu) { cpu = _cpu; }
bool
checkInterrupts(ThreadContext *tc) const
{
+return tc->readMiscReg(MISCREG_IP) != 0;
+}
+
+Fault
+getInterrupt(ThreadContext *tc)
+{
+assert(checkInterrupts(tc));
+panic("Interrupts::getInterrupt not implemented.\n");
+}
+
+void
+updateIntrInfo(ThreadContext *tc)
+{
+panic("Interrupts::updateIntrInfo not implemented.\n");
+}
+
+// Deprecated but still necessary for compatibility
+
+void
+post(int int_num, int index)
+{
warn_once("Interrupts::checkInterrupts just rudimentary
implemented");
/**
* read the machine interrupt register in order to check if
interrupts
@@ -98,17 +96,16 @@
return false;
}
-Fault
-getInterrupt(ThreadContext *tc)
+void
+clear(int int_num, int index)
{
-assert(checkInterrupts(tc));
-panic("Interrupts::getInterrupt not implemented.\n");
+panic("Interrupts::clear not implemented.\n");
}
void
-updateIntrInfo(ThreadContext *tc)
+clearAll()
{
-panic("Interrupts::updateIntrInfo not implemented.\n");
+panic("Interrupts::clearAll not implemented.\n");
}
};
--
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add interrupt handling
switch (csr) {
case CSR_FCSR:
xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4,
0));
xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
break;
+ case CSR_MIP: case CSR_MIE:
+if (oldinterrupt.mei == newinterrupt.mei &&
+oldinterrupt.mti == newinterrupt.mti &&
+oldinterrupt.msi == newinterrupt.msi) {
+
xc->setMiscReg(CSRData.at(csr).physIndex,data);
+} else {
+std::string error = "Interrupt m bits are "
+"read-only\n";
+fault =
make_shared(error,
+
machInst);
+}
+break;
default:
xc->setMiscReg(CSRData.at(csr).physIndex,
data);
break;
--
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Gerrit-Branch: master
Gerrit-Change-Id: Ia1321430f870ff5a3950217266fde0511332485b
Gerrit-Change-Number: 14377
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add xret instructions
call,
No_OpClass);
0x1: ebreak({{
fault =
make_shared(xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
-0x100: eret({{
-fault = make_shared("eret",
-machInst);
-}}, No_OpClass);
+0x2: uret({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+status.uie = status.upie;
+status.upie = 1;
+xc->setMiscReg(MISCREG_STATUS, status);
+NPC = xc->readMiscReg(MISCREG_UEPC);
+}}, IsReturn);
+0x102: sret({{
+if (xc->readMiscReg(MISCREG_PRV) == PRV_U) {
+fault = make_shared(
+"sret in user mode", machInst);
+NPC = NPC;
+} else {
+STATUS status =
xc->readMiscReg(MISCREG_STATUS);
+xc->setMiscReg(MISCREG_PRV, status.spp);
+status.sie = status.spie;
+status.spie = 1;
+status.spp = PRV_U;
+xc->setMiscReg(MISCREG_STATUS, status);
+NPC = xc->readMiscReg(MISCREG_SEPC);
+}
+}}, IsReturn);
+0x302: mret({{
+if (xc->readMiscReg(MISCREG_PRV) != PRV_M) {
+fault = make_shared(
+"mret at lower privilege",
machInst);
+NPC = NPC;
+} else {
+STATUS status =
xc->readMiscReg(MISCREG_STATUS);
+xc->setMiscReg(MISCREG_PRV, status.mpp);
+status.mie = status.mpie;
+status.mpie = 1;
+status.mpp = PRV_U;
+xc->setMiscReg(MISCREG_STATUS, status);
+NPC = xc->readMiscReg(MISCREG_MEPC);
+}
+}}, IsReturn);
}
}
format CSROp {
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index e1d57ee..bd95cf8 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -583,6 +583,53 @@
{CSR_DSCRATCH, {"dscratch", MISCREG_DSCRATCH}}
};
+/**
+ * These fields are specified in the RISC-V Instruction Set Manual, Volume
II,
+ * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register
that
+ * uses these fields is the MSTATUS register, which is shadowed by two
others
+ * accessible at lower privilege levels (SSTATUS and USTATUS) that can't
see
+ * the fields for higher privileges.
+ */
+BitUnion64(STATUS)
+Bitfield<63> sd;
+Bitfield<35, 34> sxl;
+Bitfield<33, 32> uxl;
+Bitfield<22> tsr;
+Bitfield<21> tw;
+Bitfield<20> tvm;
+Bitfield<19> mxr;
+Bitfield<18> sum;
+Bitfield<17> mprv;
+Bitfield<16, 15> xs;
+Bitfield<14, 13> fs;
+Bitfield<12, 11> mpp;
+Bitfield<8> spp;
+Bitfield<7> mpie;
+Bitfield<5> spie;
+Bitfield<4> upie;
+Bitfield<3> mie;
+Bitfield<1> sie;
+Bitfield<0> uie;
+EndBitUnion(STATUS)
+
+/**
+ * These fields are specified in the RISC-V Instruction Set Manual, Volume
II,
+ * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the
MIP
+ * and MIE registers have the same fields, so accesses to either should use
+ * this bit union.
+ */
+BitUnion64(INTERRUPT)
+Bitfield<11> mei;
+Bitfield<9> sei;
+Bitfield<8> uei;
+Bitfield<7> mti;
+Bitfield<5> sti;
+Bitfield<4> uti;
+Bitfield<3> msi;
+Bitfield<1> ssi;
+Bitfield<0> usi;
+EndBitUnion(INTERRUPT)
+
const off_t MXL_OFFSET = (sizeof(MiscReg) * 8 - 2);
const off_t SXL_OFFSET = 34;
const off_t UXL_OFFSET = 32;
--
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Gerrit-Change-Number: 11136
Gerrit-PatchSet: 6
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Robert Scheffel
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add support for trap value register
machInst);
}
uint32_t temp;
float fs1 = reinterpret_cast(temp = Fs1_bits);
@@ -1277,7 +1297,8 @@
}}, FloatCvtOp);
0x2c: fsqrt_s({{
if (RS2 != 0) {
-fault = make_shared("source reg
x1");
+fault = make_shared("source reg
x1",
+ machInst);
}
uint32_t temp;
float fs1 = reinterpret_cast(temp = Fs1_bits);
@@ -1291,7 +1312,8 @@
}}, FloatSqrtOp);
0x2d: fsqrt_d({{
if (RS2 != 0) {
-fault = make_shared("source reg
x1");
+fault = make_shared("source reg
x1",
+ machInst);
}
Fd = sqrt(Fs1);
}}, FloatSqrtOp);
@@ -1690,10 +1712,11 @@
}}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
No_OpClass);
0x1: ebreak({{
-fault = make_shared();
+fault =
make_shared(xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
0x100: eret({{
-fault = make_shared("eret");
+fault = make_shared("eret",
+machInst);
}}, No_OpClass);
}
}
diff --git a/src/arch/riscv/isa/formats/fp.isa
b/src/arch/riscv/isa/formats/fp.isa
index 1f08ca5..5f06721 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -57,7 +57,7 @@
break;
case 0x4:
// Round to nearest, ties to max magnitude not implemented
-fault = make_shared(ROUND_MODE);
+fault = make_shared(ROUND_MODE, machInst);
break;
case 0x7: {
uint8_t frm = xc->readMiscReg(MISCREG_FRM);
@@ -76,16 +76,17 @@
break;
case 0x4:
// Round to nearest, ties to max magnitude not
implemented
-fault = make_shared(ROUND_MODE);
+fault = make_shared(ROUND_MODE,
machInst);
break;
default:
-fault = std::make_shared(frm);
+fault = std::make_shared(frm,
machInst);
break;
}
break;
}
default:
-fault = std::make_shared(ROUND_MODE);
+fault = std::make_shared(ROUND_MODE,
+ machInst);
break;
}
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index e69ad7e..e9539fe 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -231,7 +231,7 @@
olddata = xc->readMiscReg(CSRData.at(csr).physIndex);
} else {
std::string error = csprintf("Illegal CSR index %#x\n",
csr);
-fault = make_shared(error);
+fault = make_shared(error, machInst);
olddata = 0;
}
break;
@@ -252,7 +252,7 @@
if (bits(csr, 11, 10) == 0x3) {
std::string error = csprintf("CSR %s is
read-only\n",
CSRData.at(csr).name);
-fault = make_shared(error);
+fault = make_shared(error,
machInst);
} else {
DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n",
data,
CSRData.at(csr).name);
--
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add support for fault handling
{}
-void
-invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
};
class IllegalInstFault : public RiscvFault
{
private:
const std::string reason;
+
public:
IllegalInstFault(std::string r)
-: RiscvFault("Illegal instruction", INST_ILLEGAL, SOFTWARE),
- reason(r)
+: RiscvFault("Illegal instruction", false, INST_ILLEGAL)
{}
-void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
};
class UnimplementedFault : public RiscvFault
{
private:
const std::string instName;
+
public:
UnimplementedFault(std::string name)
-: RiscvFault("Unimplemented instruction", INST_ILLEGAL, SOFTWARE),
-instName(name)
+: RiscvFault("Unimplemented instruction", false, INST_ILLEGAL),
+ instName(name)
{}
-void
-invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
};
class IllegalFrmFault: public RiscvFault
{
private:
const uint8_t frm;
+
public:
IllegalFrmFault(uint8_t r)
-: RiscvFault("Illegal floating-point rounding mode", INST_ILLEGAL,
-SOFTWARE),
-frm(r)
+: RiscvFault("Illegal floating-point rounding mode", false,
+ INST_ILLEGAL),
+ frm(r)
{}
-void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
};
class BreakpointFault : public RiscvFault
{
public:
-BreakpointFault() : RiscvFault("Breakpoint", BREAKPOINT, SOFTWARE)
-{}
-
-void
-invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+BreakpointFault() : RiscvFault("Breakpoint", false, BREAKPOINT) {}
+void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
};
class SyscallFault : public RiscvFault
@@ -195,11 +222,8 @@
public:
// TODO: replace ECALL_USER with the appropriate privilege level of the
// caller
-SyscallFault() : RiscvFault("System call", ECALL_USER, SOFTWARE)
-{}
-
-void
-invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+SyscallFault() : RiscvFault("System call", false, ECALL_USER) {}
+void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
};
} // namespace RiscvISA
--
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add support for trap value register
Hello Jason Lowe-Power, Alec Roelke, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/11135 to look at the new patch set (#4). Change subject: arch-riscv: Add support for trap value register .. arch-riscv: Add support for trap value register RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 --- M src/arch/riscv/faults.cc M src/arch/riscv/faults.hh M src/arch/riscv/insts/unknown.hh M src/arch/riscv/isa/decoder.isa M src/arch/riscv/isa/formats/fp.isa M src/arch/riscv/isa/formats/standard.isa 6 files changed, 110 insertions(+), 48 deletions(-) -- To view, visit https://gem5-review.googlesource.com/11135 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Gerrit-Change-Number: 11135 Gerrit-PatchSet: 4 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add xret instructions
Hello Robert Scheffel, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/11136 to look at the new patch set (#4). Change subject: arch-riscv: Add xret instructions .. arch-riscv: Add xret instructions This patch adds the uret, sret, and mret instructions for use with returning from user-, supervisor-, and machine-level code, respectively. These instructions read the STATUS register to determine the previous privilege level and modify it to re-enable interrupts at the old privilege level. These instructions can only be executed at the corresponding privilege level or higher. Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9 --- M src/arch/riscv/faults.hh M src/arch/riscv/isa/decoder.isa M src/arch/riscv/registers.hh 3 files changed, 110 insertions(+), 58 deletions(-) -- To view, visit https://gem5-review.googlesource.com/11136 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9 Gerrit-Change-Number: 11136 Gerrit-PatchSet: 4 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Robert Scheffel Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add xret instructions
Hello Robert Scheffel, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/11136 to look at the new patch set (#3). Change subject: arch-riscv: Add xret instructions .. arch-riscv: Add xret instructions This patch adds the uret, sret, and mret instructions for use with returning from user-, supervisor-, and machine-level code, respectively. These instructions read the STATUS register to determine the previous privilege level and modify it to re-enable interrupts at the old privilege level. These instructions can only be executed at the corresponding privilege level or higher. Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9 --- M src/arch/riscv/faults.hh M src/arch/riscv/isa/decoder.isa M src/arch/riscv/registers.hh 3 files changed, 91 insertions(+), 56 deletions(-) -- To view, visit https://gem5-review.googlesource.com/11136 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9 Gerrit-Change-Number: 11136 Gerrit-PatchSet: 3 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Robert Scheffel Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add support for trap value register
Alec Roelke has uploaded a new patch set (#3). ( https://gem5-review.googlesource.com/11135 ) Change subject: arch-riscv: Add support for trap value register .. arch-riscv: Add support for trap value register RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 --- M src/arch/riscv/faults.cc M src/arch/riscv/faults.hh M src/arch/riscv/insts/unknown.hh M src/arch/riscv/isa/decoder.isa M src/arch/riscv/isa/formats/fp.isa M src/arch/riscv/isa/formats/standard.isa 6 files changed, 109 insertions(+), 61 deletions(-) -- To view, visit https://gem5-review.googlesource.com/11135 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Gerrit-Change-Number: 11135 Gerrit-PatchSet: 3 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add support for fault handling
Alec Roelke has uploaded a new patch set (#7) to the change originally created by Alec Roelke. ( https://gem5-review.googlesource.com/9161 ) Change subject: arch-riscv: Add support for fault handling .. arch-riscv: Add support for fault handling This patch adds support for handling RISC-V faults, including tracking current and previous execution privilege, correctly switching to the privilege mode specified by CSRs, and setting/storing the PC. It also includes changes introduced by patch #9821, which disables interrupts during handling of a fault. Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9 --- M src/arch/riscv/faults.cc M src/arch/riscv/faults.hh 2 files changed, 160 insertions(+), 74 deletions(-) -- To view, visit https://gem5-review.googlesource.com/9161 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9 Gerrit-Change-Number: 9161 Gerrit-PatchSet: 7 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-CC: Christian Menard Gerrit-CC: Gabe Black Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add support for trap value register
Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/11135 ) Change subject: arch-riscv: Add support for trap value register .. arch-riscv: Add support for trap value register RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 --- M src/arch/riscv/faults.cc M src/arch/riscv/faults.hh M src/arch/riscv/insts/unknown.hh M src/arch/riscv/isa/decoder.isa M src/arch/riscv/isa/formats/fp.isa M src/arch/riscv/isa/formats/standard.isa 6 files changed, 109 insertions(+), 47 deletions(-) -- To view, visit https://gem5-review.googlesource.com/11135 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Gerrit-Change-Number: 11135 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add support for fault handling
Alec Roelke has uploaded a new patch set (#6) to the change originally created by Alec Roelke. ( https://gem5-review.googlesource.com/9161 ) Change subject: arch-riscv: Add support for fault handling .. arch-riscv: Add support for fault handling This patch adds support for handling RISC-V faults, including tracking current and previous execution privilege, correctly switching to the privilege mode specified by CSRs, and setting/storing the PC. It also includes changes introduced by patch #9821, which disables interrupts during handling of a fault. Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9 --- M src/arch/riscv/faults.cc M src/arch/riscv/faults.hh 2 files changed, 147 insertions(+), 74 deletions(-) -- To view, visit https://gem5-review.googlesource.com/9161 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9 Gerrit-Change-Number: 9161 Gerrit-PatchSet: 6 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-CC: Christian Menard Gerrit-CC: Gabe Black Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add support for trap value register
fault = make_shared("source reg
x1",
+ machInst);
}
uint32_t temp;
float fs1 = reinterpret_cast(temp = Fs1_bits);
@@ -1291,7 +1312,8 @@
}}, FloatSqrtOp);
0x2d: fsqrt_d({{
if (RS2 != 0) {
-fault = make_shared("source reg
x1");
+fault = make_shared("source reg
x1",
+ machInst);
}
Fd = sqrt(Fs1);
}}, FloatSqrtOp);
@@ -1690,10 +1712,11 @@
}}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
No_OpClass);
0x1: ebreak({{
-fault = make_shared();
+fault =
make_shared(xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
0x100: eret({{
-fault = make_shared("eret");
+fault = make_shared("eret",
+machInst);
}}, No_OpClass);
}
}
diff --git a/src/arch/riscv/isa/formats/fp.isa
b/src/arch/riscv/isa/formats/fp.isa
index 1f08ca5..5f06721 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -57,7 +57,7 @@
break;
case 0x4:
// Round to nearest, ties to max magnitude not implemented
-fault = make_shared(ROUND_MODE);
+fault = make_shared(ROUND_MODE, machInst);
break;
case 0x7: {
uint8_t frm = xc->readMiscReg(MISCREG_FRM);
@@ -76,16 +76,17 @@
break;
case 0x4:
// Round to nearest, ties to max magnitude not
implemented
-fault = make_shared(ROUND_MODE);
+fault = make_shared(ROUND_MODE,
machInst);
break;
default:
-fault = std::make_shared(frm);
+fault = std::make_shared(frm,
machInst);
break;
}
break;
}
default:
-fault = std::make_shared(ROUND_MODE);
+fault = std::make_shared(ROUND_MODE,
+ machInst);
break;
}
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index e69ad7e..e9539fe 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -231,7 +231,7 @@
olddata = xc->readMiscReg(CSRData.at(csr).physIndex);
} else {
std::string error = csprintf("Illegal CSR index %#x\n",
csr);
-fault = make_shared(error);
+fault = make_shared(error, machInst);
olddata = 0;
}
break;
@@ -252,7 +252,7 @@
if (bits(csr, 11, 10) == 0x3) {
std::string error = csprintf("CSR %s is
read-only\n",
CSRData.at(csr).name);
-fault = make_shared(error);
+fault = make_shared(error,
machInst);
} else {
DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n",
data,
CSRData.at(csr).name);
--
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add xret instructions
} else {
+STATUS status =
xc->readMiscReg(MISCREG_STATUS);
+xc->setMiscReg(MISCREG_PRV, status.spp);
+status.sie = status.spie;
+status.spie = 1;
+status.spp = PRV_U;
+xc->setMiscReg(MISCREG_STATUS, status);
+NPC = xc->readMiscReg(MISCREG_SEPC);
+}
+}}, IsReturn);
+0x302: mret({{
+if (xc->readMiscReg(MISCREG_PRV) != PRV_M) {
+fault = make_shared(
+"mret at lower privilege",
machInst);
+NPC = NPC;
+} else {
+STATUS status =
xc->readMiscReg(MISCREG_STATUS);
+xc->setMiscReg(MISCREG_PRV, status.mpp);
+status.mie = status.mpie;
+status.mpie = 1;
+status.mpp = PRV_U;
+xc->setMiscReg(MISCREG_STATUS, status);
+NPC = xc->readMiscReg(MISCREG_MEPC);
+}
+}}, IsReturn);
}
}
format CSROp {
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index e1d57ee..9247ebf 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -583,6 +583,40 @@
{CSR_DSCRATCH, {"dscratch", MISCREG_DSCRATCH}}
};
+BitUnion64(STATUS)
+Bitfield<63> sd;
+Bitfield<35, 34> sxl;
+Bitfield<33, 32> uxl;
+Bitfield<22> tsr;
+Bitfield<21> tw;
+Bitfield<20> tvm;
+Bitfield<19> mxr;
+Bitfield<18> sum;
+Bitfield<17> mprv;
+Bitfield<16, 15> xs;
+Bitfield<14, 13> fs;
+Bitfield<12, 11> mpp;
+Bitfield<8> spp;
+Bitfield<7> mpie;
+Bitfield<5> spie;
+Bitfield<4> upie;
+Bitfield<3> mie;
+Bitfield<1> sie;
+Bitfield<0> uie;
+EndBitUnion(STATUS)
+
+BitUnion64(INTERRUPT)
+Bitfield<11> mei;
+Bitfield<9> sei;
+Bitfield<9> uei;
+Bitfield<7> mti;
+Bitfield<5> sti;
+Bitfield<4> uti;
+Bitfield<3> msi;
+Bitfield<1> ssi;
+Bitfield<0> usi;
+EndBitUnion(INTERRUPT)
+
const off_t MXL_OFFSET = (sizeof(MiscReg) * 8 - 2);
const off_t SXL_OFFSET = 34;
const off_t UXL_OFFSET = 32;
--
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add support for fault handling
Alec Roelke has uploaded a new patch set (#5) to the change originally created by Alec Roelke. ( https://gem5-review.googlesource.com/9161 ) Change subject: arch-riscv: Add support for fault handling .. arch-riscv: Add support for fault handling This patch adds support for handling RISC-V faults, including tracking current and previous execution privilege, correctly switching to the privilege mode specified by CSRs, and setting/storing the PC. It also includes changes introduced by patch #9821, which disables interrupts during handling of a fault. Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9 --- M src/arch/riscv/faults.cc M src/arch/riscv/faults.hh 2 files changed, 147 insertions(+), 74 deletions(-) -- To view, visit https://gem5-review.googlesource.com/9161 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9 Gerrit-Change-Number: 9161 Gerrit-PatchSet: 5 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-CC: Christian Menard Gerrit-CC: Gabe Black Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add support for fault handling
Hello Tuan Ta, Robert Scheffel, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/9161 to look at the new patch set (#4). Change subject: arch-riscv: Add support for fault handling .. arch-riscv: Add support for fault handling This patch adds support for handling RISC-V faults, including tracking current and previous execution privilege, correctly switching to the privilege mode specified by CSRs, and setting/storing the PC. It also includes changes introduced by patch #9821, which disables interrupts during handling of a fault. Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9 --- M src/arch/riscv/faults.cc M src/arch/riscv/faults.hh 2 files changed, 122 insertions(+), 72 deletions(-) -- To view, visit https://gem5-review.googlesource.com/9161 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9 Gerrit-Change-Number: 9161 Gerrit-PatchSet: 4 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-CC: Christian Menard Gerrit-CC: Gabe Black Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Update CSR implementations
off_t FRM_OFFSET = 5; + +const MiscReg ISA_MXL_MASK = 3ULL << MXL_OFFSET; +const MiscReg ISA_EXT_MASK = mask(26); +const MiscReg MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK; + +const MiscReg STATUS_SD_MASK = 1ULL << ((sizeof(MiscReg) * 8) - 1); +const MiscReg STATUS_SXL_MASK = 3ULL << SXL_OFFSET; +const MiscReg STATUS_UXL_MASK = 3ULL << UXL_OFFSET; +const MiscReg STATUS_TSR_MASK = 1ULL << 22; +const MiscReg STATUS_TW_MASK = 1ULL << 21; +const MiscReg STATUS_TVM_MASK = 1ULL << 20; +const MiscReg STATUS_MXR_MASK = 1ULL << 19; +const MiscReg STATUS_SUM_MASK = 1ULL << 18; +const MiscReg STATUS_MPRV_MASK = 1ULL << 17; +const MiscReg STATUS_XS_MASK = 3ULL << 15; +const MiscReg STATUS_FS_MASK = 3ULL << FS_OFFSET; +const MiscReg STATUS_MPP_MASK = 3ULL << 11; +const MiscReg STATUS_SPP_MASK = 1ULL << 8; +const MiscReg STATUS_MPIE_MASK = 1ULL << 7; +const MiscReg STATUS_SPIE_MASK = 1ULL << 5; +const MiscReg STATUS_U
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Update CSR implementations
Hello Gabe Black, Tuan Ta, Robert Scheffel, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/7441 to look at the new patch set (#9). Change subject: arch-riscv: Update CSR implementations .. arch-riscv: Update CSR implementations This patch updates the CSRs to match the RISC-V privileged specification version 1.10. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Performance counters are also not yet implemented, as they do not have specifications. Currently they act as cycle counters. Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers based on privilege will come in a future patch. Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a --- M src/arch/riscv/insts/standard.cc M src/arch/riscv/isa.cc M src/arch/riscv/isa.hh M src/arch/riscv/isa/decoder.isa M src/arch/riscv/isa/formats/standard.isa M src/arch/riscv/isa/includes.isa M src/arch/riscv/process.cc M src/arch/riscv/registers.hh M src/arch/riscv/remote_gdb.cc 9 files changed, 738 insertions(+), 425 deletions(-) -- To view, visit https://gem5-review.googlesource.com/7441 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Gerrit-Change-Number: 7441 Gerrit-PatchSet: 9 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Update CSR implementations
Hello Gabe Black, Tuan Ta, Robert Scheffel, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/7441 to look at the new patch set (#8). Change subject: arch-riscv: Update CSR implementations .. arch-riscv: Update CSR implementations This patch updates the CSRs to match the RISC-V privileged specification version 1.10. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Performance counters are also not yet implemented, as they do not have specifications. Currently they act as cycle counters. Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers will come in a future patch. Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a --- M src/arch/riscv/insts/standard.cc M src/arch/riscv/isa.cc M src/arch/riscv/isa.hh M src/arch/riscv/isa/formats/fp.isa M src/arch/riscv/process.cc M src/arch/riscv/registers.hh M src/arch/riscv/remote_gdb.cc 7 files changed, 884 insertions(+), 404 deletions(-) -- To view, visit https://gem5-review.googlesource.com/7441 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Gerrit-Change-Number: 7441 Gerrit-PatchSet: 8 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Update CSR implementations
Hello Gabe Black, Tuan Ta, Robert Scheffel, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/7441 to look at the new patch set (#7). Change subject: arch-riscv: Update CSR implementations .. arch-riscv: Update CSR implementations This patch updates the CSRs to match the RISC-V privileged specification version 1.10. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Supervisor mode will only be supported in FS mode, so S-mode registers are guarded by checks that the system is in FS mode. Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers will come in a future patch. Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a --- M src/arch/riscv/insts/standard.cc M src/arch/riscv/isa.cc M src/arch/riscv/isa.hh M src/arch/riscv/isa/formats/fp.isa M src/arch/riscv/registers.hh M src/arch/riscv/remote_gdb.cc 6 files changed, 880 insertions(+), 404 deletions(-) -- To view, visit https://gem5-review.googlesource.com/7441 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Gerrit-Change-Number: 7441 Gerrit-PatchSet: 7 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Update CSR implementations
Hello Gabe Black, Tuan Ta, Robert Scheffel, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/7441 to look at the new patch set (#6). Change subject: arch-riscv: Update CSR implementations .. arch-riscv: Update CSR implementations This patch updates the CSRs to match the RISC-V privileged specification version 1.10. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Supervisor mode will only be supported in FS mode, so S-mode registers are guarded by checks that the system is in FS mode. Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers will come in a future patch. Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a --- M src/arch/riscv/insts/standard.cc M src/arch/riscv/isa.cc M src/arch/riscv/isa.hh M src/arch/riscv/isa/formats/fp.isa M src/arch/riscv/registers.hh M src/arch/riscv/remote_gdb.cc 6 files changed, 886 insertions(+), 404 deletions(-) -- To view, visit https://gem5-review.googlesource.com/7441 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Gerrit-Change-Number: 7441 Gerrit-PatchSet: 6 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Update CSR implementations
Hello Tuan Ta, Robert Scheffel, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/7441 to look at the new patch set (#5). Change subject: arch-riscv: Update CSR implementations .. arch-riscv: Update CSR implementations This patch updates the CSRs to match the RISC-V privileged specification version 1.10. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Supervisor mode will only be supported in FS mode, so S-mode registers are guarded by checks that the system is in FS mode. Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers will come in a future patch. Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a --- M src/arch/riscv/insts/standard.cc M src/arch/riscv/isa.cc M src/arch/riscv/isa.hh M src/arch/riscv/isa/formats/fp.isa M src/arch/riscv/registers.hh M src/arch/riscv/remote_gdb.cc 6 files changed, 837 insertions(+), 404 deletions(-) -- To view, visit https://gem5-review.googlesource.com/7441 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Gerrit-Change-Number: 7441 Gerrit-PatchSet: 5 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Add support for fault handling
ction", false, INST_ILLEGAL)
{}
void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
@@ -133,25 +115,26 @@
{
private:
const std::string instName;
+
public:
UnimplementedFault(std::string name)
-: RiscvFault("Unimplemented instruction", INST_ILLEGAL, SOFTWARE),
-instName(name)
+: RiscvFault("Unimplemented instruction", false, INST_ILLEGAL),
+ instName(name)
{}
-void
-invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
};
class IllegalFrmFault: public RiscvFault
{
private:
const uint8_t frm;
+
public:
IllegalFrmFault(uint8_t r)
-: RiscvFault("Illegal floating-point rounding mode", INST_ILLEGAL,
-SOFTWARE),
-frm(r)
+: RiscvFault("Illegal floating-point rounding mode", false,
+ INST_ILLEGAL),
+ frm(r)
{}
void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
@@ -160,11 +143,8 @@
class BreakpointFault : public RiscvFault
{
public:
-BreakpointFault() : RiscvFault("Breakpoint", BREAKPOINT, SOFTWARE)
-{}
-
-void
-invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+BreakpointFault() : RiscvFault("Breakpoint", false, BREAKPOINT) {}
+void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
};
class SyscallFault : public RiscvFault
@@ -172,11 +152,8 @@
public:
// TODO: replace ECALL_USER with the appropriate privilege level of the
// caller
-SyscallFault() : RiscvFault("System call", ECALL_USER, SOFTWARE)
-{}
-
-void
-invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+SyscallFault() : RiscvFault("System call", false, ECALL_USER) {}
+void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
};
} // namespace RiscvISA
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 71d8cef..8aa64b3 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -80,6 +80,9 @@
sstatus.fs = 0x1;
sstatus.uxl = 0x2;
}
+
+// 0x0 = user; 0x1 = supervisor; 0x3 = machine
+miscRegFile[MISCREG_PRV] = 0x3;
}
bool
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 874f923..121c909 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -83,7 +83,7 @@
// This has to be one to prevent warnings that are treated as errors
const unsigned NumVecRegs = 1;
const int NumCCRegs = 0;
-const int NumMiscRegs = 4096;
+const int NumMiscRegs = 4097;
// Semantically meaningful register indices
const int ZeroReg = 0;
@@ -193,7 +193,11 @@
MISCREG_TDATA3 = 0x7A3,
MISCREG_DCSR = 0x7B0,
MISCREG_DPC = 0x7B1,
-MISCREG_DSCRATCH = 0x7B2
+MISCREG_DSCRATCH = 0x7B2,
+
+// This register should not be accessible by software; to accomplish
that,
+// its index lies outside the range of possible 12-bit values
+MISCREG_PRV = 0x1000
};
const std::map MiscRegNames = {
--
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Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke
Gerrit-MessageType: newchange
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Update CSR implementations
Hello Tuan Ta, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/7441 to look at the new patch set (#2). Change subject: arch-riscv: Update CSR implementations .. arch-riscv: Update CSR implementations This patch updates the CSRs to match the RISC-V privileged specification version 1.10. It only modifies their initial values. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Supervisor mode will only be supported in FS mode, so S-mode registers are guarded by checks that the system is in FS mode. Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers and register fields will come in a future patch. Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a --- M src/arch/riscv/isa.cc M src/arch/riscv/isa.hh M src/arch/riscv/registers.hh 3 files changed, 292 insertions(+), 182 deletions(-) -- To view, visit https://gem5-review.googlesource.com/7441 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Gerrit-Change-Number: 7441 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Tuan Ta ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Update CSR implementations
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/7441
Change subject: arch-riscv: Update CSR implementations
..
arch-riscv: Update CSR implementations
This patch updates the CSRs to match the RISC-V privileged specification
version 1.10. It only modifies their initial values for SE mode, so only
U- and M-mode registers are implemented. As interrupts, faults, and
privilege levels are not yet supported, there are no meaninful side
effects that are implemented.
Note that even though S-mode is not implemented, placeholders for S-mode
registers are still included for future use (namely, FS mode).
Note also that this implementation trusts software to use the registers
properly. Access protection, readability, and writeability of registers
and register fields will come in a future patch.
Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
3 files changed, 252 insertions(+), 182 deletions(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 6091068..b9e9c95 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -64,9 +64,19 @@
miscRegFile[MISCREG_MVENDORID] = 0;
miscRegFile[MISCREG_MARCHID] = 0;
miscRegFile[MISCREG_MIMPID] = 0;
-miscRegFile[MISCREG_MISA] = 0x80101129ULL;
+miscRegFile[MISCREG_MCOUNTEREN] = 0x7;
+
+misa.mxl = 0x2;
+misa.extensions = 0x10112D;
+mstatus.fs = 0x1;
+mstatus.uxl = 0x2;
}
+bool
+ISA::hpmCounterEnabled(int misc_reg) const
+{
+return (miscRegFile[MISCREG_MCOUNTEREN] & (1ULL << (misc_reg & 0x1F)))
0;
+}
MiscReg
ISA::readMiscRegNoEffect(int misc_reg) const
@@ -74,31 +84,47 @@
DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
switch (misc_reg) {
+ case MISCREG_MISA:
+return misa;
+ case MISCREG_MHARTID:
+warn("Use readMiscReg to read the mhartid CSR.");
+return 0;
+ case MISCREG_MSTATUS:
+return mstatus;
+ case MISCREG_MCYCLE:
+ case MISCREG_CYCLE:
+warn("Use readMiscReg to read the cycle CSR.");
+return 0;
+ case MISCREG_TIME:
+if (!hpmCounterEnabled(MISCREG_TIME)) {
+warn("CSR %s is not enabled.\n", MiscRegNames.at(misc_reg));
+return 0;
+}
+return std::time(nullptr);
+ case MISCREG_MINSTRET:
+ case MISCREG_INSTRET:
+warn("Use readMiscReg to read the instret CSR.");
+return 0;
+ case MISCREG_MCYCLEH:
+ case MISCREG_CYCLEH:
+warn("Use readMiscReg to read the cycleh CSR.");
+return 0;
+ case MISCREG_TIMEH:
+if (!hpmCounterEnabled(MISCREG_TIMEH)) {
+warn("CSR %s is not enabled.\n", MiscRegNames.at(misc_reg));
+return 0;
+}
+return std::time(nullptr) >> 32;
+ case MISCREG_MINSTRETH:
+ case MISCREG_INSTRETH:
+warn("Use readMiscReg to read the instreth CSR.");
+return 0;
case MISCREG_FFLAGS:
return bits(miscRegFile[MISCREG_FCSR], 4, 0);
case MISCREG_FRM:
return bits(miscRegFile[MISCREG_FCSR], 7, 5);
case MISCREG_FCSR:
return bits(miscRegFile[MISCREG_FCSR], 31, 0);
- case MISCREG_CYCLE:
-warn("Use readMiscReg to read the cycle CSR.");
-return 0;
- case MISCREG_TIME:
-return std::time(nullptr);
- case MISCREG_INSTRET:
-warn("Use readMiscReg to read the instret CSR.");
-return 0;
- case MISCREG_CYCLEH:
-warn("Use readMiscReg to read the cycleh CSR.");
-return 0;
- case MISCREG_TIMEH:
-return std::time(nullptr) >> 32;
- case MISCREG_INSTRETH:
-warn("Use readMiscReg to read the instreth CSR.");
-return 0;
- case MISCREG_MHARTID:
-warn("Use readMiscReg to read the mhartid CSR.");
-return 0;
default:
return miscRegFile[misc_reg];
}
@@ -108,24 +134,44 @@
ISA::readMiscReg(int misc_reg, ThreadContext *tc)
{
switch (misc_reg) {
- case MISCREG_INSTRET:
-DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
-MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
-return tc->getCpuPtr()->totalInsts();
+ case MISCREG_MHARTID:
+return tc->cpuId() * tc->getCpuPtr()->numThreads + tc->threadId();
+ case MISCREG_MCYCLE:
case MISCREG_CYCLE:
DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
+if (!hpmCounterEnabled(misc_reg)) {
+warn("CSR %s is not enabled.\n", MiscRegNames.at(misc_reg));
+return 0;
+}
return tc->getCpuPtr()->curCycle();
- case MISCREG_INSTRETH:
+ case MISCREG_MINSTRET:
+ case MISCREG_INSTRET:
DPR
[gem5-dev] Change in public/gem5[master]: arch-riscv: Fix floating-poing op classes
ase FP_SUBNORMAL:
if (signbit(Fs1)) {
Rd = 1 << 2;
} else {
Rd = 1 << 5;
}
break;
-case FP_NORMAL:
+ case FP_NORMAL:
if (signbit(Fs1)) {
Rd = 1 << 1;
} else {
Rd = 1 << 6;
}
break;
-default:
+ default:
panic("Unknown classification for operand.");
break;
}
-}});
+}}, FloatMiscOp);
}
0x78: fmv_s_x({{
Fd_bits = (uint64_t)Rs1_uw;
--
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Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb
Gerrit-Change-Number: 6521
Gerrit-PatchSet: 5
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tuan Ta
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Fix floating-point conversion bugs
ublic/gem5 Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id983906ea0664dc246e115a9e470d9ab7733bde1 Gerrit-Change-Number: 6402 Gerrit-PatchSet: 4 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tuan Ta ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Fix floating-poing op classes
Hello Tuan Ta, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6521 to look at the new patch set (#3). Change subject: arch-riscv: Fix floating-poing op classes .. arch-riscv: Fix floating-poing op classes This patch applies correct miscellaneous or multiply-accumulate op classes to floating point instructions which had previously been incorrectly classed as add or multiply instructions. Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb --- M src/arch/riscv/isa/decoder.isa 1 file changed, 32 insertions(+), 32 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6521 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb Gerrit-Change-Number: 6521 Gerrit-PatchSet: 3 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tuan Ta ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Don't crash when printing unknown CSRs
Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/7321 )
Change subject: arch-riscv: Don't crash when printing unknown CSRs
..
arch-riscv: Don't crash when printing unknown CSRs
This patch fixes a potential crash if an unnamed CSR is accessed and
debug flags are enabled that print disassembly. Unknown CSRs will be
identified as "??" followed by the address that was used.
Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef
Reviewed-on: https://gem5-review.googlesource.com/7321
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Alec Roelke
---
M src/arch/riscv/insts/standard.cc
1 file changed, 5 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
Alec Roelke: Looks good to me, approved
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
index bcf0741..60cf4fc 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -60,7 +60,11 @@
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
if (_numSrcRegs > 0)
ss << registerName(_srcRegIdx[0]) << ", ";
-ss << MiscRegNames.at(csr);
+auto name = MiscRegNames.find(csr);
+if (name != MiscRegNames.end())
+ss << name->second;
+else
+ss << "?? (" << hex << "0x" << csr << ")";
return ss.str();
}
--
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Gerrit-Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef
Gerrit-Change-Number: 7321
Gerrit-PatchSet: 3
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Don't crash when printing unknown CSRs
Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/7321 ) Change subject: arch-riscv: Don't crash when printing unknown CSRs .. arch-riscv: Don't crash when printing unknown CSRs This patch fixes a potential crash if an unnamed CSR is accessed and debug flags are enabled that print disassembly. Unknown CSRs will be identified as "??" followed by the address that was used. Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef --- M src/arch/riscv/insts/standard.cc 1 file changed, 5 insertions(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/7321 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef Gerrit-Change-Number: 7321 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-CC: Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Don't crash when printing unknown CSRs
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/7321
Change subject: arch-riscv: Don't crash when printing unknown CSRs
..
arch-riscv: Don't crash when printing unknown CSRs
This patch fixes a potential crash if an unnamed CSR is accessed and
debug flags are enabled that print disassembly. Unknown CSRs will be
identified as "??" followed by the address that was used.
Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef
---
M src/arch/riscv/insts/standard.cc
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
index bcf0741..73f3bb8 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -60,7 +60,10 @@
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
if (_numSrcRegs > 0)
ss << registerName(_srcRegIdx[0]) << ", ";
-ss << MiscRegNames.at(csr);
+if (MiscRegNames.count(csr) > 0)
+ss << MiscRegNames.at(csr);
+else
+ss << "?? (" << hex << "0x" << csr << ")";
return ss.str();
}
--
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Gerrit-Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef
Gerrit-Change-Number: 7321
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Change AMO request flags
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/7181
Change subject: arch-riscv: Change AMO request flags
..
arch-riscv: Change AMO request flags
This patch adds the LOCKED_RMW flag to atomic memory operations to
ensure that they are atomic. It does not change their memory ordering
flags.
Change-Id: Ibc01091f83e3ff7c5b1e6153beb62291eba9dde4
---
M src/arch/riscv/isa/formats/amo.isa
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/arch/riscv/isa/formats/amo.isa
b/src/arch/riscv/isa/formats/amo.isa
index e3be237..241dab4 100644
--- a/src/arch/riscv/isa/formats/amo.isa
+++ b/src/arch/riscv/isa/formats/amo.isa
@@ -43,8 +43,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst);
-protected:
-
+ protected:
class %(class_name)sLoad : public %(base_class)sMicro
{
public:
@@ -101,8 +100,9 @@
%(constructor)s;
flags[IsFirstMicroop] = true;
flags[IsDelayedCommit] = true;
+memAccessFlags = memAccessFlags | Request::LOCKED_RMW;
if (AQ)
-memAccessFlags = Request::ACQUIRE;
+memAccessFlags = memAccessFlags | Request::ACQUIRE;
}
}};
@@ -114,8 +114,9 @@
%(constructor)s;
flags[IsLastMicroop] = true;
flags[IsNonSpeculative] = true;
+memAccessFlags = memAccessFlags | Request::LOCKED_RMW;
if (RL)
-memAccessFlags = Request::RELEASE;
+memAccessFlags = memAccessFlags | Request::RELEASE;
}
}};
--
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Gerrit-Change-Id: Ibc01091f83e3ff7c5b1e6153beb62291eba9dde4
Gerrit-Change-Number: 7181
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Fix floating-point op classes
Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/6521 ) Change subject: arch-riscv: Fix floating-point op classes .. arch-riscv: Fix floating-point op classes This patch applies correct miscellaneous or multiply-accumulate op classes to floating point instructions which had previously been incorrectly classed as add or multiply instructions. Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb --- M src/arch/riscv/isa/decoder.isa 1 file changed, 32 insertions(+), 32 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6521 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb Gerrit-Change-Number: 6521 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Correct syscall argument reg count
Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/7081 )
Change subject: arch-riscv: Correct syscall argument reg count
..
arch-riscv: Correct syscall argument reg count
As per the discussion in patch #6904 and the Linux 4.15 kernel code for
RISC-V, RISC-V has 7 system call argument registers, x10 through x16 (a0
through a6), with x17 (a7) being used for the system call number.
Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809
Reviewed-on: https://gem5-review.googlesource.com/7081
Reviewed-by: Jason Lowe-Power
Reviewed-by: Tuan Ta
Maintainer: Alec Roelke
---
M src/arch/riscv/registers.hh
1 file changed, 4 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve
Tuan Ta: Looks good to me, approved
Alec Roelke: Looks good to me, approved
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 01e3859..a61554c 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -97,6 +97,10 @@
const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
const int AMOTempReg = 32;
+const int SyscallPseudoReturnReg = 10;
+const std::vector SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
+const int SyscallNumReg = 17;
+
const std::vector IntRegNames = {
"zero", "ra", "sp", "gp",
"tp", "t0", "t1", "t2",
@@ -118,10 +122,6 @@
"ft8", "ft9", "ft10", "ft11"
};
-const int SyscallNumReg = 17;
-const std::vector SyscallArgumentRegs = {10, 11, 12, 13};
-const int SyscallPseudoReturnReg = 10;
-
enum MiscRegIndex {
MISCREG_USTATUS = 0x000,
MISCREG_UIE = 0x004,
--
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Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809
Gerrit-Change-Number: 7081
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tuan Ta
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Correct syscall argument reg count
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/7081
Change subject: arch-riscv: Correct syscall argument reg count
..
arch-riscv: Correct syscall argument reg count
As per the discussion in patch #6904 and the Linux 4.15 kernel code for
RISC-V, RISC-V has 7 system call argument registers, x10 through x16 (a0
through a6), with x17 (a7) being used for the system call number.
Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809
---
M src/arch/riscv/registers.hh
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 01e3859..a61554c 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -97,6 +97,10 @@
const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
const int AMOTempReg = 32;
+const int SyscallPseudoReturnReg = 10;
+const std::vector SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
+const int SyscallNumReg = 17;
+
const std::vector IntRegNames = {
"zero", "ra", "sp", "gp",
"tp", "t0", "t1", "t2",
@@ -118,10 +122,6 @@
"ft8", "ft9", "ft10", "ft11"
};
-const int SyscallNumReg = 17;
-const std::vector SyscallArgumentRegs = {10, 11, 12, 13};
-const int SyscallPseudoReturnReg = 10;
-
enum MiscRegIndex {
MISCREG_USTATUS = 0x000,
MISCREG_UIE = 0x004,
--
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Remove "magic" syscall number constant
Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/7061 )
Change subject: arch-riscv: Remove "magic" syscall number constant
..
arch-riscv: Remove "magic" syscall number constant
getSyscallArg() in RISC-V has an explicit check to make sure that the
register index is within the bounds of the system call register indices
vector. This patch fixes it so that it uses SyscallArgumentRegs.size()
rather than a "magic" constant that has to be updated every time
SyscallArgumentRegs is changed.
Change-Id: I2935d811177dc8028cb3df64b250ba997bc970d8
Reviewed-on: https://gem5-review.googlesource.com/7061
Reviewed-by: Jason Lowe-Power
Maintainer: Alec Roelke
---
M src/arch/riscv/process.cc
1 file changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Alec Roelke: Looks good to me, approved
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 6fe935c..b4fe1ee 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -215,10 +215,10 @@
RiscvISA::IntReg
RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
{
-// RISC-V only has four system call argument registers by convention,
so
-// if a larger index is requested return 0
+// If a larger index is requested than there are syscall argument
+// registers, return 0
RiscvISA::IntReg retval = 0;
-if (i < 4)
+if (i < SyscallArgumentRegs.size())
retval = tc->readIntReg(SyscallArgumentRegs[i]);
i++;
return retval;
--
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Gerrit-Change-Id: I2935d811177dc8028cb3df64b250ba997bc970d8
Gerrit-Change-Number: 7061
Gerrit-PatchSet: 2
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Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Remove "magic" syscall number constant
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/7061
Change subject: arch-riscv: Remove "magic" syscall number constant
..
arch-riscv: Remove "magic" syscall number constant
getSyscallArg() in RISC-V has an explicit check to make sure that the
register index is within the bounds of the system call register indices
vector. This patch fixes it so that it uses SyscallArgumentRegs.size()
rather than a "magic" constant that has to be updated every time
SyscallArgumentRegs is changed.
Change-Id: I2935d811177dc8028cb3df64b250ba997bc970d8
---
M src/arch/riscv/process.cc
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 6fe935c..b4fe1ee 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -215,10 +215,10 @@
RiscvISA::IntReg
RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
{
-// RISC-V only has four system call argument registers by convention,
so
-// if a larger index is requested return 0
+// If a larger index is requested than there are syscall argument
+// registers, return 0
RiscvISA::IntReg retval = 0;
-if (i < 4)
+if (i < SyscallArgumentRegs.size())
retval = tc->readIntReg(SyscallArgumentRegs[i]);
i++;
return retval;
--
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Define AT_RANDOM properly
Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/6681 )
Change subject: arch-riscv: Define AT_RANDOM properly
..
arch-riscv: Define AT_RANDOM properly
According to the getauxval(3) man page, the AT_RANDOM aux value should
be a pointer to 16 random bytes. In the initial implementation of
RISC-V, this was based on spike's program stack setup, which copied the
program header table there instead. This patch changes the
implementation to use the proper 16 random bytes, making it compatible
with some RISC-V programs that use custom linker scripts.
Change-Id: Idaae7f19bf3ed3fd06d293e5e9c0b6f778270eb2
Reviewed-on: https://gem5-review.googlesource.com/6681
Reviewed-by: Jason Lowe-Power
Maintainer: Alec Roelke
---
M src/arch/riscv/process.cc
1 file changed, 11 insertions(+), 10 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Alec Roelke: Looks good to me, approved
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 371a8e4..6fe935c 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -44,6 +45,7 @@
#include "base/loader/elf_object.hh"
#include "base/loader/object_file.hh"
#include "base/logging.hh"
+#include "base/random.hh"
#include "cpu/thread_context.hh"
#include "debug/Stack.hh"
#include "mem/page_table.hh"
@@ -81,6 +83,8 @@
template void
RiscvProcess::argsInit(int pageSize)
{
+const int RandomBytes = 16;
+
updateBias();
objFile->loadSections(initVirtMem);
ElfObject* elfObject = dynamic_cast(objFile);
@@ -88,7 +92,7 @@
// Determine stack size and populate auxv
Addr stack_top = memState->getStackMin();
-stack_top -= elfObject->programHeaderSize();
+stack_top -= RandomBytes;
for (const string& arg: argv)
stack_top -= arg.size() + 1;
for (const string& env: envp)
@@ -114,15 +118,12 @@
allocateMem(roundDown(stack_top, pageSize),
roundUp(memState->getStackSize(), pageSize));
-// Copy program headers to stack
-memState->setStackMin(memState->getStackMin() -
-elfObject->programHeaderSize());
-uint8_t* phdr = new uint8_t[elfObject->programHeaderSize()];
-initVirtMem.readBlob(elfObject->programHeaderTable(), phdr,
-elfObject->programHeaderSize());
-initVirtMem.writeBlob(memState->getStackMin(), phdr,
-elfObject->programHeaderSize());
-delete phdr;
+// Copy random bytes (for AT_RANDOM) to stack
+memState->setStackMin(memState->getStackMin() - RandomBytes);
+uint8_t at_random[RandomBytes];
+generate(begin(at_random), end(at_random),
+ [&]{ return random_mt.random(0, 0xFF); });
+initVirtMem.writeBlob(memState->getStackMin(), at_random, RandomBytes);
// Copy argv to stack
vector argPointers;
--
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Gerrit-Change-Number: 6681
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Define AT_RANDOM properly
Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/6681 ) Change subject: arch-riscv: Define AT_RANDOM properly .. arch-riscv: Define AT_RANDOM properly According to the getauxval(3) man page, the AT_RANDOM aux value should be a pointer to 16 random bytes. In the initial implementation of RISC-V, this was based on spike's program stack setup, which copied the program header table there instead. This patch changes the implementation to use the proper 16 random bytes, making it compatible with some RISC-V programs that use custom linker scripts. Change-Id: Idaae7f19bf3ed3fd06d293e5e9c0b6f778270eb2 --- M src/arch/riscv/process.cc 1 file changed, 11 insertions(+), 10 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6681 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idaae7f19bf3ed3fd06d293e5e9c0b6f778270eb2 Gerrit-Change-Number: 6681 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-CC: Jason Lowe-Power ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Define AT_RANDOM properly
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6681
Change subject: arch-riscv: Define AT_RANDOM properly
..
arch-riscv: Define AT_RANDOM properly
According to the getauxval(3) man page, the AT_RANDOM aux value should
be a pointer to 16 random bytes. In the initial implementation of
RISC-V, this was based on spike's program stack setup, which copied the
program header table there instead. This patch changes the
implementation to use the proper 16 random bytes, making it compatible
with some RISC-V programs that use custom linker scripts.
Change-Id: Idaae7f19bf3ed3fd06d293e5e9c0b6f778270eb2
---
M src/arch/riscv/process.cc
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 371a8e4..5a0ee8c 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -35,7 +35,9 @@
#include
#include
+#include
#include
+#include
#include
#include
#include
@@ -81,6 +83,8 @@
template void
RiscvProcess::argsInit(int pageSize)
{
+const int RandomBytes = 16;
+
updateBias();
objFile->loadSections(initVirtMem);
ElfObject* elfObject = dynamic_cast(objFile);
@@ -88,7 +92,7 @@
// Determine stack size and populate auxv
Addr stack_top = memState->getStackMin();
-stack_top -= elfObject->programHeaderSize();
+stack_top -= RandomBytes;
for (const string& arg: argv)
stack_top -= arg.size() + 1;
for (const string& env: envp)
@@ -114,15 +118,12 @@
allocateMem(roundDown(stack_top, pageSize),
roundUp(memState->getStackSize(), pageSize));
-// Copy program headers to stack
-memState->setStackMin(memState->getStackMin() -
-elfObject->programHeaderSize());
-uint8_t* phdr = new uint8_t[elfObject->programHeaderSize()];
-initVirtMem.readBlob(elfObject->programHeaderTable(), phdr,
-elfObject->programHeaderSize());
-initVirtMem.writeBlob(memState->getStackMin(), phdr,
-elfObject->programHeaderSize());
-delete phdr;
+// Copy random bytes (for AT_RANDOM) to stack
+memState->setStackMin(memState->getStackMin() - RandomBytes);
+uint8_t at_random[RandomBytes];
+srand(time(nullptr));
+generate(begin(at_random), end(at_random), ::rand);
+initVirtMem.writeBlob(memState->getStackMin(), at_random, RandomBytes);
// Copy argv to stack
vector argPointers;
--
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Increase maximum stack size
Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/6661 )
Change subject: arch-riscv: Increase maximum stack size
..
arch-riscv: Increase maximum stack size
This patch increases the maximum stack size of RISC-V, which should help
to reduce problems with programs that allocate large amounts of data on
the stack or do many small allocations.
Change-Id: I1d760050229b12f01a4a8f24c047b587299fef6d
Reviewed-on: https://gem5-review.googlesource.com/6661
Reviewed-by: Jason Lowe-Power
Maintainer: Alec Roelke
---
M src/arch/riscv/process.cc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Alec Roelke: Looks good to me, approved
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 54afc85..371a8e4 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -61,7 +61,7 @@
ObjectFile *objFile) : Process(params, objFile)
{
const Addr stack_base = 0x7FFFL;
-const Addr max_stack_size = PageBytes * 64;
+const Addr max_stack_size = 8 * 1024 * 1024;
const Addr next_thread_stack_base = stack_base - max_stack_size;
const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
PageBytes);
--
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Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I1d760050229b12f01a4a8f24c047b587299fef6d
Gerrit-Change-Number: 6661
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Increase maximum stack size
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6661
Change subject: arch-riscv: Increase maximum stack size
..
arch-riscv: Increase maximum stack size
This patch increases the maximum stack size of RISC-V, which should help
to reduce problems with programs that allocate large amounts of data on
the stack or do many small allocations.
Change-Id: I1d760050229b12f01a4a8f24c047b587299fef6d
---
M src/arch/riscv/process.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 54afc85..371a8e4 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -61,7 +61,7 @@
ObjectFile *objFile) : Process(params, objFile)
{
const Addr stack_base = 0x7FFFL;
-const Addr max_stack_size = PageBytes * 64;
+const Addr max_stack_size = 8 * 1024 * 1024;
const Addr next_thread_stack_base = stack_base - max_stack_size;
const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
PageBytes);
--
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Gerrit-Change-Id: I1d760050229b12f01a4a8f24c047b587299fef6d
Gerrit-Change-Number: 6661
Gerrit-PatchSet: 1
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Fix floating-poing op classes
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6521
Change subject: arch-riscv: Fix floating-poing op classes
..
arch-riscv: Fix floating-poing op classes
This patch applies correct miscellaneous or multiply-accumulate op
classes to floating point instructions which had previously been
incorrectly classed as add or multiply instructions.
Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index baae581..ecee161 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -366,10 +366,10 @@
format Load {
0x2: flw({{
Fd_bits = (uint64_t)Mem_uw;
-}});
+}}, inst_flags=FloatMemReadOp);
0x3: fld({{
Fd_bits = Mem;
-}});
+}}, inst_flags=FloatMemReadOp);
}
}
@@ -460,10 +460,10 @@
format Store {
0x2: fsw({{
Mem_uw = (uint32_t)Fs2_bits;
-}});
+}}, inst_flags=FloatMemWriteOp);
0x3: fsd({{
Mem_ud = Fs2_bits;
-}});
+}}, inst_flags=FloatMemWriteOp);
}
}
@@ -806,7 +806,7 @@
fd = fs1*fs2 + fs3;
}
Fd_bits = (uint64_t)reinterpret_cast(fd);
-}}, FloatMultOp);
+}}, FloatMultAccOp);
0x1: fmadd_d({{
if (std::isnan(Fs1) || std::isnan(Fs2) ||
std::isnan(Fs3)) {
@@ -829,7 +829,7 @@
} else {
Fd = Fs1*Fs2 + Fs3;
}
-}}, FloatMultOp);
+}}, FloatMultAccOp);
}
0x11: decode FUNCT2 {
0x0: fmsub_s({{
@@ -861,7 +861,7 @@
fd = fs1*fs2 - fs3;
}
Fd_bits = (uint64_t)reinterpret_cast(fd);
-}}, FloatMultOp);
+}}, FloatMultAccOp);
0x1: fmsub_d({{
if (std::isnan(Fs1) || std::isnan(Fs2) ||
std::isnan(Fs3)) {
@@ -884,7 +884,7 @@
} else {
Fd = Fs1*Fs2 - Fs3;
}
-}}, FloatMultOp);
+}}, FloatMultAccOp);
}
0x12: decode FUNCT2 {
0x0: fnmsub_s({{
@@ -916,7 +916,7 @@
fd = -(fs1*fs2 - fs3);
}
Fd_bits = (uint64_t)reinterpret_cast(fd);
-}}, FloatMultOp);
+}}, FloatMultAccOp);
0x1: fnmsub_d({{
if (std::isnan(Fs1) || std::isnan(Fs2) ||
std::isnan(Fs3)) {
@@ -939,7 +939,7 @@
} else {
Fd = -(Fs1*Fs2 - Fs3);
}
-}}, FloatMultOp);
+}}, FloatMultAccOp);
}
0x13: decode FUNCT2 {
0x0: fnmadd_s({{
@@ -971,7 +971,7 @@
fd = -(fs1*fs2 + fs3);
}
Fd_bits = (uint64_t)reinterpret_cast(fd);
-}}, FloatMultOp);
+}}, FloatMultAccOp);
0x1: fnmadd_d({{
if (std::isnan(Fs1) || std::isnan(Fs2) ||
std::isnan(Fs3)) {
@@ -994,7 +994,7 @@
} else {
Fd = -(Fs1*Fs2 + Fs3);
}
-}}, FloatMultOp);
+}}, FloatMultAccOp);
}
0x14: decode FUNCT7 {
0x0: fadd_s({{
@@ -1115,7 +1115,7 @@
fd = copysign(fs1, fs2);
}
Fd_bits =
(uint64_t)reinterpret_cast(fd);
-}});
+}}, FloatMiscOp);
0x1: fsgnjn_s({{
uint32_t temp;
float fs1 = reinterpret_cast(temp =
Fs1_bits);
@@ -1129,7 +1129,7 @@
fd = copysign(fs1, -fs2);
}
Fd_bits =
(uint64_t)reinterpret_cast(fd);
-}});
+}}, FloatMiscOp);
0x2: fsgnjx_s({{
uint32_t temp;
float fs1 = reinterpret_cast(temp =
Fs1_bits);
@@ -1143,7 +1143,7 @@
fd = fs1*(signbit(fs2) ? -1.0 : 1.0);
}
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move compressed ops out of ISA
S OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#ifndef __ARCH_RISCV_INSTS_COMPRESSED_HH__
+#define __ARCH_RISCV_INSTS_COMPRESSED_HH__
+
+#include
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Base class for compressed operations that work only on registers
+ */
+class CompRegOp : public RiscvStaticInst
+{
+ protected:
+using RiscvStaticInst::RiscvStaticInst;
+
+std::string generateDisassembly(
+Addr pc, const SymbolTable *symtab) const override;
+};
+
+}
+
+#endif // __ARCH_RISCV_INSTS_COMPRESSED_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/compressed.isa
b/src/arch/riscv/isa/formats/compressed.isa
index 683795d..3c47a90 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -28,35 +28,6 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Alec Roelke
-
-output header {{
-/**
- * Base class for compressed operations that work only on registers
- */
-class CompRegOp : public RiscvStaticInst
-{
- protected:
-/// Constructor
-CompRegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
-: RiscvStaticInst(mnem, _machInst, __opClass)
-{}
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-}};
-
-output decoder {{
-std::string
-CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab)
const
-{
-std::stringstream ss;
-ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-registerName(_srcRegIdx[0]);
-return ss.str();
-}
-}};
-
def format CROp(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index f4662da..9f3d99f 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -43,6 +43,7 @@
#include
#include "arch/riscv/insts/amo.hh"
+#include "arch/riscv/insts/compressed.hh"
#include "arch/riscv/insts/mem.hh"
#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
Gerrit-Change-Number: 6026
Gerrit-PatchSet: 7
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Make use of ImmOp's polymorphism
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6401
Change subject: arch-riscv: Make use of ImmOp's polymorphism
..
arch-riscv: Make use of ImmOp's polymorphism
This patch makes use of ImmOp's polymorphism to remove unnecessary
casting from the implementations of arithmetic instructions with
immediate operands and to remove the CUIOp format by combining it with
the CIOp format (compressed arithmetic instructions with immediate
operands). Interestingly, RISC-V specifies that instructions with
unsigned immediate operands still need to sign-extend the immediates
from 12 (or 20) bits to 64 bits, so that is left alone.
Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/formats/standard.isa
M tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest
M tests/test-progs/insttest/src/riscv/rv64i.cpp
5 files changed, 25 insertions(+), 35 deletions(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 2761fac..435266c 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -36,7 +36,7 @@
decode QUADRANT default Unknown::unknown() {
0x0: decode COPCODE {
-0x0: CUIOp::c_addi4spn({{
+0x0: CIOp::c_addi4spn({{
imm = CIMM8<1:1> << 2 |
CIMM8<0:0> << 3 |
CIMM8<7:6> << 4 |
@@ -45,7 +45,7 @@
if (machInst == 0)
fault = make_shared("zero instruction");
Rp2 = sp + imm;
-}});
+}}, uint64_t);
format CompressedLoad {
0x1: c_fld({{
offset = CIMM3 << 3 | CIMM2 << 6;
@@ -152,26 +152,26 @@
}
}
0x4: decode CFUNCT2HIGH {
-format CUIOp {
+format CIOp {
0x0: c_srli({{
imm = CIMM5 | (CIMM1 << 5);
assert(imm != 0);
}}, {{
Rp1 = Rp1 >> imm;
-}});
+}}, uint64_t);
0x1: c_srai({{
imm = CIMM5 | (CIMM1 << 5);
assert(imm != 0);
}}, {{
Rp1_sd = Rp1_sd >> imm;
-}});
+}}, uint64_t);
0x2: c_andi({{
imm = CIMM5;
if (CIMM1 > 0)
imm |= ~((uint64_t)0x1F);
}}, {{
Rp1 = Rp1 & imm;
-}});
+}}, uint64_t);
}
format ROp {
0x3: decode CFUNCT1 {
@@ -242,13 +242,13 @@
}
}
0x2: decode COPCODE {
-0x0: CUIOp::c_slli({{
+0x0: CIOp::c_slli({{
imm = CIMM5 | (CIMM1 << 5);
assert(imm != 0);
}}, {{
assert(RC1 != 0);
Rc1 = Rc1 << imm;
-}});
+}}, uint64_t);
format CompressedLoad {
0x1: c_fldsp({{
offset = CIMM5<4:3> << 3 |
@@ -376,9 +376,9 @@
0x03: decode FUNCT3 {
format IOp {
0x0: fence({{
-}}, IsNonSpeculative, IsMemBarrier, No_OpClass);
+}}, uint64_t, IsNonSpeculative, IsMemBarrier, No_OpClass);
0x1: fence_i({{
-}}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
+}}, uint64_t, IsNonSpeculative, IsSerializeAfter,
No_OpClass);
}
}
@@ -394,11 +394,11 @@
Rd = (Rs1_sd < imm) ? 1 : 0;
}});
0x3: sltiu({{
-Rd = (Rs1 < (uint64_t)imm) ? 1 : 0;
-}});
+Rd = (Rs1 < imm) ? 1 : 0;
+}}, uint64_t);
0x4: xori({{
-Rd = Rs1 ^ (uint64_t)imm;
-}});
+Rd = Rs1 ^ imm;
+}}, uint64_t);
0x5: decode SRTYPE {
0x0: srli({{
Rd = Rs1 >> SHAMT6;
@@ -408,11 +408,11 @@
}});
}
0x6: ori({{
-Rd = Rs1 | (uint64_t)imm;
-}});
+Rd = Rs1 | imm;
+}}, uint64_t);
0x7: andi({{
-Rd = Rs1 & (uint64_t)imm;
-}});
+Rd = Rs1 & imm;
+}}, uint64_t);
}
}
@@ -423,8 +423,8 @@
0x06: decode FUNCT3 {
format IOp {
0x0: addiw({{
-Rd_sd = (int32_t)Rs1 + (int32_t)imm;
-}});
+Rd_sd = Rs1_sw + imm;
+}}, int32_t);
0x1: slliw({{
Rd_sd = Rs1_sw << SHA
[gem5-dev] Change in public/gem5[master]: arch-riscv: Fix floating-point conversion bugs
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6402
Change subject: arch-riscv: Fix floating-point conversion bugs
..
arch-riscv: Fix floating-point conversion bugs
Using the fetestexcept function to check for specific types of floating
point exceptions is unreliable for some kinds of
floating-point-to-integer conversion operations. RISC-V code used to
make use of them to check for some exceptional cases like overflow and
underflow, which caused incorrect output when compiler optimization is
turned on. This patch changes the use of fetestexcept to explicit checks
for those exceptional cases.
Change-Id: Id983906ea0664dc246e115a9e470d9ab7733bde1
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 63 insertions(+), 53 deletions(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 435266c..baae581 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1338,31 +1338,31 @@
if (std::isnan(fs1)) {
Rd_sd = numeric_limits::max();
FFLAGS |= FloatInvalid;
+} else if (fs1 >= numeric_limits::max()) {
+Rd_sd = numeric_limits::max();
+FFLAGS |= FloatInvalid;
+} else if (fs1 <= numeric_limits::min()) {
+Rd_sd = numeric_limits::min();
+FFLAGS |= FloatInvalid;
} else {
Rd_sd = (int32_t)fs1;
-if (fetestexcept(FE_INVALID)) {
-if (signbit(fs1)) {
-Rd_sd = numeric_limits::min();
-} else {
-Rd_sd = numeric_limits::max();
-}
-feclearexcept(FE_INEXACT);
-}
}
}}, FloatCvtOp);
0x1: fcvt_wu_s({{
uint32_t temp;
float fs1 = reinterpret_cast(temp =
Fs1_bits);
-if (fs1 < 0.0) {
+if (std::isnan(fs1)) {
+Rd = numeric_limits::max();
+FFLAGS |= FloatInvalid;
+} else if (fs1 < 0.0) {
Rd = 0;
FFLAGS |= FloatInvalid;
+} else if (fs1 > numeric_limits::max()) {
+Rd = numeric_limits::max();
+FFLAGS |= FloatInvalid;
} else {
Rd = (uint32_t)fs1;
-if (fetestexcept(FE_INVALID)) {
-Rd = numeric_limits::max();
-feclearexcept(FE_INEXACT);
-}
}
}}, FloatCvtOp);
0x2: fcvt_l_s({{
@@ -1372,79 +1372,89 @@
if (std::isnan(fs1)) {
Rd_sd = numeric_limits::max();
FFLAGS |= FloatInvalid;
+} else if (fs1 > numeric_limits::max()) {
+Rd_sd = numeric_limits::max();
+FFLAGS |= FloatInvalid;
+} else if (fs1 < numeric_limits::min()) {
+Rd_sd = numeric_limits::min();
+FFLAGS |= FloatInvalid;
} else {
Rd_sd = (int64_t)fs1;
-if (fetestexcept(FE_INVALID)) {
-if (signbit(fs1)) {
-Rd_sd = numeric_limits::min();
-} else {
-Rd_sd = numeric_limits::max();
-}
-feclearexcept(FE_INEXACT);
-}
}
}}, FloatCvtOp);
0x3: fcvt_lu_s({{
uint32_t temp;
float fs1 = reinterpret_cast(temp =
Fs1_bits);
-if (fs1 < 0.0) {
+if (std::isnan(fs1)) {
+Rd = numeric_limits::max();
+FFLAGS |= FloatInvalid;
+} else if (fs1 < 0.0) {
Rd = 0;
FFLAGS |= FloatInvalid;
+} else if (fs1 > numeric_limits::max()) {
+Rd = numeric_limits::max();
+FFLAGS |= Floa
[gem5-dev] Change in public/gem5[master]: arch-riscv: use sext rather than manual masks
);',
'regs': ','.join(regs)}, opt_flags)
header_output = JumpDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
@@ -261,10 +259,9 @@
}};
def format UOp(code, *opt_flags) {{
-imm_code = 'imm = (int32_t)(IMM20 << 12);'
regs = ['_destRegIdx[0]']
iop = InstObjParams(name, Name, 'ImmOp',
-{'code': code, 'imm_code': imm_code,
+{'code': code, 'imm_code': 'imm = sext<20>(IMM20) << 12;',
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
@@ -274,11 +271,11 @@
def format JOp(code, *opt_flags) {{
imm_code = """
-imm |= UJIMMBITS19TO12 << 12;
-imm |= UJIMMBIT11 << 11;
-imm |= UJIMMBITS10TO1 << 1;
-if (IMMSIGN > 0)
-imm |= ~((uint64_t)0xF);
+ imm = UJIMMBITS10TO1 << 1 |
+ UJIMMBIT11 << 11 |
+ UJIMMBITS19TO12 << 12 |
+ IMMSIGN << 20;
+imm = sext<21>(imm);
"""
pc = 'pc.set(pc.pc() + imm);'
regs = ['_destRegIdx[0]']
--
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Gerrit-Change-Id: Ief2df91a25500c64f5bcae0dcd437c1e3bb95e6c
Gerrit-Change-Number: 6182
Gerrit-PatchSet: 3
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Gabe Black
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[gem5-dev] Change in public/gem5[master]: arch-riscv: use sext rather than manual masks
Hello Gabe Black, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6182 to look at the new patch set (#2). Change subject: arch-riscv: use sext rather than manual masks .. arch-riscv: use sext rather than manual masks Replace manual creation of masks for sign extension of immediates with the sext function. Change-Id: Ief2df91a25500c64f5bcae0dcd437c1e3bb95e6c --- M src/arch/riscv/isa/bitfields.isa M src/arch/riscv/isa/formats/mem.isa M src/arch/riscv/isa/formats/standard.isa 3 files changed, 21 insertions(+), 32 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6182 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ief2df91a25500c64f5bcae0dcd437c1e3bb95e6c Gerrit-Change-Number: 6182 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Remove spaces around ea_code
Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/6181 )
Change subject: arch-riscv: Remove spaces around ea_code
..
arch-riscv: Remove spaces around ea_code
This patch makes mem.isa conform to style guidelines better by removing
spaces around the "ea_code" argument default value assignment of the
Load format.
Change-Id: I1c62b99de3617a3734b128b00fb421773e021317
Reviewed-on: https://gem5-review.googlesource.com/6181
Reviewed-by: Gabe Black
Maintainer: Alec Roelke
---
M src/arch/riscv/isa/formats/mem.isa
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Gabe Black: Looks good to me, approved
Alec Roelke: Looks good to me, approved
diff --git a/src/arch/riscv/isa/formats/mem.isa
b/src/arch/riscv/isa/formats/mem.isa
index ef5f952..2cb2f18 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -254,7 +254,7 @@
}
}};
-def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}},
mem_flags=[],
+def format Load(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[],
inst_flags=[]) {{
offset_code = """
offset = IMM12;
--
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Gerrit-Change-Number: 6181
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Gerrit-Reviewer: Gabe Black
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Add missing license paragraphs
@@ -1,34 +1,34 @@
-// -*- mode:c++ -*-
-
-// Copyright (c) 2015 RISC-V Foundation
-// Copyright (c) 2016 The University of Virginia
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Maxwell Walter
-// Alec Roelke
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Maxwell Walter
+ * Alec Roelke
+ */
#ifndef __ARCH_RISCV_STATIC_INST_HH__
#define __ARCH_RISCV_STATIC_INST_HH__
@@ -66,7 +66,6 @@
protected:
std::vector microops;
-// Constructor
RiscvMacroInst(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
RiscvStaticInst(mnem, _machInst, __opClass)
@@ -104,7 +103,6 @@
class RiscvMicroInst : public RiscvStaticInst
{
protected:
-// Constructor
RiscvMicroInst(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
RiscvStaticInst(mnem, _machInst, __opClass)
--
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Gerrit-Change-Id: I2ac4910a415de6032fc0b7d4422904c682e0ad87
Gerrit-Change-Number: 6183
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Add missing license paragraphs
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6183
Change subject: arch-riscv: Add missing license paragraphs
..
arch-riscv: Add missing license paragraphs
Some of the files in earlier patches rearranging instruction definitions
were missing copyright and license information. This patch adds them.
Change-Id: I2ac4910a415de6032fc0b7d4422904c682e0ad87
---
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/static_inst.cc
M src/arch/riscv/insts/static_inst.hh
3 files changed, 92 insertions(+), 33 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index ad504e2..439219c 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,3 +1,32 @@
+# Copyright (c) 2015 RISC-V Foundation
+# Copyright (c) 2017 The University of Virginia
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Alec Roelke
+
Import('*')
if env['TARGET_ISA'] == 'riscv':
diff --git a/src/arch/riscv/insts/static_inst.cc
b/src/arch/riscv/insts/static_inst.cc
index 8fc396d..665fab8 100644
--- a/src/arch/riscv/insts/static_inst.cc
+++ b/src/arch/riscv/insts/static_inst.cc
@@ -1,3 +1,35 @@
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Maxwell Walter
+ * Alec Roelke
+ */
+
#include "arch/riscv/insts/static_inst.hh"
#include "arch/riscv/types.hh"
diff --git a/src/arch/riscv/insts/static_inst.hh
b/src/arch/riscv/insts/static_inst.hh
index d360d44..bf34c9b 100644
--- a/src/arch/riscv/insts/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -1,34 +1,34 @@
-// -*- mode:c++ -*-
-
-// Copyright (c) 2015 RISC-V Foundation
-// Copyright (c) 2016 The University of Virginia
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the follow
[gem5-dev] Change in public/gem5[master]: arch-riscv: use sext rather than manual masks
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6182
Change subject: arch-riscv: use sext rather than manual masks
..
arch-riscv: use sext rather than manual masks
Replace manual creation of masks for sign extension of immediates with
the sext function.
Change-Id: Ief2df91a25500c64f5bcae0dcd437c1e3bb95e6c
---
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/formats/standard.isa
3 files changed, 21 insertions(+), 32 deletions(-)
diff --git a/src/arch/riscv/isa/bitfields.isa
b/src/arch/riscv/isa/bitfields.isa
index 8372ed9..903fce3 100644
--- a/src/arch/riscv/isa/bitfields.isa
+++ b/src/arch/riscv/isa/bitfields.isa
@@ -64,8 +64,8 @@
// SB-Type
def bitfield BIMM12BIT11 <7>;
def bitfield BIMM12BITS4TO1<11:8>;
-def bitfield IMMSIGN <31>;
def bitfield BIMM12BITS10TO5 <30:25>;
+def bitfield IMMSIGN <31>;
// UJ-Type
def bitfield UJIMMBITS10TO1 <30:21>;
diff --git a/src/arch/riscv/isa/formats/mem.isa
b/src/arch/riscv/isa/formats/mem.isa
index ef5f952..11b6c42 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -254,25 +254,17 @@
}
}};
-def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}},
mem_flags=[],
-inst_flags=[]) {{
-offset_code = """
-offset = IMM12;
-if (IMMSIGN > 0)
-offset |= ~((uint64_t)0xFFF);
- """
+def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}},
+offset_code={{offset = sext<12>(IMM12);}},
+mem_flags=[], inst_flags=[]) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, offset_code, ea_code, memacc_code,
mem_flags,
inst_flags, 'Load', exec_template_base='Load')
}};
-def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[],
-inst_flags=[]) {{
-offset_code = """
-offset = IMM5 | (IMM7 << 5);
-if (IMMSIGN > 0)
-offset |= ~((uint64_t)0xFFF);
- """
+def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}},
+offset_code={{offset = sext<12>(IMM5 | (IMM7 << 5));}},
+mem_flags=[], inst_flags=[]) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, offset_code, ea_code, memacc_code,
mem_flags,
inst_flags, 'Store', exec_template_base='Store')
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index e68cedf..517313d 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -219,10 +219,9 @@
}};
def format IOp(code, *opt_flags) {{
-imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
regs = ['_destRegIdx[0]','_srcRegIdx[0]']
iop = InstObjParams(name, Name, 'ImmOp',
-{'code': code, 'imm_code': imm_code,
+{'code': code, 'imm_code': 'imm = sext<12>(IMM12);',
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
@@ -232,11 +231,11 @@
def format BOp(code, *opt_flags) {{
imm_code = """
-imm |= BIMM12BIT11 << 11;
-imm |= BIMM12BITS4TO1 << 1;
-imm |= BIMM12BITS10TO5 << 5;
-if (IMMSIGN > 0)
-imm |= ~((uint64_t)0xFFF);
+imm = BIMM12BITS4TO1 << 1 |
+ BIMM12BITS10TO5 << 5 |
+ BIMM12BIT11 << 11|
+ IMMSIGN << 12;
+imm = sext<13>(imm);
"""
regs = ['_srcRegIdx[0]','_srcRegIdx[1]']
iop = InstObjParams(name, Name, 'ImmOp',
@@ -249,10 +248,9 @@
}};
def format Jump(code, *opt_flags) {{
-imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
-regs = ['_destRegIdx[0]','_srcRegIdx[0]']
+regs = ['_destRegIdx[0]', '_srcRegIdx[0]']
iop = InstObjParams(name, Name, 'ImmOp',
-{'code': code, 'imm_code': imm_code,
+{'code': code, 'imm_code': 'imm = sext<12>(IMM12);',
'regs': ','.join(regs)}, opt_flags)
header_output = JumpDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
@@ -261,10 +259,9 @@
}};
def format UOp(code, *opt_flags) {{
-imm_code = 'imm = (int32_t)(IMM20 << 12);'
regs = ['_destRegIdx[0]']
iop = InstObjParams(name, Name, 'ImmOp',
-{'code': code, 'imm_code': imm_code,
+{'code': code, 'imm_code': 'imm = sext<20>(IMM20) << 12;',
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
@@ -274,11 +271,11 @@
def format JOp(code, *opt_flags) {{
imm_code = """
-imm |= UJIMMBITS19TO12 <
[gem5-dev] Change in public/gem5[master]: arch-riscv: Remove spaces around ea_code
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6181
Change subject: arch-riscv: Remove spaces around ea_code
..
arch-riscv: Remove spaces around ea_code
This patch makes mem.isa conform to style guidelines better by removing
spaces around the "ea_code" argument default value assignment of the
Load format.
Change-Id: I1c62b99de3617a3734b128b00fb421773e021317
---
M src/arch/riscv/isa/formats/mem.isa
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa/formats/mem.isa
b/src/arch/riscv/isa/formats/mem.isa
index ef5f952..2cb2f18 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -254,7 +254,7 @@
}
}};
-def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}},
mem_flags=[],
+def format Load(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[],
inst_flags=[]) {{
offset_code = """
offset = IMM12;
--
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Remove static parts of AMOs out of ISA
served::generateDisassembly(Addr pc,
-const SymbolTable *symtab) const
-{
-std::stringstream ss;
-ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
-<< registerName(_srcRegIdx[0]) << ')';
-return ss.str();
-}
-
-std::string StoreCond::generateDisassembly(Addr pc,
-const SymbolTable *symtab) const
-{
-std::stringstream ss;
-ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
-<< registerName(_srcRegIdx[1]) << ", ("
-<< registerName(_srcRegIdx[0]) << ')';
-return ss.str();
-}
-
-std::string AtomicMemOp::generateDisassembly(Addr pc,
-const SymbolTable *symtab) const
-{
-std::stringstream ss;
-ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
-<< registerName(_srcRegIdx[1]) << ", ("
-<< registerName(_srcRegIdx[0]) << ')';
-return ss.str();
-}
-
-std::string AtomicMemOpMicro::generateDisassembly(Addr pc,
-const SymbolTable *symtab) const
-{
-std::stringstream ss;
-ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
-return ss.str();
-}
-}};
-
def template AtomicMemOpDeclare {{
/**
* Static instruction class for an AtomicMemOp operation
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index 0723620..f4662da 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -42,6 +42,7 @@
#include
#include
+#include "arch/riscv/insts/amo.hh"
#include "arch/riscv/insts/mem.hh"
#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
--
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Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
Gerrit-Change-Number: 6025
Gerrit-PatchSet: 6
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move parts of mem insts out of ISA
e *symtab) const;
-};
-
-class Store : public RiscvStaticInst
-{
- public:
-/// Displacement for EA calculation (signed).
-int64_t sdisp;
-
- protected:
-/// Memory request flags. See mem_req_base.hh.
-Request::Flags memAccessFlags;
-
-/// Constructor
-Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
-: RiscvStaticInst(mnem, _machInst, __opClass), sdisp(0)
-{
-sdisp = IMM5 | (IMM7 << 5);
-if (IMMSIGN > 0)
-sdisp |= ~((uint64_t)0xFFF);
-}
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-
-}};
-
-
-output decoder {{
-std::string
-Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
-std::stringstream ss;
-ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-ldisp << '(' << registerName(_srcRegIdx[0]) << ')';
-return ss.str();
-}
-
-std::string
-Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
-std::stringstream ss;
-ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " <<
-sdisp << '(' << registerName(_srcRegIdx[0]) << ')';
-return ss.str();
-}
-}};
-
def template LoadStoreDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
@@ -320,24 +254,24 @@
}
}};
-def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
+def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}},
mem_flags=[],
inst_flags=[]) {{
offset_code = """
-ldisp = IMM12;
+offset = IMM12;
if (IMMSIGN > 0)
-ldisp |= ~((uint64_t)0xFFF);
+offset |= ~((uint64_t)0xFFF);
"""
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, offset_code, ea_code, memacc_code,
mem_flags,
inst_flags, 'Load', exec_template_base='Load')
}};
-def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
+def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[],
inst_flags=[]) {{
offset_code = """
-sdisp = IMM5 | (IMM7 << 5);
+offset = IMM5 | (IMM7 << 5);
if (IMMSIGN > 0)
-sdisp |= ~((uint64_t)0xFFF);
+offset |= ~((uint64_t)0xFFF);
"""
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, offset_code, ea_code, memacc_code,
mem_flags,
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index cd43996..0723620 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -42,6 +42,7 @@
#include
#include
+#include "arch/riscv/insts/mem.hh"
#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
#include "arch/riscv/insts/unknown.hh"
--
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Gerrit-Change-Number: 6024
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Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move unknown out of ISA description
: RiscvStaticInst("unknown", _machInst, No_OpClass)
-{
-flags[IsNonSpeculative] = true;
-}
-
-Fault execute(ExecContext *, Trace::InstRecord *) const;
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-}};
-
-output decoder {{
-std::string
-Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
-return csprintf("unknown opcode 0x%02x", OPCODE);
-}
-}};
-
-output exec {{
-Fault
-Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
-{
-Fault fault = std::make_shared();
-return fault;
-}
-}};
-
def format Unknown() {{
decode_block = 'return new Unknown(machInst);\n'
}};
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index dfd0f37..cd43996 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -44,6 +44,7 @@
#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/insts/unknown.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
Gerrit-Change-Number: 6023
Gerrit-PatchSet: 6
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move standard ops out of ISA
27;imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
regs = ['_destRegIdx[0]','_srcRegIdx[0]']
-iop = InstObjParams(name, Name, 'BranchOp',
+iop = InstObjParams(name, Name, 'ImmOp',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = JumpDeclare.subst(iop)
@@ -404,7 +263,7 @@
def format UOp(code, *opt_flags) {{
imm_code = 'imm = (int32_t)(IMM20 << 12);'
regs = ['_destRegIdx[0]']
-iop = InstObjParams(name, Name, 'ImmOp',
+iop = InstObjParams(name, Name, 'ImmOp',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
@@ -423,7 +282,7 @@
"""
pc = 'pc.set(pc.pc() + imm);'
regs = ['_destRegIdx[0]']
-iop = InstObjParams(name, Name, 'BranchOp',
+iop = InstObjParams(name, Name, 'ImmOp',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = BranchDeclare.subst(iop)
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index 48f2b19..dfd0f37 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -42,6 +42,7 @@
#include
#include
+#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
Gerrit-Change-Number: 6022
Gerrit-PatchSet: 5
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move parts of mem insts out of ISA
Hello Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6024 to look at the new patch set (#5). Change subject: arch-riscv: Move parts of mem insts out of ISA .. arch-riscv: Move parts of mem insts out of ISA This patch moves static portions of the memory instructions out of the ISA generated code and puts them into arch/riscv/insts. It also simplifies the definitions of load and store instructions by giving them a common base class. Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 --- M src/arch/riscv/insts/SConscript M src/arch/riscv/insts/bitfields.hh A src/arch/riscv/insts/mem.cc A src/arch/riscv/insts/mem.hh M src/arch/riscv/isa/decoder.isa M src/arch/riscv/isa/formats/mem.isa M src/arch/riscv/isa/includes.isa 7 files changed, 194 insertions(+), 115 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6024 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 Gerrit-Change-Number: 6024 Gerrit-PatchSet: 5 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power Gerrit-CC: Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move parts of mem insts out of ISA
Hello Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6024 to look at the new patch set (#4). Change subject: arch-riscv: Move parts of mem insts out of ISA .. arch-riscv: Move parts of mem insts out of ISA This patch moves static portions of the memory instructions out of the ISA generated code and puts them into arch/riscv/insts. It also simplifies the definitions of load and store instructions by giving them a common base class. Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 --- M src/arch/riscv/insts/SConscript M src/arch/riscv/insts/bitfields.hh A src/arch/riscv/insts/mem.cc A src/arch/riscv/insts/mem.hh M src/arch/riscv/isa/decoder.isa M src/arch/riscv/isa/formats/mem.isa M src/arch/riscv/isa/includes.isa 7 files changed, 175 insertions(+), 96 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6024 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 Gerrit-Change-Number: 6024 Gerrit-PatchSet: 4 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move standard ops out of ISA
Hello Gabe Black, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6022 to look at the new patch set (#4). Change subject: arch-riscv: Move standard ops out of ISA .. arch-riscv: Move standard ops out of ISA This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a --- M src/arch/riscv/insts/SConscript A src/arch/riscv/insts/bitfields.hh A src/arch/riscv/insts/standard.cc A src/arch/riscv/insts/standard.hh M src/arch/riscv/isa/formats/compressed.isa M src/arch/riscv/isa/formats/standard.isa M src/arch/riscv/isa/includes.isa 7 files changed, 192 insertions(+), 148 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6022 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Gerrit-Change-Number: 6022 Gerrit-PatchSet: 4 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Remove static parts of AMOs out of ISA
Hello Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6025 to look at the new patch set (#4). Change subject: arch-riscv: Remove static parts of AMOs out of ISA .. arch-riscv: Remove static parts of AMOs out of ISA This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 --- M src/arch/riscv/insts/SConscript A src/arch/riscv/insts/amo.cc A src/arch/riscv/insts/amo.hh M src/arch/riscv/isa/formats/amo.isa M src/arch/riscv/isa/includes.isa 5 files changed, 168 insertions(+), 97 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6025 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Gerrit-Change-Number: 6025 Gerrit-PatchSet: 4 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move compressed ops out of ISA
Hello Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6026 to look at the new patch set (#4). Change subject: arch-riscv: Move compressed ops out of ISA .. arch-riscv: Move compressed ops out of ISA This patch moves static portions of the compressed instruction definitions out of the ISA generated code. Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296 --- M src/arch/riscv/insts/SConscript A src/arch/riscv/insts/compressed.cc A src/arch/riscv/insts/compressed.hh M src/arch/riscv/isa/formats/compressed.isa M src/arch/riscv/isa/includes.isa 5 files changed, 111 insertions(+), 29 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6026 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296 Gerrit-Change-Number: 6026 Gerrit-PatchSet: 4 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move unknown out of ISA description
Hello Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6023 to look at the new patch set (#4). Change subject: arch-riscv: Move unknown out of ISA description .. arch-riscv: Move unknown out of ISA description This patch removes the Unknown instruction type out of the ISA generated code and puts it into arch/riscv/insts. Since there isn't any dynamic behavior to it, all that's left behind is a template for creating a new Unknown instruction. Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db --- M src/arch/riscv/insts/bitfields.hh A src/arch/riscv/insts/unknown.hh M src/arch/riscv/isa/formats/unknown.isa M src/arch/riscv/isa/includes.isa 4 files changed, 76 insertions(+), 41 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6023 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db Gerrit-Change-Number: 6023 Gerrit-PatchSet: 4 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power Gerrit-CC: Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Remove static parts of AMOs out of ISA
Hello Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6025 to look at the new patch set (#3). Change subject: arch-riscv: Remove static parts of AMOs out of ISA .. arch-riscv: Remove static parts of AMOs out of ISA This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 --- M src/arch/riscv/insts/SConscript A src/arch/riscv/insts/amo.cc A src/arch/riscv/insts/amo.hh M src/arch/riscv/isa/formats/amo.isa M src/arch/riscv/isa/includes.isa 5 files changed, 172 insertions(+), 97 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6025 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Gerrit-Change-Number: 6025 Gerrit-PatchSet: 3 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move parts of mem insts out of ISA
Hello Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6024 to look at the new patch set (#3). Change subject: arch-riscv: Move parts of mem insts out of ISA .. arch-riscv: Move parts of mem insts out of ISA This patch moves static portions of the memory instructions out of the ISA generated code and puts them into arch/riscv/insts. It also simplifies the definitions of load and store instructions by giving them a common base class. Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 --- M src/arch/riscv/insts/SConscript M src/arch/riscv/insts/bitfields.hh A src/arch/riscv/insts/mem.cc A src/arch/riscv/insts/mem.hh M src/arch/riscv/isa/decoder.isa M src/arch/riscv/isa/formats/mem.isa M src/arch/riscv/isa/includes.isa 7 files changed, 179 insertions(+), 96 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6024 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 Gerrit-Change-Number: 6024 Gerrit-PatchSet: 3 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move standard ops out of ISA
Alec Roelke has uploaded a new patch set (#3). ( https://gem5-review.googlesource.com/6022 ) Change subject: arch-riscv: Move standard ops out of ISA .. arch-riscv: Move standard ops out of ISA This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a --- M src/arch/riscv/insts/SConscript A src/arch/riscv/insts/bitfields.hh A src/arch/riscv/insts/standard.cc A src/arch/riscv/insts/standard.hh M src/arch/riscv/isa/formats/compressed.isa M src/arch/riscv/isa/formats/standard.isa M src/arch/riscv/isa/includes.isa 7 files changed, 196 insertions(+), 148 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6022 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Gerrit-Change-Number: 6022 Gerrit-PatchSet: 3 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-CC: Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move compressed ops out of ISA
Hello Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6026 to look at the new patch set (#3). Change subject: arch-riscv: Move compressed ops out of ISA .. arch-riscv: Move compressed ops out of ISA This patch moves static portions of the compressed instruction definitions out of the ISA generated code. Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296 --- M src/arch/riscv/insts/SConscript A src/arch/riscv/insts/compressed.cc A src/arch/riscv/insts/compressed.hh M src/arch/riscv/isa/formats/compressed.isa M src/arch/riscv/isa/includes.isa 5 files changed, 115 insertions(+), 29 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6026 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296 Gerrit-Change-Number: 6026 Gerrit-PatchSet: 3 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move unknown out of ISA description
Hello Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/6023 to look at the new patch set (#3). Change subject: arch-riscv: Move unknown out of ISA description .. arch-riscv: Move unknown out of ISA description This patch removes the Unknown instruction type out of the ISA generated code and puts it into arch/riscv/insts. Since there isn't any dynamic behavior to it, all that's left behind is a template for creating a new Unknown instruction. Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db --- M src/arch/riscv/insts/bitfields.hh A src/arch/riscv/insts/unknown.hh M src/arch/riscv/isa/formats/unknown.isa M src/arch/riscv/isa/includes.isa 4 files changed, 80 insertions(+), 41 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6023 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db Gerrit-Change-Number: 6023 Gerrit-PatchSet: 3 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move compressed ops out of ISA
Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/6026 ) Change subject: arch-riscv: Move compressed ops out of ISA .. arch-riscv: Move compressed ops out of ISA This patch moves static portions of the compressed instruction definitions out of the ISA generated code. Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296 --- M src/arch/riscv/insts/SConscript A src/arch/riscv/insts/compressed.cc A src/arch/riscv/insts/compressed.hh M src/arch/riscv/isa/formats/compressed.isa M src/arch/riscv/isa/includes.isa 5 files changed, 49 insertions(+), 29 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6026 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296 Gerrit-Change-Number: 6026 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move parts of mem insts out of ISA
Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/6024 ) Change subject: arch-riscv: Move parts of mem insts out of ISA .. arch-riscv: Move parts of mem insts out of ISA This patch moves static portions of the memory instructions out of the ISA generated code and puts them into arch/riscv/insts. It also simplifies the definitions of load and store instructions by giving them a common base class. Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 --- M src/arch/riscv/insts/SConscript M src/arch/riscv/insts/bitfields.hh A src/arch/riscv/insts/mem.cc A src/arch/riscv/insts/mem.hh M src/arch/riscv/isa/decoder.isa M src/arch/riscv/isa/formats/mem.isa M src/arch/riscv/isa/includes.isa 7 files changed, 113 insertions(+), 96 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6024 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 Gerrit-Change-Number: 6024 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move standard ops out of ISA
Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/6022 ) Change subject: arch-riscv: Move standard ops out of ISA .. arch-riscv: Move standard ops out of ISA This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a --- M src/arch/riscv/insts/SConscript A src/arch/riscv/insts/bitfields.hh A src/arch/riscv/insts/standard.cc A src/arch/riscv/insts/standard.hh M src/arch/riscv/isa/formats/compressed.isa M src/arch/riscv/isa/formats/standard.isa M src/arch/riscv/isa/includes.isa 7 files changed, 134 insertions(+), 148 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6022 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Gerrit-Change-Number: 6022 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-CC: Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Remove static parts of AMOs out of ISA
Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/6025 ) Change subject: arch-riscv: Remove static parts of AMOs out of ISA .. arch-riscv: Remove static parts of AMOs out of ISA This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 --- M src/arch/riscv/insts/SConscript A src/arch/riscv/insts/amo.cc A src/arch/riscv/insts/amo.hh M src/arch/riscv/isa/formats/amo.isa M src/arch/riscv/isa/includes.isa 5 files changed, 106 insertions(+), 97 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6025 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Gerrit-Change-Number: 6025 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move unknown out of ISA description
Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/6023 ) Change subject: arch-riscv: Move unknown out of ISA description .. arch-riscv: Move unknown out of ISA description This patch removes the Unknown instruction type out of the ISA generated code and puts it into arch/riscv/insts. Since there isn't any dynamic behavior to it, all that's left behind is a template for creating a new Unknown instruction. Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db --- M src/arch/riscv/insts/SConscript M src/arch/riscv/insts/bitfields.hh A src/arch/riscv/insts/unknown.cc A src/arch/riscv/insts/unknown.hh M src/arch/riscv/isa/formats/unknown.isa M src/arch/riscv/isa/includes.isa 6 files changed, 62 insertions(+), 42 deletions(-) -- To view, visit https://gem5-review.googlesource.com/6023 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db Gerrit-Change-Number: 6023 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move static_inst into a directory
Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/6021 )
Change subject: arch-riscv: Move static_inst into a directory
..
arch-riscv: Move static_inst into a directory
This patch creates an "insts" directory in src/arch/riscv to store
static portions of instruction definitions that aren't part of the code
generated by the ISA description. It serves as a starting point for
future patches to simplify the ISA description.
Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa
Reviewed-on: https://gem5-review.googlesource.com/6021
Reviewed-by: Gabe Black
Maintainer: Alec Roelke
---
A src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/static_inst.cc
R src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/isa/includes.isa
4 files changed, 37 insertions(+), 33 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Alec Roelke: Looks good to me, approved
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
new file mode 100644
index 000..95e6afd
--- /dev/null
+++ b/src/arch/riscv/insts/SConscript
@@ -0,0 +1,4 @@
+Import('*')
+
+if env['TARGET_ISA'] == 'riscv':
+Source('static_inst.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/static_inst.cc
b/src/arch/riscv/insts/static_inst.cc
new file mode 100644
index 000..8fc396d
--- /dev/null
+++ b/src/arch/riscv/insts/static_inst.cc
@@ -0,0 +1,19 @@
+#include "arch/riscv/insts/static_inst.hh"
+
+#include "arch/riscv/types.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+void
+RiscvMicroInst::advancePC(PCState &pcState) const
+{
+if (flags[IsLastMicroop]) {
+pcState.uEnd();
+} else {
+pcState.uAdvance();
+}
+}
+
+} // namespace RiscvISA
\ No newline at end of file
diff --git a/src/arch/riscv/static_inst.hh
b/src/arch/riscv/insts/static_inst.hh
similarity index 80%
rename from src/arch/riscv/static_inst.hh
rename to src/arch/riscv/insts/static_inst.hh
index bdcdee7..d360d44 100644
--- a/src/arch/riscv/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -33,12 +33,15 @@
#ifndef __ARCH_RISCV_STATIC_INST_HH__
#define __ARCH_RISCV_STATIC_INST_HH__
-
-//
-// Base class for Riscv instructions, and some support functions
-//
+#include
-namespace RiscvISA {
+#include "arch/riscv/types.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+#include "mem/packet.hh"
+
+namespace RiscvISA
+{
/**
* Base class for all RISC-V static instructions.
@@ -46,20 +49,13 @@
class RiscvStaticInst : public StaticInst
{
protected:
-// Constructor
-RiscvStaticInst(const char *mnem, MachInst _machInst,
-OpClass __opClass) : StaticInst(mnem, _machInst, __opClass)
-{}
+using StaticInst::StaticInst;
virtual std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
public:
-void
-advancePC(RiscvISA::PCState &pc) const
-{
-pc.advance();
-}
+void advancePC(PCState &pc) const { pc.advance(); }
};
/**
@@ -78,16 +74,9 @@
flags[IsMacroop] = true;
}
-~RiscvMacroInst()
-{
-microops.clear();
-}
+~RiscvMacroInst() { microops.clear(); }
-StaticInstPtr
-fetchMicroop(MicroPC upc) const
-{
-return microops[upc];
-}
+StaticInstPtr fetchMicroop(MicroPC upc) const { return microops[upc]; }
Fault
initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
@@ -123,15 +112,7 @@
flags[IsMicroop] = true;
}
-void
-advancePC(RiscvISA::PCState &pcState) const
-{
-if (flags[IsLastMicroop]) {
-pcState.uEnd();
-} else {
-pcState.uAdvance();
-}
-}
+void advancePC(PCState &pcState) const;
};
}
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index c172d03..48f2b19 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -42,7 +42,7 @@
#include
#include
-#include "arch/riscv/static_inst.hh"
+#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa
Gerrit-Change-Number: 6021
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Gabe Black
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move compressed ops out of ISA
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6026
Change subject: arch-riscv: Move compressed ops out of ISA
..
arch-riscv: Move compressed ops out of ISA
This patch moves static portions of the compressed instruction
definitions out of the ISA generated code.
Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/compressed.cc
A src/arch/riscv/insts/compressed.hh
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/includes.isa
5 files changed, 47 insertions(+), 29 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index d058f85..39205a2 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -2,6 +2,7 @@
if env['TARGET_ISA'] == 'riscv':
Source('amo.cc')
+Source('compressed.cc')
Source('mem.cc')
Source('standard.cc')
Source('static_inst.cc')
diff --git a/src/arch/riscv/insts/compressed.cc
b/src/arch/riscv/insts/compressed.cc
new file mode 100644
index 000..8a8481e
--- /dev/null
+++ b/src/arch/riscv/insts/compressed.cc
@@ -0,0 +1,21 @@
+#include "arch/riscv/insts/compressed.hh"
+
+#include
+#include
+
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+std::string
+CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+registerName(_srcRegIdx[0]);
+return ss.str();
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/compressed.hh
b/src/arch/riscv/insts/compressed.hh
new file mode 100644
index 000..7d7e693
--- /dev/null
+++ b/src/arch/riscv/insts/compressed.hh
@@ -0,0 +1,24 @@
+#ifndef __ARCH_RISCV_INSTS_COMPRESSED_HH__
+#define __ARCH_RISCV_INSTS_COMPRESSED_HH__
+
+#include
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Base class for compressed operations that work only on registers
+ */
+class CompRegOp : public RiscvStaticInst
+{
+ protected:
+using RiscvStaticInst::RiscvStaticInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
+};
+
+}
+
+#endif // __ARCH_RISCV_INSTS_COMPRESSED_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/compressed.isa
b/src/arch/riscv/isa/formats/compressed.isa
index 1fd2319..91b6672 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -28,35 +28,6 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Alec Roelke
-
-output header {{
-/**
- * Base class for compressed operations that work only on registers
- */
-class CompRegOp : public RiscvStaticInst
-{
- protected:
-/// Constructor
-CompRegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
-: RiscvStaticInst(mnem, _machInst, __opClass)
-{}
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-}};
-
-output decoder {{
-std::string
-CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab)
const
-{
-std::stringstream ss;
-ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-registerName(_srcRegIdx[0]);
-return ss.str();
-}
-}};
-
def format CROp(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index f4662da..9f3d99f 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -43,6 +43,7 @@
#include
#include "arch/riscv/insts/amo.hh"
+#include "arch/riscv/insts/compressed.hh"
#include "arch/riscv/insts/mem.hh"
#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
Gerrit-Change-Number: 6026
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move static_inst into a directory
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6021
Change subject: arch-riscv: Move static_inst into a directory
..
arch-riscv: Move static_inst into a directory
This patch creates an "insts" directory in src/arch/riscv to store
static portions of instruction definitions that aren't part of the code
generated by the ISA description. It serves as a starting point for
future patches to simplify the ISA description.
Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa
---
A src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/static_inst.cc
R src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/isa/includes.isa
4 files changed, 37 insertions(+), 33 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
new file mode 100644
index 000..95e6afd
--- /dev/null
+++ b/src/arch/riscv/insts/SConscript
@@ -0,0 +1,4 @@
+Import('*')
+
+if env['TARGET_ISA'] == 'riscv':
+Source('static_inst.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/static_inst.cc
b/src/arch/riscv/insts/static_inst.cc
new file mode 100644
index 000..8fc396d
--- /dev/null
+++ b/src/arch/riscv/insts/static_inst.cc
@@ -0,0 +1,19 @@
+#include "arch/riscv/insts/static_inst.hh"
+
+#include "arch/riscv/types.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+void
+RiscvMicroInst::advancePC(PCState &pcState) const
+{
+if (flags[IsLastMicroop]) {
+pcState.uEnd();
+} else {
+pcState.uAdvance();
+}
+}
+
+} // namespace RiscvISA
\ No newline at end of file
diff --git a/src/arch/riscv/static_inst.hh
b/src/arch/riscv/insts/static_inst.hh
similarity index 80%
rename from src/arch/riscv/static_inst.hh
rename to src/arch/riscv/insts/static_inst.hh
index bdcdee7..d360d44 100644
--- a/src/arch/riscv/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -33,12 +33,15 @@
#ifndef __ARCH_RISCV_STATIC_INST_HH__
#define __ARCH_RISCV_STATIC_INST_HH__
-
-//
-// Base class for Riscv instructions, and some support functions
-//
+#include
-namespace RiscvISA {
+#include "arch/riscv/types.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+#include "mem/packet.hh"
+
+namespace RiscvISA
+{
/**
* Base class for all RISC-V static instructions.
@@ -46,20 +49,13 @@
class RiscvStaticInst : public StaticInst
{
protected:
-// Constructor
-RiscvStaticInst(const char *mnem, MachInst _machInst,
-OpClass __opClass) : StaticInst(mnem, _machInst, __opClass)
-{}
+using StaticInst::StaticInst;
virtual std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
public:
-void
-advancePC(RiscvISA::PCState &pc) const
-{
-pc.advance();
-}
+void advancePC(PCState &pc) const { pc.advance(); }
};
/**
@@ -78,16 +74,9 @@
flags[IsMacroop] = true;
}
-~RiscvMacroInst()
-{
-microops.clear();
-}
+~RiscvMacroInst() { microops.clear(); }
-StaticInstPtr
-fetchMicroop(MicroPC upc) const
-{
-return microops[upc];
-}
+StaticInstPtr fetchMicroop(MicroPC upc) const { return microops[upc]; }
Fault
initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
@@ -123,15 +112,7 @@
flags[IsMicroop] = true;
}
-void
-advancePC(RiscvISA::PCState &pcState) const
-{
-if (flags[IsLastMicroop]) {
-pcState.uEnd();
-} else {
-pcState.uAdvance();
-}
-}
+void advancePC(PCState &pcState) const;
};
}
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index c172d03..48f2b19 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -42,7 +42,7 @@
#include
#include
-#include "arch/riscv/static_inst.hh"
+#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa
Gerrit-Change-Number: 6021
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move unknown out of ISA description
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6023
Change subject: arch-riscv: Move unknown out of ISA description
..
arch-riscv: Move unknown out of ISA description
This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts. Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.
Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
---
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/unknown.cc
A src/arch/riscv/insts/unknown.hh
M src/arch/riscv/isa/formats/unknown.isa
M src/arch/riscv/isa/includes.isa
6 files changed, 61 insertions(+), 42 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index fe90280..3da7ba3 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -2,4 +2,5 @@
if env['TARGET_ISA'] == 'riscv':
Source('standard.cc')
-Source('static_inst.cc')
\ No newline at end of file
+Source('static_inst.cc')
+Source('unknown.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/bitfields.hh
b/src/arch/riscv/insts/bitfields.hh
index 45744e0..d664822 100644
--- a/src/arch/riscv/insts/bitfields.hh
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -5,5 +5,6 @@
#define CSRIMM bits(machInst, 19, 15)
#define FUNCT12 bits(machInst, 31, 20)
+#define OPCODE bits(machInst, 6, 0)
#endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/insts/unknown.cc
b/src/arch/riscv/insts/unknown.cc
new file mode 100644
index 000..aaec865
--- /dev/null
+++ b/src/arch/riscv/insts/unknown.cc
@@ -0,0 +1,17 @@
+#include "arch/riscv/insts/unknown.hh"
+
+#include
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+std::string
+Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+return csprintf("unknown opcode 0x%02x", OPCODE);
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/unknown.hh
b/src/arch/riscv/insts/unknown.hh
new file mode 100644
index 000..0540371
--- /dev/null
+++ b/src/arch/riscv/insts/unknown.hh
@@ -0,0 +1,40 @@
+#ifndef __ARCH_RISCV_UNKNOWN_INST_HH__
+#define __ARCH_RISCV_UNKNOWN_INST_HH__
+
+#include
+#include
+
+#include "arch/riscv/faults.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Static instruction class for unknown (illegal) instructions.
+ * These cause simulator termination if they are executed in a
+ * non-speculative mode. This is a leaf class.
+ */
+class Unknown : public RiscvStaticInst
+{
+ public:
+/// Constructor
+Unknown(MachInst _machInst)
+: RiscvStaticInst("unknown", _machInst, No_OpClass)
+{
+flags[IsNonSpeculative] = true;
+}
+
+Fault execute(ExecContext *, Trace::InstRecord *) const
+{
+return std::make_shared();
+}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
+};
+
+}
+
+#endif // __ARCH_RISCV_UNKNOWN_INST_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/unknown.isa
b/src/arch/riscv/isa/formats/unknown.isa
index b6d7649..7c2317f 100644
--- a/src/arch/riscv/isa/formats/unknown.isa
+++ b/src/arch/riscv/isa/formats/unknown.isa
@@ -34,47 +34,6 @@
//
// Unknown instructions
//
-
-output header {{
-/**
- * Static instruction class for unknown (illegal) instructions.
- * These cause simulator termination if they are executed in a
- * non-speculative mode. This is a leaf class.
- */
-class Unknown : public RiscvStaticInst
-{
- public:
-/// Constructor
-Unknown(MachInst _machInst)
-: RiscvStaticInst("unknown", _machInst, No_OpClass)
-{
-flags[IsNonSpeculative] = true;
-}
-
-Fault execute(ExecContext *, Trace::InstRecord *) const;
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-}};
-
-output decoder {{
-std::string
-Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
-return csprintf("unknown opcode 0x%02x", OPCODE);
-}
-}};
-
-output exec {{
-Fault
-Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
-{
-Fault fault = std::make_shared();
-return fault;
-}
-}};
-
def format Unknown() {{
decode_block = 'return new Unknown(machInst);\n'
}};
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index dfd0f37..cd43996 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -44,6 +44,7 @@
#include "arch/riscv/insts/standard.hh"
#include "a
[gem5-dev] Change in public/gem5[master]: arch-riscv: Remove static parts of AMOs out of ISA
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6025
Change subject: arch-riscv: Remove static parts of AMOs out of ISA
..
arch-riscv: Remove static parts of AMOs out of ISA
This patch removes the static parts of the RISC-V atomic memory
instructions out of the ISA generated code and into arch/riscv/insts. It
also makes the LR and SC instructions subclasses of MemInst from
arch/riscv/insts/mem.hh.
Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/amo.cc
A src/arch/riscv/insts/amo.hh
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/includes.isa
5 files changed, 98 insertions(+), 97 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index 49b31f0..d058f85 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,6 +1,7 @@
Import('*')
if env['TARGET_ISA'] == 'riscv':
+Source('amo.cc')
Source('mem.cc')
Source('standard.cc')
Source('static_inst.cc')
diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc
new file mode 100644
index 000..e492281
--- /dev/null
+++ b/src/arch/riscv/insts/amo.cc
@@ -0,0 +1,52 @@
+#include "arch/riscv/insts/amo.hh"
+
+#include
+#include
+
+#include "arch/riscv/utility.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+using namespace std;
+
+namespace RiscvISA
+{
+
+string LoadReserved::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
+<< registerName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
+string StoreCond::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
+<< registerName(_srcRegIdx[1]) << ", ("
+<< registerName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
+string AtomicMemOp::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
+<< registerName(_srcRegIdx[1]) << ", ("
+<< registerName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
+string AtomicMemOpMicro::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
+return ss.str();
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/amo.hh b/src/arch/riscv/insts/amo.hh
new file mode 100644
index 000..6e81722
--- /dev/null
+++ b/src/arch/riscv/insts/amo.hh
@@ -0,0 +1,44 @@
+#ifndef __ARCH_RISCV_INSTS_AMO_HH__
+#define __ARCH_RISCV_INSTS_AMO_HH__
+
+#include
+
+#include "arch/riscv/insts/mem.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+class LoadReserved : public MemInst
+{
+ protected:
+using MemInst::MemInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
+};
+
+class StoreCond : public MemInst
+{
+ protected:
+using MemInst::MemInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
+};
+
+class AtomicMemOp : public RiscvMacroInst
+{
+ protected:
+using RiscvMacroInst::RiscvMacroInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
+};
+
+class AtomicMemOpMicro : public RiscvMicroInst
+{
+ protected:
+Request::Flags memAccessFlags;
+using RiscvMicroInst::RiscvMicroInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
+};
+
+}
+
+#endif // __ARCH_RISCV_INSTS_AMO_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/amo.isa
b/src/arch/riscv/isa/formats/amo.isa
index 80a5faa..ea4e148 100644
--- a/src/arch/riscv/isa/formats/amo.isa
+++ b/src/arch/riscv/isa/formats/amo.isa
@@ -33,103 +33,6 @@
//
// Atomic memory operation instructions
//
-output header {{
-class LoadReserved : public RiscvStaticInst
-{
- protected:
-Request::Flags memAccessFlags;
-
-LoadReserved(const char *mnem, ExtMachInst _machInst,
-OpClass __opClass)
-: RiscvStaticInst(mnem, _machInst, __opClass)
-{}
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-
-class StoreCond : public RiscvStaticInst
-{
- protected:
-Request::Flags memAccessFlags;
-
-StoreCond(const char* mnem, ExtMachInst _machInst, OpClass
__opClass)
-: RiscvStaticInst(mnem, _machInst, __opClass)
-{}
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-
-class AtomicMemOp : public RiscvMacroInst
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move standard ops out of ISA
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6022
Change subject: arch-riscv: Move standard ops out of ISA
..
arch-riscv: Move standard ops out of ISA
This patch removes static portions of the standard instruction types
from the generated ISA code and puts them into arch/riscv/insts. Some
dynamicallly-generated content is left behind for each individual
instruction's implementation.
Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/standard.cc
A src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/isa/includes.isa
6 files changed, 178 insertions(+), 141 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index 95e6afd..fe90280 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,4 +1,5 @@
Import('*')
if env['TARGET_ISA'] == 'riscv':
+Source('standard.cc')
Source('static_inst.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/bitfields.hh
b/src/arch/riscv/insts/bitfields.hh
new file mode 100644
index 000..45744e0
--- /dev/null
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -0,0 +1,9 @@
+#ifndef __ARCH_RISCV_BITFIELDS_HH__
+#define __ARCH_RISCV_BITFIELDS_HH__
+
+#include "base/bitfield.hh"
+
+#define CSRIMM bits(machInst, 19, 15)
+#define FUNCT12 bits(machInst, 31, 20)
+
+#endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
new file mode 100644
index 000..a87fb7a
--- /dev/null
+++ b/src/arch/riscv/insts/standard.cc
@@ -0,0 +1,36 @@
+#include "arch/riscv/insts/standard.hh"
+
+#include
+#include
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+using namespace std;
+
+namespace RiscvISA
+{
+
+string
+RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+registerName(_srcRegIdx[0]) << ", " <<
+registerName(_srcRegIdx[1]);
+return ss.str();
+}
+
+string
+CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
+if (_numSrcRegs > 0)
+ss << registerName(_srcRegIdx[0]) << ", ";
+ss << MiscRegNames.at(csr);
+return ss.str();
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/standard.hh
b/src/arch/riscv/insts/standard.hh
new file mode 100644
index 000..e8fc63f
--- /dev/null
+++ b/src/arch/riscv/insts/standard.hh
@@ -0,0 +1,131 @@
+#ifndef __ARCH_RISCV_STANDARD_INST_HH__
+#define __ARCH_RISCV_STANDARD_INST_HH__
+
+#include
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Base class for operations that work only on registers
+ */
+class RegOp : public RiscvStaticInst
+{
+ protected:
+/// Constructor
+RegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+: RiscvStaticInst(mnem, _machInst, __opClass)
+{}
+
+std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
+ * Base class for operations with signed immediates
+ */
+class ImmOp : public RiscvStaticInst
+{
+ protected:
+int64_t imm;
+
+/// Constructor
+ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+: RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
+{}
+
+virtual std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
+};
+
+/**
+ * Base class for operations with unsigned immediates
+ */
+class UImmOp : public RiscvStaticInst
+{
+ protected:
+uint64_t imm;
+
+/// Constructor
+UImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+: RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
+{}
+
+virtual std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
+};
+
+/**
+ * Base class for operations with branching
+ */
+class BranchOp : public ImmOp
+{
+ protected:
+/// Constructor
+BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+: ImmOp(mnem, _machInst, __opClass)
+{}
+
+using StaticInst::branchTarget;
+
+virtual RiscvISA::PCState
+branchTarget(ThreadContext *tc) const
+{
+return StaticInst::branchTarget(tc);
+}
+
+virtual RiscvISA::PCState
+branchTarget(const RiscvISA::PCState &branchPC) const
+{
+return StaticInst::branchTarget(branchPC);
+}
+
+virtual std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) c
[gem5-dev] Change in public/gem5[master]: arch-riscv: Move parts of mem insts out of ISA
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6024
Change subject: arch-riscv: Move parts of mem insts out of ISA
..
arch-riscv: Move parts of mem insts out of ISA
This patch moves static portions of the memory instructions out of the
ISA generated code and puts them into arch/riscv/insts. It also
simplifies the definitions of load and store instructions by giving
them a common base class.
Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803
---
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/mem.cc
A src/arch/riscv/insts/mem.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/includes.isa
7 files changed, 112 insertions(+), 96 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index 3da7ba3..49b31f0 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,6 +1,7 @@
Import('*')
if env['TARGET_ISA'] == 'riscv':
+Source('mem.cc')
Source('standard.cc')
Source('static_inst.cc')
Source('unknown.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/bitfields.hh
b/src/arch/riscv/insts/bitfields.hh
index d664822..eac070e 100644
--- a/src/arch/riscv/insts/bitfields.hh
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -5,6 +5,9 @@
#define CSRIMM bits(machInst, 19, 15)
#define FUNCT12 bits(machInst, 31, 20)
+#define IMM5bits(machInst, 11, 7)
+#define IMM7bits(machInst, 31, 25)
+#define IMMSIGN bits(machInst, 31)
#define OPCODE bits(machInst, 6, 0)
#endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/insts/mem.cc b/src/arch/riscv/insts/mem.cc
new file mode 100644
index 000..a372d44
--- /dev/null
+++ b/src/arch/riscv/insts/mem.cc
@@ -0,0 +1,34 @@
+#include "arch/riscv/insts/mem.hh"
+
+#include
+#include
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+using namespace std;
+
+namespace RiscvISA
+{
+
+string
+Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+offset << '(' << registerName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
+string
+Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " <<
+offset << '(' << registerName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
+}
diff --git a/src/arch/riscv/insts/mem.hh b/src/arch/riscv/insts/mem.hh
new file mode 100644
index 000..c7da897
--- /dev/null
+++ b/src/arch/riscv/insts/mem.hh
@@ -0,0 +1,43 @@
+#ifndef __ARCH_RISCV_INST_MEM_HH__
+#define __ARCH_RISCV_INST_MEM_HH__
+
+#include
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+class MemInst : public RiscvStaticInst
+{
+ protected:
+int64_t offset;
+Request::Flags memAccessFlags;
+
+MemInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+: RiscvStaticInst(mnem, _machInst, __opClass), offset(0)
+{}
+
+virtual std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
+};
+
+class Load : public MemInst
+{
+ protected:
+using MemInst::MemInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
+};
+
+class Store : public MemInst
+{
+ protected:
+using MemInst::MemInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
+};
+
+}
+
+#endif // __ARCH_RISCV_INST_MEM_HH__
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index a6f8816..2cfdeea 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -48,52 +48,52 @@
}});
format CompressedLoad {
0x1: c_fld({{
-ldisp = CIMM3 << 3 | CIMM2 << 6;
+offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
Fp2_bits = Mem;
}}, {{
-EA = Rp1 + ldisp;
+EA = Rp1 + offset;
}});
0x2: c_lw({{
-ldisp = CIMM2<1:1> << 2 |
+offset = CIMM2<1:1> << 2 |
CIMM3 << 3 |
CIMM2<0:0> << 6;
}}, {{
Rp2_sd = Mem_sw;
}}, {{
-EA = Rp1 + ldisp;
+EA = Rp1 + offset;
}});
0x3: c_ld({{
-ldisp = CIMM3 << 3 | CIMM2 << 6;
+offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
Rp2_sd = Mem_sd;
}}, {{
-EA = Rp1 + ldisp;
+
[gem5-dev] Change in public/gem5[master]: arch-riscv: Add missing system calls
)},
+{182, SyscallDesc("mq_timedsend")},
+{183, SyscallDesc("mq_timedrecieve")},
+{184, SyscallDesc("mq_notify")},
+{185, SyscallDesc("mq_getsetattr")},
+{186, SyscallDesc("msgget")},
+{187, SyscallDesc("msgctl")},
+{188, SyscallDesc("msgrcv")},
+{189, SyscallDesc("msgsnd")},
+{190, SyscallDesc("semget")},
+{191, SyscallDesc("semctl")},
+{192, SyscallDesc("semtimedop")},
+{193, SyscallDesc("semop")},
+{194, SyscallDesc("shmget")},
+{195, SyscallDesc("shmctl")},
+{196, SyscallDesc("shmat")},
+{197, SyscallDesc("shmdt")},
+{198, SyscallDesc("socket")},
+{199, SyscallDesc("socketpair")},
+{200, SyscallDesc("bind")},
+{201, SyscallDesc("listen")},
+{202, SyscallDesc("accept")},
+{203, SyscallDesc("connect")},
+{204, SyscallDesc("getsockname")},
+{205, SyscallDesc("getpeername")},
+{206, SyscallDesc("sendo")},
+{207, SyscallDesc("recvfrom")},
+{208, SyscallDesc("setsockopt")},
+{209, SyscallDesc("getsockopt")},
+{210, SyscallDesc("shutdown")},
+{211, SyscallDesc("sendmsg")},
+{212, SyscallDesc("recvmsg")},
+{213, SyscallDesc("readahead")},
+{214, SyscallDesc("brk", brkFunc)},
+{215, SyscallDesc("munmap", munmapFunc)},
+{216, SyscallDesc("mremap", mremapFunc)},
+{217, SyscallDesc("add_key")},
+{218, SyscallDesc("request_key")},
+{219, SyscallDesc("keyctl")},
+{220, SyscallDesc("clone", cloneFunc)},
+{221, SyscallDesc("execve", execveFunc)},
+{222, SyscallDesc("mmap", mmapFunc)},
+{223, SyscallDesc("fadvise64")},
+{224, SyscallDesc("swapon")},
+{225, SyscallDesc("swapoff")},
+{226, SyscallDesc("mprotect", ignoreFunc)},
+{227, SyscallDesc("msync", ignoreFunc)},
+{228, SyscallDesc("mlock", ignoreFunc)},
+{229, SyscallDesc("munlock", ignoreFunc)},
+{230, SyscallDesc("mlockall", ignoreFunc)},
+{231, SyscallDesc("munlockall", ignoreFunc)},
+{232, SyscallDesc("mincore", ignoreFunc)},
+{233, SyscallDesc("madvise", ignoreFunc)},
+{234, SyscallDesc("remap_file_pages")},
+{235, SyscallDesc("mbind", ignoreFunc)},
+{236, SyscallDesc("get_mempolicy")},
+{237, SyscallDesc("set_mempolicy")},
+{238, SyscallDesc("migrate_pages")},
+{239, SyscallDesc("move_pages")},
+{240, SyscallDesc("tgsigqueueinfo")},
+{241, SyscallDesc("perf_event_open")},
+{242, SyscallDesc("accept4")},
+{243, SyscallDesc("recvmmsg")},
+{260, SyscallDesc("wait4")},
+{261, SyscallDesc("prlimit64", prlimitFunc)},
+{262, SyscallDesc("fanotify_init")},
+{263, SyscallDesc("fanotify_mark")},
+{264, SyscallDesc("name_to_handle_at")},
+{265, SyscallDesc("open_by_handle_at")},
+{266, SyscallDesc("clock_adjtime")},
+{267, SyscallDesc("syncfs")},
+{268, SyscallDesc("setns")},
+{269, SyscallDesc("sendmmsg")},
+{270, SyscallDesc("process_vm_ready")},
+{271, SyscallDesc("process_vm_writev")},
+{272, SyscallDesc("kcmp")},
+{273, SyscallDesc("finit_module")},
+{274, SyscallDesc("sched_setattr")},
+{275, SyscallDesc("sched_getattr")},
+{276, SyscallDesc("renameat2")},
+{277, SyscallDesc("seccomp")},
+{278, SyscallDesc("getrandom")},
+{279, SyscallDesc("memfd_create")},
+{280, SyscallDesc("bpf")},
+{281, SyscallDesc("execveat")},
+{282, SyscallDesc("userfaultid")},
+{283, SyscallDesc("membarrier")},
+{284, SyscallDesc("mlock2")},
+{285, SyscallDesc("copy_file_range")},
+{286, SyscallDesc("preadv2")},
+{287, SyscallDesc("pwritev2")},
{1024, SyscallDesc("open", openFunc)},
-{1025, SyscallDesc("link", unimplementedFunc)},
+{1025, SyscallDesc("link")},
{1026, SyscallDesc("unlink", unlinkFunc)},
+{1027, SyscallDesc("mknod")},
+{1028, SyscallDesc("chmod", chmodFunc)},
+{1029, SyscallDesc("chown", chownFunc)},
{1030, SyscallDesc("mkdir", mkdirFunc)},
+{1031, SyscallDesc("rmdir")},
+{1032, SyscallDesc("lchown")},
{1033, SyscallDesc("access", accessFunc)},
+{1034, SyscallDesc("rename", renameFunc)},
+{1035, SyscallDesc("readlink", readlinkFunc)},
+{1036, SyscallDesc("symlink")},
+{1037, SyscallDesc("utimes", utimesFunc)},
{1038, SyscallDesc("stat", stat64Func)},
{1039, SyscallDesc("lstat", lstat64Func)},
+{1040, SyscallDesc("pipe", pipeFunc)},
+{1041, SyscallDesc("dup2", dup2Func)},
+{1042, SyscallDesc("epoll_create")},
+{1043, SyscallDesc("inotifiy_init")},
+{1044, SyscallDesc("eventfd")},
+{1045, SyscallDesc("signalfd")},
+{1046, SyscallDesc("sendfile")},
+{1047, SyscallDesc("ftruncate", ftruncate64Func)},
+{1048, SyscallDesc("truncate", truncate64Func)},
+{1049, SyscallDesc("stat", stat64Func)},
+{1050, SyscallDesc("lstat", lstat64Func)},
+{1051, SyscallDesc("fstat", fstat64Func)},
+{1052, SyscallDesc("fcntl", fcntl64Func)},
+{1053, SyscallDesc("fadvise64")},
+{1054, SyscallDesc("newfstatat")},
+{1055, SyscallDesc("fstatfs", fstatfsFunc)},
+{1056, SyscallDesc("statfs", statfsFunc)},
+{1057, SyscallDesc("lseek", lseekFunc)},
+{1058, SyscallDesc("mmap", mmapFunc)},
+{1059, SyscallDesc("alarm")},
+{1060, SyscallDesc("getpgrp")},
+{1061, SyscallDesc("pause")},
{1062, SyscallDesc("time", timeFunc)},
-{2011, SyscallDesc("getmainvars", unimplementedFunc)},
+{1063, SyscallDesc("utime")},
+{1064, SyscallDesc("creat")},
+{1065, SyscallDesc("getdents")},
+{1066, SyscallDesc("futimesat")},
+{1067, SyscallDesc("select")},
+{1068, SyscallDesc("poll")},
+{1069, SyscallDesc("epoll_wait")},
+{1070, SyscallDesc("ustat")},
+{1071, SyscallDesc("vfork")},
+{1072, SyscallDesc("oldwait4")},
+{1073, SyscallDesc("recv")},
+{1074, SyscallDesc("send")},
+{1075, SyscallDesc("bdflush")},
+{1076, SyscallDesc("umount")},
+{1077, SyscallDesc("uselib")},
+{1078, SyscallDesc("sysctl")},
+{1079, SyscallDesc("fork")},
+{2011, SyscallDesc("getmainvars")}
};
RiscvLinuxProcess::RiscvLinuxProcess(ProcessParams * params,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9
Gerrit-Change-Number: 5322
Gerrit-PatchSet: 5
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Gabe Black
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[gem5-dev] Change in public/gem5[master]: sim-se: Add default to SyscallDesc constructor
Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/5501 )
Change subject: sim-se: Add default to SyscallDesc constructor
..
sim-se: Add default to SyscallDesc constructor
This patch adds a default value of unimplementedFunc to SyscallDesc's
constructor's second argument, which makes adding system call
placeholders to SE mode cleaner.
Change-Id: I3e7efb3a887cc52d16d2095d3dd2e2a96fb882fb
Reviewed-on: https://gem5-review.googlesource.com/5501
Reviewed-by: Gabe Black
Maintainer: Brandon Potter
---
M src/sim/syscall_desc.hh
1 file changed, 6 insertions(+), 1 deletion(-)
Approvals:
Gabe Black: Looks good to me, approved
Brandon Potter: Looks good to me, approved
diff --git a/src/sim/syscall_desc.hh b/src/sim/syscall_desc.hh
index d72803e..451db08 100644
--- a/src/sim/syscall_desc.hh
+++ b/src/sim/syscall_desc.hh
@@ -51,9 +51,13 @@
#include "base/types.hh"
class Process;
+class SyscallDesc;
class SyscallReturn;
class ThreadContext;
+SyscallReturn unimplementedFunc(SyscallDesc *desc, int num,
+Process *p, ThreadContext *tc);
+
/**
* This class provides the wrapper interface for the system call
* implementations which are defined in the sim/syscall_emul files and
@@ -66,7 +70,8 @@
typedef SyscallReturn (*SyscallExecutor)(SyscallDesc*, int num,
Process*, ThreadContext*);
-SyscallDesc(const char *name, SyscallExecutor sys_exec, int flags = 0)
+SyscallDesc(const char *name,
+SyscallExecutor sys_exec=unimplementedFunc, int flags=0)
: _name(name), executor(sys_exec), _flags(flags), _warned(false)
{
}
--
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Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I3e7efb3a887cc52d16d2095d3dd2e2a96fb882fb
Gerrit-Change-Number: 5501
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Gabe Black
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Add missing system calls
Hello Brandon Potter, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/5322 to look at the new patch set (#4). Change subject: arch-riscv: Add missing system calls .. arch-riscv: Add missing system calls This patch adds all system calls present in riscv-gnu-toolchain at commit hash 65cb174. Many of them do not have implementations in gem5, so they are just placeholders. [Remove the variadic macro and replace it with a function that has default arguments because variadic macros may not be portable across compilers] [Remove spaces around default arguments of createSyscall for better style] [Switch from using a loose function to using SyscallDesc's new constructor] Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9 --- M src/arch/riscv/linux/linux.hh M src/arch/riscv/linux/process.cc 2 files changed, 356 insertions(+), 47 deletions(-) -- To view, visit https://gem5-review.googlesource.com/5322 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9 Gerrit-Change-Number: 5322 Gerrit-PatchSet: 4 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Brandon Potter Gerrit-CC: Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: sim-se: Add default to SyscallDesc constructor
Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/5501
Change subject: sim-se: Add default to SyscallDesc constructor
..
sim-se: Add default to SyscallDesc constructor
This patch adds a default value of unimplementedFunc to SyscallDesc's
constructor's second argument, which makes adding system call
placeholders to SE mode cleaner.
Change-Id: I3e7efb3a887cc52d16d2095d3dd2e2a96fb882fb
---
M src/sim/syscall_desc.hh
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/sim/syscall_desc.hh b/src/sim/syscall_desc.hh
index d72803e..451db08 100644
--- a/src/sim/syscall_desc.hh
+++ b/src/sim/syscall_desc.hh
@@ -51,9 +51,13 @@
#include "base/types.hh"
class Process;
+class SyscallDesc;
class SyscallReturn;
class ThreadContext;
+SyscallReturn unimplementedFunc(SyscallDesc *desc, int num,
+Process *p, ThreadContext *tc);
+
/**
* This class provides the wrapper interface for the system call
* implementations which are defined in the sim/syscall_emul files and
@@ -66,7 +70,8 @@
typedef SyscallReturn (*SyscallExecutor)(SyscallDesc*, int num,
Process*, ThreadContext*);
-SyscallDesc(const char *name, SyscallExecutor sys_exec, int flags = 0)
+SyscallDesc(const char *name,
+SyscallExecutor sys_exec=unimplementedFunc, int flags=0)
: _name(name), executor(sys_exec), _flags(flags), _warned(false)
{
}
--
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Gerrit-Change-Id: I3e7efb3a887cc52d16d2095d3dd2e2a96fb882fb
Gerrit-Change-Number: 5501
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Gerrit-Owner: Alec Roelke
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[gem5-dev] Change in public/gem5[master]: sim-se: Add prlimit system call
Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/5321 )
Change subject: sim-se: Add prlimit system call
..
sim-se: Add prlimit system call
Some ISAs (namely RISC-V) implement getrlimit and setrlimit using
prlimit. This patch adds an implementation for the prlimit system call.
Normally prlimit is supposed to provide the functionality of both
getrlimit and setrlimit, but because gem5 does not support setrlimit
this implementation of prlimit will simply display a warning and return
a failure code if the setrlimit mode is used. The same thing will happen
if a pid other than 0 is passed to it.
Change-Id: I653af2d5a60e716f4d6286196be7600409efcef8
Reviewed-on: https://gem5-review.googlesource.com/5321
Maintainer: Brandon Potter
Reviewed-by: Jason Lowe-Power
---
M src/sim/syscall_emul.hh
1 file changed, 42 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Brandon Potter: Looks good to me, approved
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index fa0959f..1b4580b 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1687,6 +1687,48 @@
return 0;
}
+template
+SyscallReturn
+prlimitFunc(SyscallDesc *desc, int callnum, Process *process,
+ThreadContext *tc)
+{
+int index = 0;
+if (process->getSyscallArg(tc, index) != 0)
+{
+warn("prlimit: ignoring rlimits for nonzero pid");
+return -EPERM;
+}
+int resource = process->getSyscallArg(tc, index);
+Addr n = process->getSyscallArg(tc, index);
+if (n != 0)
+warn("prlimit: ignoring new rlimit");
+Addr o = process->getSyscallArg(tc, index);
+if (o != 0)
+{
+TypedBufferArg rlp(
+process->getSyscallArg(tc, index));
+switch (resource) {
+ case OS::TGT_RLIMIT_STACK:
+// max stack size in bytes: make up a number (8MB for now)
+rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
+rlp->rlim_cur = TheISA::htog(rlp->rlim_cur);
+rlp->rlim_max = TheISA::htog(rlp->rlim_max);
+break;
+ case OS::TGT_RLIMIT_DATA:
+// max data segment size in bytes: make up a number
+rlp->rlim_cur = rlp->rlim_max = 256*1024*1024;
+rlp->rlim_cur = TheISA::htog(rlp->rlim_cur);
+rlp->rlim_max = TheISA::htog(rlp->rlim_max);
+ default:
+warn("prlimit: unimplemented resource %d", resource);
+return -EINVAL;
+break;
+}
+rlp.copyOut(tc->getMemProxy());
+}
+return 0;
+}
+
/// Target clock_gettime() function.
template
SyscallReturn
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I653af2d5a60e716f4d6286196be7600409efcef8
Gerrit-Change-Number: 5321
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Add missing system calls
Hello Brandon Potter, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/5322 to look at the new patch set (#3). Change subject: arch-riscv: Add missing system calls .. arch-riscv: Add missing system calls This patch adds all system calls present in riscv-gnu-toolchain at commit hash 65cb174. Many of them do not have implementations in gem5, so they are just placeholders. [Remove the variadic macro and replace it with a function that has default arguments because variadic macros may not be portable across compilers] [Remove spaces around default arguments of createSyscall for better style] Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9 --- M src/arch/riscv/linux/linux.hh M src/arch/riscv/linux/process.cc 2 files changed, 370 insertions(+), 54 deletions(-) -- To view, visit https://gem5-review.googlesource.com/5322 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9 Gerrit-Change-Number: 5322 Gerrit-PatchSet: 3 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Brandon Potter Gerrit-CC: Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arch-riscv: Add missing system calls
Hello Brandon Potter, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/5322 to look at the new patch set (#2). Change subject: arch-riscv: Add missing system calls .. arch-riscv: Add missing system calls This patch adds all system calls present in riscv-gnu-toolchain at commit hash 65cb174. Many of them do not have implementations in gem5, so they are just placeholders. [Remove the variadic macro and replace it with a function that has default arguments because variadic macros may not be portable across compilers] Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9 --- M src/arch/riscv/linux/linux.hh M src/arch/riscv/linux/process.cc 2 files changed, 370 insertions(+), 54 deletions(-) -- To view, visit https://gem5-review.googlesource.com/5322 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9 Gerrit-Change-Number: 5322 Gerrit-PatchSet: 2 Gerrit-Owner: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Brandon Potter ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
