[gem5-dev] Change in gem5/gem5[master]: arch-x86,cpu-o3: Replace M5_UNREACHABLE definition for X86.
Juan Manuel Cebrián González has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28052 )
Change subject: arch-x86,cpu-o3: Replace M5_UNREACHABLE definition for X86.
..
arch-x86,cpu-o3: Replace M5_UNREACHABLE definition for X86.
Now it generates an unknown instruction instead of an exception.
This exception was not handled by the simulator and crashes it.
This situation is triggered when running deep into a mis-speculated data
path when the simulator tries to decode random data from memory.
By generating this instruction we give time to the simulator to squash the
pipeline when it realizes the wrong data path.
Change-Id: Ie552cfc6ca90e4319e7d17553086e6efae989905
---
M src/arch/isa_parser.py
M src/base/compiler.hh
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 7f09b16..f5662dd 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -2314,8 +2314,12 @@
codeObj = t[3]
# just wrap the decoding code from the block as a case in the
# outer switch statement.
-codeObj.wrap_decode_block('\n%s\n' % ''.join(case_list),
- 'M5_UNREACHABLE;\n')
+if (self.isa_name == "X86ISA"):
+codeObj.wrap_decode_block('\n%s\n' % ''.join(case_list),
+ 'M5_X86_UNREACHABLE;\n')
+else:
+codeObj.wrap_decode_block('\n%s\n' % ''.join(case_list),
+ 'M5_UNREACHABLE;\n')
codeObj.has_decode_default = (case_list == ['default:'])
t[0] = codeObj
diff --git a/src/base/compiler.hh b/src/base/compiler.hh
index 957ef40..b08f4b0 100644
--- a/src/base/compiler.hh
+++ b/src/base/compiler.hh
@@ -56,6 +56,7 @@
# define M5_DEPRECATED __attribute__((deprecated))
# define M5_DEPRECATED_MSG(MSG) __attribute__((deprecated(MSG)))
# define M5_UNREACHABLE __builtin_unreachable()
+# define M5_X86_UNREACHABLE return new Unknown(machInst)
# define M5_PUBLIC __attribute__ ((visibility ("default")))
# define M5_LOCAL __attribute__ ((visibility ("hidden")))
#endif
--
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Gerrit-Branch: master
Gerrit-Change-Id: Ie552cfc6ca90e4319e7d17553086e6efae989905
Gerrit-Change-Number: 28052
Gerrit-PatchSet: 1
Gerrit-Owner: Juan Manuel Cebrián González
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix for ruby latency
Juan Manuel Cebrián González has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28053 )
Change subject: mem-ruby: Fix for ruby latency
..
mem-ruby: Fix for ruby latency
The classic memory model clears L1 hits instantaneously and sets the 'when'
to curTick + hit_latency. Ruby models however advance the curTick instead.
Therefore the legacy '+1' adds an additional cycle to ruby L1 cache hits.
This causes significantly more front-end stalls of the o3 cpu when compared
to real Intel hardware. By applying this fix both performance and
simulation time are improved by around 30%. Front-end stalls look much
closer to real hardware with this fix.
Change-Id: I4c91dc09bff5f45f1d1e42edc13d3c15d6205c46
---
M src/mem/packet_queue.cc
M src/mem/packet_queue.hh
M src/mem/request.hh
M src/mem/ruby/system/Sequencer.cc
4 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/src/mem/packet_queue.cc b/src/mem/packet_queue.cc
index dd1ba3d..60b1889 100644
--- a/src/mem/packet_queue.cc
+++ b/src/mem/packet_queue.cc
@@ -148,12 +148,18 @@
// either the packet list is empty or this has to be inserted
// before every other packet
transmitList.emplace_front(when, pkt);
-schedSendEvent(when);
+schedSendEvent(when,pkt);
}
void
PacketQueue::schedSendEvent(Tick when)
{
+schedSendEvent(when,NULL);
+}
+
+void
+PacketQueue::schedSendEvent(Tick when, PacketPtr pkt)
+{
// if we are waiting on a retry just hold off
if (waitingOnRetry) {
DPRINTF(PacketQueue, "Not scheduling send as waiting for retry\n");
@@ -162,10 +168,20 @@
}
if (when != MaxTick) {
+// The classic memory model clears L1 hits instantaneously and
+// sets the 'when' to curTick + hit_latency. Ruby models however
+// advance the curTick instead. Therefore the legacy '+1' adds an
+// additional cycle to ruby L1 cache hits.
// we cannot go back in time, and to be consistent we stick to
// one tick in the future
-when = std::max(when, curTick() + 1);
+Tick initWhen = when;
+when = std::max(initWhen, curTick() + 1);
// @todo Revisit the +1
+if (pkt != NULL) {
+ if (pkt->req->wasHandledByRuby()) {
+when = std::max(initWhen, curTick());
+ }
+}
if (!sendEvent.scheduled()) {
em.schedule(&sendEvent, when);
diff --git a/src/mem/packet_queue.hh b/src/mem/packet_queue.hh
index b9c5b75..bac4db2 100644
--- a/src/mem/packet_queue.hh
+++ b/src/mem/packet_queue.hh
@@ -194,6 +194,12 @@
*
* @param when time to schedule an event
*/
+void schedSendEvent(Tick when, PacketPtr pkt);
+
+/**
+ * Wrapper for old schedSendEvent
+ * @param when time to schedule an event
+ */
void schedSendEvent(Tick when);
/**
diff --git a/src/mem/request.hh b/src/mem/request.hh
index aca9fe8..b127a4a 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -251,6 +251,9 @@
ARG_SEGMENT= 0x0800,
};
+/* Flag set when a packet passes through Ruby */
+bool handledByRuby;
+
private:
typedef uint16_t PrivateFlagsType;
typedef ::Flags PrivateFlags;
@@ -299,6 +302,7 @@
privateFlags.set(VALID_PADDR|VALID_SIZE);
depth = 0;
accessDelta = 0;
+handledByRuby = false;
//translateDelta = 0;
}
@@ -399,7 +403,7 @@
_extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
-{}
+{ handledByRuby = false; }
Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
InstSeqNum seq_num, ContextID cid)
@@ -540,6 +544,7 @@
accessDelta = 0;
translateDelta = 0;
atomicOpFunctor = std::move(amo_op);
+handledByRuby = false;
}
/**
@@ -908,6 +913,8 @@
bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
bool isAtomicNoReturn() const { return
_flags.isSet(ATOMIC_NO_RETURN_OP); }
+bool wasHandledByRuby() const { return handledByRuby; };
+
bool
isAtomic() const
{
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index a90523e..4f1ba2a 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -520,6 +520,8 @@
return RequestStatus_BufferFull;
}
+pkt->req->handledByRuby = true;
+
RubyRequestType primary_type = RubyRequestType_NULL;
RubyRequestType secondary_type = RubyRequestType_NULL;
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: SimpleNetwork implementation of functional reads
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/22021 )
Change subject: mem-ruby: SimpleNetwork implementation of functional reads
..
mem-ruby: SimpleNetwork implementation of functional reads
Change-Id: Id362d992cbf178f15294f0a5e9060a1de2beb394
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22021
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/Switch.cc
2 files changed, 33 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc
b/src/mem/ruby/network/simple/SimpleNetwork.cc
index 51d4dae..84817e4 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -178,9 +190,12 @@
SimpleNetwork::functionalRead(Packet *pkt)
{
for (unsigned int i = 0; i < m_switches.size(); i++) {
-if (m_switches[i]->functionalRead(pkt)) {
+if (m_switches[i]->functionalRead(pkt))
return true;
-}
+}
+for (unsigned int i = 0; i < m_int_link_buffers.size(); ++i) {
+if (m_int_link_buffers[i]->functionalRead(pkt))
+return true;
}
return false;
diff --git a/src/mem/ruby/network/simple/Switch.cc
b/src/mem/ruby/network/simple/Switch.cc
index 71b6636..d1e5026 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -1,5 +1,17 @@
/*
* Copyright (c) 2020 Inria
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -154,6 +166,10 @@
bool
Switch::functionalRead(Packet *pkt)
{
+for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
+if (m_port_buffers[i]->functionalRead(pkt))
+return true;
+}
return false;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id362d992cbf178f15294f0a5e9060a1de2beb394
Gerrit-Change-Number: 22021
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Nikos Nikoleris
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add functionalReadBuffers to AbstractController
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/22020 )
Change subject: mem-ruby: Add functionalReadBuffers to AbstractController
..
mem-ruby: Add functionalReadBuffers to AbstractController
Forwards a functional read accesses to all message buffers, similar to
functionalWriteBuffers.
Change-Id: I54b0ba16aab84575e4c9d6102f6c519b309aa95b
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22020
Tested-by: kokoro
Reviewed-by: Bradford Beckmann
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/slicc/symbols/StateMachine.py
2 files changed, 37 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Bradford Beckmann: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 1c34bde..48f9618 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -112,6 +112,7 @@
//! These functions are used by ruby system to read/write the data
blocks
//! that exist with in the controller.
+virtual bool functionalReadBuffers(PacketPtr&) = 0;
virtual void functionalRead(const Addr &addr, PacketPtr) = 0;
void functionalMemoryRead(PacketPtr);
//! The return value indicates the number of messages written with the
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 0e336e6..ee6b5fb 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2019 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
# Copyright (c) 2009 The Hewlett-Packard Development Company
# Copyright (c) 2013 Advanced Micro Devices, Inc.
@@ -313,6 +325,7 @@
Sequencer* getCPUSequencer() const;
GPUCoalescer* getGPUCoalescer() const;
+bool functionalReadBuffers(PacketPtr&);
int functionalWriteBuffers(PacketPtr&);
void countTransition(${ident}_State state, ${ident}_Event event);
@@ -1041,6 +1054,29 @@
}
''')
+# Function for functional reads to messages buffered in the
controller
+code('''
+bool
+$c_ident::functionalReadBuffers(PacketPtr& pkt)
+{
+''')
+for var in self.objects:
+vtype = var.type
+if vtype.isBuffer:
+vid = "m_%s_ptr" % var.ident
+code('if ($vid->functionalRead(pkt)) return true;')
+
+for var in self.config_parameters:
+vtype = var.type_ast.type
+if vtype.isBuffer:
+vid = "m_%s_ptr" % var.ident
+code('if ($vid->functionalRead(pkt)) return true;')
+
+code('''
+return false;
+}
+''')
+
code.write(path, "%s.cc" % c_ident)
def printCWakeup(self, path, includes):
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I54b0ba16aab84575e4c9d6102f6c519b309aa95b
Gerrit-Change-Number: 22020
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Nikos Nikoleris
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Allow MessageBuffer functional reads
onalAccess(pkt, true) == 1; +} private: void reanalyzeList(std::list &, Tick); +uint32_t functionalAccess(Packet *pkt, bool is_read); + private: // Data Members (m_ prefix) //! Consumer to signal a wakeup(), can be NULL -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/22019 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I433e9bb960680348c25bf19ace2d405109380241 Gerrit-Change-Number: 22019 Gerrit-PatchSet: 4 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Bradford Beckmann Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-CC: Nikos Nikoleris Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix Ruby handling of functional requests
cer.cc
index f815787..1f538c3 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -112,6 +124,21 @@
}
}
+int
+Sequencer::functionalWrite(Packet *func_pkt)
+{
+int num_written = RubyPort::functionalWrite(func_pkt);
+
+for (const auto &table_entry : m_RequestTable) {
+for (const auto& seq_req : table_entry.second) {
+if (seq_req.functionalWrite(func_pkt))
+++num_written;
+}
+}
+
+return num_written;
+}
+
void Sequencer::resetStats()
{
m_outstandReqHist.reset();
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 71ffa99..0569478 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -52,6 +64,15 @@
: pkt(_pkt), m_type(_m_type),
m_second_type(_m_second_type),
issue_time(_issue_time)
{}
+
+bool functionalWrite(Packet *func_pkt) const
+{
+// Follow-up on RubyRequest::functionalWrite
+// This makes sure the hitCallback won't overrite the value we
+// expect to find
+assert(func_pkt->isWrite());
+return func_pkt->trySatisfyFunctional(pkt);
+}
};
std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
@@ -103,6 +124,8 @@
void invalidateSC(Addr address);
int coreId() const { return m_coreId; }
+virtual int functionalWrite(Packet *func_pkt) override;
+
void recordRequestType(SequencerRequestType requestType);
Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; }
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index ee6b5fb..0904ac6 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -323,6 +323,7 @@
void recordCacheTrace(int cntrl, CacheRecorder* tr);
Sequencer* getCPUSequencer() const;
+DMASequencer* getDMASequencer() const;
GPUCoalescer* getGPUCoalescer() const;
bool functionalReadBuffers(PacketPtr&);
@@ -702,6 +703,12 @@
assert(param.pointer)
seq_ident = "m_%s_ptr" % param.ident
+dma_seq_ident = "NULL"
+for param in self.config_parameters:
+if param.ident == "dma_sequencer":
+assert(param.pointer)
+dma_seq_ident = "m_%s_ptr" % param.ident
+
coal_ident = "NULL"
for param in self.config_parameters:
if param.ident == "coalescer":
@@ -730,6 +737,28 @@
}
''')
+if dma_seq_ident != "NULL":
+code('''
+DMASequencer*
+$c_ident::getDMASequencer() const
+{
+if (NULL != $dma_seq_ident) {
+return $dma_seq_ident;
+} else {
+return NULL;
+}
+}
+''')
+else:
+code('''
+
+DMASequencer*
+$c_ident::getDMASequencer() const
+{
+return NULL;
+}
+''')
+
if coal_ident != "NULL":
code('''
GPUCoalescer*
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Deallocating unused entries in MOESI_CMP L2
@ -1941,6 +1948,7 @@
t_recordFwdXID;
ee_sendLocalInv;
gg_clearLocalSharers;
+removeFromDir;
m_popRequestQueue;
}
@@ -1970,6 +1978,7 @@
t_recordFwdXID;
e_sendAck;
s_deallocateTBE;
+checkCacheNoSharersNoOwner;
rr_deallocateL2CacheBlock;
m_popRequestQueue;
}
@@ -2115,12 +2124,12 @@
// LOCAL REQUESTS THAT MUST ISSUE
- transition(NP, {L1_PUTS, L1_PUTX, L1_PUTO}) {
+ transition(I, {L1_PUTS, L1_PUTX, L1_PUTO}) {
ll_writebackNack;
o_popL1RequestQueue;
}
- transition({NP, I}, L1_GETS, IGS) {
+ transition(I, L1_GETS, IGS) {
i_allocateTBE;
s_recordGetSL1ID;
a_issueGETS;
@@ -2128,7 +2137,7 @@
o_popL1RequestQueue;
}
- transition({NP, I}, L1_GETX, IGM) {
+ transition(I, L1_GETX, IGM) {
i_allocateTBE;
s_recordGetXL1ID;
a_issueGETX;
@@ -2791,7 +2800,8 @@
// L2 WRITEBACKS
- transition({I, S}, L2_Replacement, I) {
+ transition(S, L2_Replacement, I) {
+checkCacheNoSharersNoOwner;
rr_deallocateL2CacheBlock;
}
@@ -2885,12 +2895,14 @@
transition({MI, OI}, Writeback_Ack, I) {
qq_sendDataFromTBEToMemory;
+removeFromDir;
s_deallocateTBE;
n_popResponseQueue;
wa_wakeUpDependents;
}
transition(MII, Writeback_Nack, I) {
+removeFromDir;
s_deallocateTBE;
n_popResponseQueue;
wa_wakeUpDependents;
@@ -2910,6 +2922,7 @@
transition(MII, Writeback_Ack, I) {
f_sendUnblock;
+removeFromDir;
s_deallocateTBE;
n_popResponseQueue;
wa_wakeUpDependents;
--
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Gerrit-Change-Id: Id807b341a2aadb06008491545aca614d5a09b8df
Gerrit-Change-Number: 21922
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix MOESI_CMP_directory DMA handling
44 --- a/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm @@ -192,7 +192,7 @@ out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.Requestor := machineID; out_msg.RequestorMachine := MachineType:DMA; - out_msg.MessageSize := MessageSizeType:Writeback_Control; + out_msg.MessageSize := MessageSizeType:Data; } } } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/21926 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I759344ea4136cd11c3a52f9eaab2e8ce678edd04 Gerrit-Change-Number: 21926 Gerrit-PatchSet: 5 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Pouya Fotouhi Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: removed checkCoherence from MOESI_CMP_directory
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21923 )
Change subject: mem-ruby: removed checkCoherence from MOESI_CMP_directory
..
mem-ruby: removed checkCoherence from MOESI_CMP_directory
The implementation is empty and this is not used by other protocols
Change-Id: Iaed7d6d4b7ef1eb4cd47bdc0710dc9dbb7a86a0c
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21923
Reviewed-by: Jason Lowe-Power
Reviewed-by: Pouya Fotouhi
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
3 files changed, 0 insertions(+), 11 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Pouya Fotouhi: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
index b8d8ab4..d7b175c 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
@@ -215,7 +215,6 @@
((cache_entry.CacheState != State:O) && (state == State:O)) ) {
cache_entry.CacheState := state;
-sequencer.checkCoherence(addr);
}
else {
cache_entry.CacheState := state;
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index 5dfc6a9..0faa03f 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -522,13 +522,6 @@
(state == State:SLS)) {
assert(is_valid(cache_entry));
assert(L2cache.isTagPresent(addr));
-
- if ( ((cache_entry.CacheState != State:M) && (state == State:M)) ||
- ((cache_entry.CacheState != State:S) && (state == State:S)) ||
- ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
-// disable Coherence Checker for now
-// sequencer.checkCoherence(addr);
- }
} else if ( (state == State:ILS) ||
(state == State:ILX) ||
(state == State:ILO) ||
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index 6f868b4..70035e2 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -156,9 +156,6 @@
assert(getDirectoryEntry(addr).Sharers.count() == 0);
directory.deallocate(addr);
-
-// disable coherence checker
-// sequencer.checkCoherence(addr);
}
State getState(TBE tbe, Addr addr) {
--
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Gerrit-Change-Id: Iaed7d6d4b7ef1eb4cd47bdc0710dc9dbb7a86a0c
Gerrit-Change-Number: 21923
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Removed invalid transition from MOESI_CMP dir
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27848 )
Change subject: mem-ruby: Removed invalid transition from MOESI_CMP dir
..
mem-ruby: Removed invalid transition from MOESI_CMP dir
When memory data is received we always have a valid directory
entry or are in a transient state.
Change-Id: I0e9120e320c157fd306909458cbc446275a4f738
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27848
Reviewed-by: Jason Lowe-Power
Reviewed-by: Pouya Fotouhi
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Pouya Fotouhi: Looks good to me, approved
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index e8d0863..6f868b4 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -905,7 +905,7 @@
j_popIncomingUnblockQueue;
}
- transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS},
Memory_Data) {
+ transition({S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS}, Memory_Data)
{
d_sendDataMsg;
q_popMemQueue;
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I0e9120e320c157fd306909458cbc446275a4f738
Gerrit-Change-Number: 27848
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Check on PerfectCacheMemory deallocate
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21921 )
Change subject: mem-ruby: Check on PerfectCacheMemory deallocate
..
mem-ruby: Check on PerfectCacheMemory deallocate
Allowing deallocate to be called for non-existing blocks may hide
potential bugs.
Change-Id: Ida77e2db1da59d7cdb21d58968e1f17e75eaa6e0
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21921
Reviewed-by: Pouya Fotouhi
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/structures/PerfectCacheMemory.hh
1 file changed, 14 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Pouya Fotouhi: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh
b/src/mem/ruby/structures/PerfectCacheMemory.hh
index 363e3e8..9898995 100644
--- a/src/mem/ruby/structures/PerfectCacheMemory.hh
+++ b/src/mem/ruby/structures/PerfectCacheMemory.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -138,7 +150,8 @@
inline void
PerfectCacheMemory::deallocate(Addr address)
{
-m_map.erase(makeLineAddress(address));
+auto num_erased M5_VAR_USED = m_map.erase(makeLineAddress(address));
+assert(num_erased == 1);
}
// Returns with the physical address of the conflicting cache line
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ida77e2db1da59d7cdb21d58968e1f17e75eaa6e0
Gerrit-Change-Number: 21921
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Deallocating unused entries in MOESI_CMP dir
{
+DPRINTF(RubySlicc, "%s\n",
Directory_State_to_permission(dir_entry.DirectoryState));
+return Directory_State_to_permission(dir_entry.DirectoryState);
+ } else {
+DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(State:I));
+return Directory_State_to_permission(State:I);
+ }
}
-
DPRINTF(RubySlicc, "AccessPermission_NotPresent\n");
return AccessPermission:NotPresent;
}
void setAccessPermission(Addr addr, State state) {
if (directory.isPresent(addr)) {
-
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
+ Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+ if (is_valid(dir_entry)) {
+dir_entry.changePermission(Directory_State_to_permission(state));
+ } else {
+assert(state == State:I);
+ }
}
}
@@ -319,6 +346,14 @@
// Actions
+ action(allocDirEntry, "alloc", desc="Allocate directory entry") {
+allocateDirectoryEntry(address);
+ }
+
+ action(deallocDirEntry, "dealloc", desc="Deallocate directory entry") {
+deallocateDirectoryEntry(address);
+ }
+
action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
peek(requestQueue_in, RequestMsg) {
enqueue(responseNetwork_out, ResponseMsg, directory_latency) {
@@ -600,16 +635,19 @@
// TRANSITIONS
transition(I, GETX, MM) {
+allocDirEntry;
qf_queueMemoryFetchRequest;
i_popIncomingRequestQueue;
}
transition(I, DMA_READ, XI_M) {
+allocDirEntry;
qf_queueMemoryFetchRequest;
i_popIncomingRequestQueue;
}
transition(I, DMA_WRITE, XI_U) {
+allocDirEntry;
qw_queueMemoryWBFromDMARequest;
a_sendDMAAck; // ack count may be zero
i_popIncomingRequestQueue;
@@ -617,12 +655,14 @@
transition(XI_M, Memory_Data, I) {
d_sendDataMsg; // ack count may be zero
+deallocDirEntry;
q_popMemQueue;
}
transition(XI_U, Exclusive_Unblock, I) {
cc_clearSharers;
c_clearOwner;
+deallocDirEntry;
j_popIncomingUnblockQueue;
}
@@ -647,6 +687,7 @@
}
transition(I, GETS, IS) {
+allocDirEntry;
qf_queueMemoryFetchRequest;
i_popIncomingRequestQueue;
}
@@ -812,6 +853,7 @@
c_clearOwner;
cc_clearSharers;
qw_queueMemoryWBFromCacheRequest;
+deallocDirEntry;
i_popIncomingRequestQueue;
}
@@ -846,6 +888,7 @@
transition(MI, Clean_Writeback, I) {
c_clearOwner;
cc_clearSharers;
+deallocDirEntry;
i_popIncomingRequestQueue;
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I616686a78c5eddb7748192bf94bb691a4f158cbc
Gerrit-Change-Number: 27847
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add deallocate to DirectoryMemory
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21920 )
Change subject: mem-ruby: Add deallocate to DirectoryMemory
..
mem-ruby: Add deallocate to DirectoryMemory
Change-Id: Ib261ec8b302b55e539d8e13064957170412b752c
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21920
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/structures/DirectoryMemory.cc
M src/mem/ruby/structures/DirectoryMemory.hh
3 files changed, 21 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 66d84fc..fc1f7f3 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -197,6 +197,7 @@
structure (DirectoryMemory, external = "yes") {
AbstractCacheEntry allocate(Addr, AbstractCacheEntry);
AbstractCacheEntry lookup(Addr);
+ void deallocate(Addr);
bool isPresent(Addr);
void invalidateBlock(Addr);
void recordRequestType(DirectoryRequestType);
diff --git a/src/mem/ruby/structures/DirectoryMemory.cc
b/src/mem/ruby/structures/DirectoryMemory.cc
index e2ee0fc..c6e3ccf 100644
--- a/src/mem/ruby/structures/DirectoryMemory.cc
+++ b/src/mem/ruby/structures/DirectoryMemory.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -127,6 +127,7 @@
idx = mapAddressToLocalIdx(address);
assert(idx < m_num_entries);
+assert(m_entries[idx] == NULL);
entry->changePermission(AccessPermission_Read_Only);
m_entries[idx] = entry;
@@ -134,6 +135,20 @@
}
void
+DirectoryMemory::deallocate(Addr address)
+{
+assert(isPresent(address));
+uint64_t idx;
+DPRINTF(RubyCache, "Removing entry for address: %#x\n", address);
+
+idx = mapAddressToLocalIdx(address);
+assert(idx < m_num_entries);
+assert(m_entries[idx] != NULL);
+delete m_entries[idx];
+m_entries[idx] = NULL;
+}
+
+void
DirectoryMemory::print(ostream& out) const
{
}
diff --git a/src/mem/ruby/structures/DirectoryMemory.hh
b/src/mem/ruby/structures/DirectoryMemory.hh
index f879b29..3dd0e95 100644
--- a/src/mem/ruby/structures/DirectoryMemory.hh
+++ b/src/mem/ruby/structures/DirectoryMemory.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -79,6 +79,9 @@
AbstractCacheEntry *lookup(Addr address);
AbstractCacheEntry *allocate(Addr address, AbstractCacheEntry*
new_entry);
+// Explicitly free up this address
+void deallocate(Addr address);
+
void print(std::ostream& out) const;
void recordRequestType(DirectoryRequestType requestType);
--
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Gerrit-Change-Id: Ib261ec8b302b55e539d8e13064957170412b752c
Gerrit-Change-Number: 21920
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Missing transition in MOESI_CMP_directory
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21925 )
Change subject: mem-ruby: Missing transition in MOESI_CMP_directory
..
mem-ruby: Missing transition in MOESI_CMP_directory
Change-Id: I3aa9cd0230c141128ef5bddc728775b1ea6bbe14
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21925
Reviewed-by: Jason Lowe-Power
Reviewed-by: Pouya Fotouhi
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Pouya Fotouhi: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index 70035e2..64d67be 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -695,7 +695,7 @@
i_popIncomingRequestQueue;
}
- transition({I, S}, PUTO) {
+ transition({I, S}, {PUTO, PUTO_SHARERS}) {
b_sendWriteBackNack;
i_popIncomingRequestQueue;
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I3aa9cd0230c141128ef5bddc728775b1ea6bbe14
Gerrit-Change-Number: 21925
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: removed unused checkCoherence
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21924 )
Change subject: mem-ruby: removed unused checkCoherence
..
mem-ruby: removed unused checkCoherence
Change-Id: I108b95513f2828470fe70bad5f136b0721598582
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21924
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
5 files changed, 0 insertions(+), 20 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index fc1f7f3..ff574b5 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -128,7 +128,6 @@
void writeCallbackScFail(Addr, DataBlock);
bool llscCheckMonitor(Addr);
- void checkCoherence(Addr);
void evictionCallback(Addr);
void recordRequestType(SequencerRequestType);
bool checkResourceAvailable(CacheResourceType, Addr);
@@ -148,7 +147,6 @@
Cycles, Cycles, Cycles);
void writeCallback(Addr, MachineType, DataBlock,
Cycles, Cycles, Cycles, bool);
- void checkCoherence(Addr);
void evictionCallback(Addr);
void recordCPReadCallBack(MachineID, MachineID);
void recordCPWriteCallBack(MachineID, MachineID);
@@ -169,7 +167,6 @@
Cycles, Cycles, Cycles, bool);
void invCallback(Addr);
void wbCallback(Addr);
- void checkCoherence(Addr);
void evictionCallback(Addr);
}
diff --git a/src/mem/ruby/system/GPUCoalescer.cc
b/src/mem/ruby/system/GPUCoalescer.cc
index 93275cb..a7b658e 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -976,13 +976,6 @@
<< "]";
}
-// this can be called from setState whenever coherence permissions are
-// upgraded when invoked, coherence violations will be checked for the
-// given block
-void
-GPUCoalescer::checkCoherence(Addr addr)
-{
-}
void
GPUCoalescer::recordRequestType(SequencerRequestType requestType) {
diff --git a/src/mem/ruby/system/GPUCoalescer.hh
b/src/mem/ruby/system/GPUCoalescer.hh
index 1321173..3230ef1 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -176,7 +176,6 @@
bool empty() const;
void print(std::ostream& out) const;
-void checkCoherence(Addr address);
void markRemoved();
void removeRequest(GPUCoalescerRequest* request);
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index de7941a..aa134f4 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -738,14 +738,6 @@
<< "]";
}
-// this can be called from setState whenever coherence permissions are
-// upgraded when invoked, coherence violations will be checked for the
-// given block
-void
-Sequencer::checkCoherence(Addr addr)
-{
-}
-
void
Sequencer::recordRequestType(SequencerRequestType requestType) {
DPRINTF(RubyStats, "Recorded statistic: %s\n",
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index bb93607..ebca568 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -124,7 +124,6 @@
{ deschedule(deadlockCheckEvent); }
void print(std::ostream& out) const;
-void checkCoherence(Addr address);
void markRemoved();
void evictionCallback(Addr address);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I108b95513f2828470fe70bad5f136b0721598582
Gerrit-Change-Number: 21924
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix MOESI_CMP_directory functional reads
locDirEntry;
i_popIncomingRequestQueue;
}
- transition(MIS, Dirty_Writeback, S) {
+ transition(WBI, Memory_Ack, I) {
+clearWBAck;
+w_deallocateTBE;
+deallocDirEntry;
+q_popMemQueue;
+ }
+
+ transition(MIS, Dirty_Writeback, WBS) {
c_moveOwnerToSharer;
+v_allocateTBE;
qw_queueMemoryWBFromCacheRequest;
i_popIncomingRequestQueue;
}
@@ -911,18 +1004,26 @@
i_popIncomingRequestQueue;
}
- transition(OS, Dirty_Writeback, S) {
+ transition(OS, Dirty_Writeback, WBS) {
c_clearOwner;
+v_allocateTBE;
qw_queueMemoryWBFromCacheRequest;
i_popIncomingRequestQueue;
}
- transition(OSS, Dirty_Writeback, S) {
+ transition(OSS, Dirty_Writeback, WBS) {
c_moveOwnerToSharer;
+v_allocateTBE;
qw_queueMemoryWBFromCacheRequest;
i_popIncomingRequestQueue;
}
+ transition(WBS, Memory_Ack, S) {
+clearWBAck;
+w_deallocateTBE;
+q_popMemQueue;
+ }
+
transition(OSS, Clean_Writeback, S) {
c_moveOwnerToSharer;
i_popIncomingRequestQueue;
@@ -940,15 +1041,17 @@
i_popIncomingRequestQueue;
}
- transition({MI, MIS}, Unblock, M) {
-j_popIncomingUnblockQueue;
+ transition({S, O, M, SS, OO}, Memory_Data_Cache) {
+d_sendDataMsg;
+q_popMemQueue;
}
- transition({OS, OSS}, Unblock, O) {
-j_popIncomingUnblockQueue;
+ transition(IS_M, Memory_Data_Cache, IS) {
+d_sendDataMsg;
+q_popMemQueue;
}
- transition({S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS},
Memory_Data_Cache) {
+ transition(MM_M, Memory_Data_Cache, MM) {
d_sendDataMsg;
q_popMemQueue;
}
@@ -959,8 +1062,4 @@
q_popMemQueue;
}
- transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS, XI_U,
XI_M, XI_M_U}, Memory_Ack) {
-q_popMemQueue;
- }
-
}
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
index 1dc0c58..5a52b60 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
@@ -100,6 +100,7 @@
}
AccessPermission getAccessPermission(Addr addr) {
+DPRINTF(RubySlicc, "AccessPermission_NotPresent\n");
return AccessPermission:NotPresent;
}
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
index 7dc5822..2dd34e4 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
@@ -109,9 +109,7 @@
bool functionalRead(Packet *pkt) {
// Read only those messages that contain the data
-if (Type == CoherenceRequestType:DMA_READ ||
-Type == CoherenceRequestType:DMA_WRITE ||
-Type == CoherenceRequestType:WRITEBACK_CLEAN_DATA ||
+if (Type == CoherenceRequestType:WRITEBACK_CLEAN_DATA ||
Type == CoherenceRequestType:WRITEBACK_DIRTY_DATA) {
return testAndRead(addr, DataBlk, pkt);
}
--
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Gerrit-Change-Id: Ie4f6eac3b4d2641ec91ac6b168a0a017f61c0d6f
Gerrit-Change-Number: 21927
Gerrit-PatchSet: 6
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fixed MOESI_CMP_directory resource tracking
ckQueue;
@@ -980,7 +1006,6 @@
transition(MI, Dirty_Writeback, WBI) {
c_clearOwner;
cc_clearSharers;
-v_allocateTBE;
qw_queueMemoryWBFromCacheRequest;
i_popIncomingRequestQueue;
}
@@ -994,13 +1019,13 @@
transition(MIS, Dirty_Writeback, WBS) {
c_moveOwnerToSharer;
-v_allocateTBE;
qw_queueMemoryWBFromCacheRequest;
i_popIncomingRequestQueue;
}
transition(MIS, Clean_Writeback, S) {
c_moveOwnerToSharer;
+w_deallocateTBE;
i_popIncomingRequestQueue;
}
@@ -1032,6 +1057,7 @@
transition(MI, Clean_Writeback, I) {
c_clearOwner;
cc_clearSharers;
+w_deallocateTBE;
deallocDirEntry;
i_popIncomingRequestQueue;
}
@@ -1041,7 +1067,7 @@
i_popIncomingRequestQueue;
}
- transition({S, O, M, SS, OO}, Memory_Data_Cache) {
+ transition({S, SS}, Memory_Data_Cache) {
d_sendDataMsg;
q_popMemQueue;
}
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
index 5a52b60..c2eb593 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
@@ -255,6 +255,7 @@
}
action(v_allocateTBE, "v", desc="Allocate TBE entry") {
+check_allocate(TBEs);
TBEs.allocate(address);
set_tbe(TBEs[address]);
}
--
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Gerrit-Change-Id: I17016668bd64a50a4354baad5d181e6d3802ac46
Gerrit-Change-Number: 21928
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix possible MOESI_CMP deadlock
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21929 )
Change subject: mem-ruby: fix possible MOESI_CMP deadlock
..
mem-ruby: fix possible MOESI_CMP deadlock
Freeing the L2 block only after local invalidates are acked in the OLSF
state may lead to a deadlock.
Change-Id: Ia4b60e5bc9e2d3315b874a8c6616478db6eb38c1
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21929
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
1 file changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index 3c7763f..9894107 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -1910,6 +1910,9 @@
i_allocateTBE;
t_recordFwdXID;
ee_sendLocalInv;
+gg_clearLocalSharers;
+checkCacheNoSharersNoOwner;
+rr_deallocateL2CacheBlock;
m_popRequestQueue;
}
@@ -1921,10 +1924,7 @@
transition(OLSF, All_Acks, I) {
c_sendDataFromTBEToFwdGETX;
-gg_clearLocalSharers;
s_deallocateTBE;
-checkCacheNoSharersNoOwner;
-rr_deallocateL2CacheBlock;
n_popTriggerQueue;
wa_wakeUpDependents;
}
--
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Gerrit-Change-Id: Ia4b60e5bc9e2d3315b874a8c6616478db6eb38c1
Gerrit-Change-Number: 21929
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: Timothy Hayes
Gerrit-Reviewer: kokoro
Gerrit-CC: Ciro Santilli
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: MemDepUnit tracks load-acquire/store-release
st->pcState(), inst->seqNum);
@@ -268,21 +304,7 @@
void
MemDepUnit::insertNonSpec(const DynInstPtr &inst)
{
-ThreadID tid = inst->threadNumber;
-
-MemDepEntryPtr inst_entry = std::make_shared(inst);
-
-// Insert the MemDepEntry into the hash.
-memDepHash.insert(
-std::pair(inst->seqNum, inst_entry));
-#ifdef DEBUG
-MemDepEntry::memdep_insert++;
-#endif
-
-// Add the instruction to the list.
-instList[tid].push_back(inst);
-
-inst_entry->listIt = --(instList[tid].end());
+insertBarrier(inst);
// Might want to turn this part into an inline function or something.
// It's shared between both insert functions.
@@ -304,28 +326,13 @@
void
MemDepUnit::insertBarrier(const DynInstPtr &barr_inst)
{
-InstSeqNum barr_sn = barr_inst->seqNum;
-// Memory barriers block loads and stores, write barriers only stores.
-if (barr_inst->isMemBarrier()) {
-loadBarrier = true;
-loadBarrierSN = barr_sn;
-storeBarrier = true;
-storeBarrierSN = barr_sn;
-DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n",
-barr_inst->pcState(),barr_sn);
-} else if (barr_inst->isWriteBarrier()) {
-storeBarrier = true;
-storeBarrierSN = barr_sn;
-DPRINTF(MemDepUnit, "Inserted a write barrier\n");
-}
-
ThreadID tid = barr_inst->threadNumber;
MemDepEntryPtr inst_entry = std::make_shared(barr_inst);
// Add the MemDepEntry to the hash.
memDepHash.insert(
-std::pair(barr_sn, inst_entry));
+std::pair(barr_inst->seqNum,
inst_entry));
#ifdef DEBUG
MemDepEntry::memdep_insert++;
#endif
@@ -334,6 +341,8 @@
instList[tid].push_back(barr_inst);
inst_entry->listIt = --(instList[tid].end());
+
+insertBarrierSN(barr_inst);
}
template
@@ -348,7 +357,7 @@
inst_entry->regsReady = true;
-if (inst_entry->memDepReady) {
+if (inst_entry->memDeps == 0) {
DPRINTF(MemDepUnit, "Instruction has its memory "
"dependencies resolved, adding it to the ready list.\n");
@@ -430,18 +439,19 @@
{
wakeDependents(inst);
completed(inst);
-
InstSeqNum barr_sn = inst->seqNum;
-DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
-inst->seqNum);
if (inst->isMemBarrier()) {
-if (loadBarrierSN == barr_sn)
-loadBarrier = false;
-if (storeBarrierSN == barr_sn)
-storeBarrier = false;
+assert(hasLoadBarrier());
+assert(hasStoreBarrier());
+loadBarrierSNs.erase(barr_sn);
+storeBarrierSNs.erase(barr_sn);
+DPRINTF(MemDepUnit, "Memory barrier completed: %s SN:%lli\n",
+inst->pcState(), inst->seqNum);
} else if (inst->isWriteBarrier()) {
-if (storeBarrierSN == barr_sn)
-storeBarrier = false;
+assert(hasStoreBarrier());
+storeBarrierSNs.erase(barr_sn);
+DPRINTF(MemDepUnit, "Write barrier completed: %s SN:%lli\n",
+inst->pcState(), inst->seqNum);
}
}
@@ -469,10 +479,13 @@
"[sn:%lli].\n",
woken_inst->inst->seqNum);
-if (woken_inst->regsReady && !woken_inst->squashed) {
+assert(woken_inst->memDeps > 0);
+woken_inst->memDeps -= 1;
+
+if ((woken_inst->memDeps == 0) &&
+woken_inst->regsReady &&
+!woken_inst->squashed) {
moveToReady(woken_inst);
-} else {
-woken_inst->memDepReady = true;
}
}
@@ -507,11 +520,9 @@
DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
(*squash_it)->seqNum);
- if ((*squash_it)->seqNum == loadBarrierSN)
- loadBarrier = false;
+loadBarrierSNs.erase((*squash_it)->seqNum);
- if ((*squash_it)->seqNum == storeBarrierSN)
- storeBarrier = false;
+storeBarrierSNs.erase((*squash_it)->seqNum);
hash_it = memDepHash.find((*squash_it)->seqNum);
--
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Gerrit-Change-Id: I95b0c710d7c7e4a138492177e3eaaf5143e9a0ba
Gerrit-Change-Number: 27132
Gerrit-PatchSet: 6
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Giacomo Travaglini
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86,cpu: Fix bpred by annotating branch instructions in x86
X86ISA::PCState pcs = branchPC;
+DPRINTF(X86, "Br branchTarget PC info: %s, Target: %d\n",
+pcs, (int16_t)target);
+pcs.nupc(target);
+pcs.uAdvance();
+return pcs;
+}
}};
output decoder {{
@@ -174,7 +191,8 @@
"else_code": "nuIP = nuIP;",
"cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
- "cond_control_flag_init": "flags[IsCondControl] = true"})
+ "cond_control_flag_init": "flags[IsCondControl] = true; \
+ flags[IsDirectControl] = true;"})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)
decoder_output += SeqOpConstructor.subst(iop)
@@ -192,7 +210,8 @@
{"code": "", "else_code": "",
"cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
- "cond_control_flag_init": ""})
+ "cond_control_flag_init": "flags[IsUncondControl] = true;\
+ flags[IsDirectControl] = true;"})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)
decoder_output += SeqOpConstructor.subst(iop)
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 86f9339..561b482 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -749,8 +749,9 @@
DPRINTF(Decode,
"[tid:%i] [sn:%llu] "
-"Updating predictions: PredPC: %s\n",
-tid, inst->seqNum, target);
+ "Updating predictions: Wrong predicted target: %s \
+PredPC: %s\n",
+ tid, inst->seqNum, inst->readPredTarg(), target);
//The micro pc after an instruction level branch should be
0
inst->setPredTarg(target);
break;
--
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Gerrit-Change-Number: 29154
Gerrit-PatchSet: 1
Gerrit-Owner: Juan Manuel Cebrián González
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: fix store-release issuing
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27135 )
Change subject: cpu-minor: fix store-release issuing
..
cpu-minor: fix store-release issuing
Store with release flag are treated like store conditionals and are not
bufferable. Also they are only sent when the store buffer is empty to
satisfy the release semantics.
Change-Id: I253ec5ecd39901b14d0dc8efbc82cf7e4b07f08f
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27135
Reviewed-by: Anthony Gutierrez
Maintainer: Anthony Gutierrez
Tested-by: kokoro
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
---
M src/cpu/minor/lsq.cc
1 file changed, 12 insertions(+), 2 deletions(-)
Approvals:
Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index e50d498..e4a9dc0 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014,2017-2018 ARM Limited
+ * Copyright (c) 2013-2014,2017-2018,2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1029,10 +1029,11 @@
bool is_load = request->isLoad;
bool is_llsc = request->request->isLLSC();
+bool is_release = request->request->isRelease();
bool is_swap = request->request->isSwap();
bool is_atomic = request->request->isAtomic();
bool bufferable = !(request->request->isStrictlyOrdered() ||
-is_llsc || is_swap || is_atomic);
+is_llsc || is_swap || is_atomic || is_release);
if (is_load) {
if (numStoresInTransfers != 0) {
@@ -1050,6 +1051,15 @@
}
}
+// Process store conditionals or store release after all previous
+// stores are completed
+if (((!is_load && is_llsc) || is_release) &&
+!storeBuffer.isDrained()) {
+DPRINTF(MinorMem, "Memory access needs to wait for store buffer"
+ " to drain\n");
+return;
+}
+
/* Check if this is the head instruction (and so must be executable as
* its stream sequence number was checked above) for loads which must
* not be speculatively issued and stores which must be issued here */
--
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Gerrit-Change-Id: I253ec5ecd39901b14d0dc8efbc82cf7e4b07f08f
Gerrit-Change-Number: 27135
Gerrit-PatchSet: 7
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: fix store-release issuing
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27134 )
Change subject: cpu-o3: fix store-release issuing
..
cpu-o3: fix store-release issuing
Requests from stores with release semantics are only issued when they
are at the head of the store queue.
Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27134
Reviewed-by: Anthony Gutierrez
Maintainer: Anthony Gutierrez
Tested-by: kokoro
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
---
M src/cpu/o3/lsq_unit_impl.hh
1 file changed, 16 insertions(+), 1 deletion(-)
Approvals:
Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index f7fb3fe..7383c6f 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2010-2014, 2017-2019 ARM Limited
+ * Copyright (c) 2010-2014, 2017-2020 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -753,6 +753,21 @@
DynInstPtr inst = storeWBIt->instruction();
LSQRequest* req = storeWBIt->request();
+
+// Process store conditionals or store release after all previous
+// stores are completed
+if ((req->mainRequest()->isLLSC() ||
+ req->mainRequest()->isRelease()) &&
+ (storeWBIt.idx() != storeQueue.head())) {
+DPRINTF(LSQUnit, "Store idx:%i PC:%s to Addr:%#x "
+"[sn:%lli] is %s%s and not head of the queue\n",
+storeWBIt.idx(), inst->pcState(),
+req->request()->getPaddr(), inst->seqNum,
+req->mainRequest()->isLLSC() ? "SC" : "",
+req->mainRequest()->isRelease() ? "/Release" : "");
+break;
+}
+
storeWBIt->committed() = true;
assert(!inst->memData);
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Gerrit-Change-Number: 27134
Gerrit-PatchSet: 7
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Using acquire/release memory flags
::RELEASE")
+
if self.flavor in ("relex", "exclusive", "exp", "relexp"):
self.instFlags.append("IsStoreConditional")
self.memFlags.append("Request::LLSC")
--
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Gerrit-Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044
Gerrit-Change-Number: 27133
Gerrit-PatchSet: 7
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: fix IQ missing mem barriers
template
void
-MemDepUnit::completeBarrier(const DynInstPtr &inst)
+MemDepUnit::completeInst(const DynInstPtr &inst)
{
wakeDependents(inst);
completed(inst);
--
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Gerrit-Change-Id: I28b5f112b45778f6272e71bb3766b364c3d2e7db
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add memory footprint statistic
Adrià Armejach has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/29772 )
Change subject: mem: Add memory footprint statistic
..
mem: Add memory footprint statistic
Touched memory in bytes. Useful to understand if a workload is
exercising the memory hierarchy as expected.
Change-Id: I99e7558789eec1c9135a6c77b4f524e314db3964
---
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
2 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 5f0fcc7..4e15fe7 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -408,6 +408,13 @@
// the controller
bool foundInWrQ = false;
Addr burst_addr = burstAlign(addr);
+
+// Compute memory footprint
+if (!memoryAddrSet.count(burst_addr)) {
+memoryAddrSet.insert(burst_addr);
+stats.bytesMemoryFootprint += burstSize;
+}
+
// if the burst address is not present then there is no need
// looking any further
if (isInWriteQueue.find(burst_addr) != isInWriteQueue.end()) {
@@ -2636,6 +2643,8 @@
ADD_STAT(bytesReadSys, "Total read bytes from the system interface
side"),
ADD_STAT(bytesWrittenSys,
"Total written bytes from the system interface side"),
+ADD_STAT(bytesMemoryFootprint,
+ "Total memory footprint in bytes"),
ADD_STAT(avgRdBW, "Average DRAM read bandwidth in MiByte/s"),
ADD_STAT(avgWrBW, "Average achieved write bandwidth in MiByte/s"),
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 0fe78da..803cc87 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -966,6 +966,11 @@
std::unordered_set isInWriteQueue;
/**
+ * Set of accessed addresses, needed to determine memory footprint.
+ */
+std::unordered_set memoryAddrSet;
+
+/**
* Response queue where read packets wait after we're done working
* with them, but it's not time to send the response yet. The
* responses are stored separately mostly to keep the code clean
@@ -1152,6 +1157,7 @@
Stats::Scalar bytesWritten;
Stats::Scalar bytesReadSys;
Stats::Scalar bytesWrittenSys;
+Stats::Scalar bytesMemoryFootprint;
// Average bandwidth
Stats::Formula avgRdBW;
--
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Gerrit-Change-Id: I99e7558789eec1c9135a6c77b4f524e314db3964
Gerrit-Change-Number: 29772
Gerrit-PatchSet: 1
Gerrit-Owner: Adrià Armejach
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add memory controller options to fs_bigLITTLE
em_channels=options.mem_channels, bootloader=options.bootloader) root.system = system -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/29773 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I87a0ec22e56339b19ec54f678156075f045afd5e Gerrit-Change-Number: 29773 Gerrit-PatchSet: 1 Gerrit-Owner: Adrià Armejach Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: fix IQ missing mem barriers
pename std::list::iterator ListIt;
class MemDepEntry;
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh
b/src/cpu/o3/mem_dep_unit_impl.hh
index d1eac29..3a7ad36 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -435,7 +435,7 @@
template
void
-MemDepUnit::completeBarrier(const DynInstPtr &inst)
+MemDepUnit::completeInst(const DynInstPtr &inst)
{
wakeDependents(inst);
completed(inst);
--
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Gerrit-Change-Id: I28b5f112b45778f6272e71bb3766b364c3d2e7db
Gerrit-Change-Number: 29654
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MessageBuffer capacity check
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31254 ) Change subject: mem-ruby: MessageBuffer capacity check .. mem-ruby: MessageBuffer capacity check Trip assert if call enqueue on a full message buffer. Change-Id: I842183d8bf2c681787f1b6ac23c95825095ad05d Signed-off-by: Tiago Mück --- M src/mem/ruby/network/MessageBuffer.cc 1 file changed, 3 insertions(+), 0 deletions(-) diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc index 3db8515..fb1d734 100644 --- a/src/mem/ruby/network/MessageBuffer.cc +++ b/src/mem/ruby/network/MessageBuffer.cc @@ -225,6 +225,9 @@ // Increment the number of messages statistic m_buf_msgs++; +assert((m_max_size == 0) || + ((m_prio_heap.size() + m_stall_map_size) <= m_max_size)); + DPRINTF(RubyQueue, "Enqueue arrival_time: %lld, Message: %s\n", arrival_time, *(message.get())); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31254 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I842183d8bf2c681787f1b6ac23c95825095ad05d Gerrit-Change-Number: 31254 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: missing method in NetDest interface
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31262 ) Change subject: mem-ruby: missing method in NetDest interface .. mem-ruby: missing method in NetDest interface Change-Id: Ibf651c37c50174186daebebc06aa115e6bc2ed33 Signed-off-by: Tiago Mück --- M src/mem/ruby/protocol/RubySlicc_Types.sm 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm b/src/mem/ruby/protocol/RubySlicc_Types.sm index 71716f9..adbe06e 100644 --- a/src/mem/ruby/protocol/RubySlicc_Types.sm +++ b/src/mem/ruby/protocol/RubySlicc_Types.sm @@ -111,6 +111,7 @@ bool isEmpty(); bool intersectionIsEmpty(Set); bool intersectionIsEmpty(NetDest); + MachineID smallestElement(); MachineID smallestElement(MachineType); NetDest OR(NetDest); NetDest AND(NetDest); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31262 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ibf651c37c50174186daebebc06aa115e6bc2ed33 Gerrit-Change-Number: 31262 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Network can use custom data msg size
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31256 )
Change subject: mem-ruby: Network can use custom data msg size
..
mem-ruby: Network can use custom data msg size
The size for network data messages can be set using a configuration
parameter. This is necessary so line transfers may be split in multiple
messages at the protocol level.
Change-Id: I86a272de597b04a898071db412b921cbe1651ef0
Signed-off-by: Tiago Mück
---
M src/mem/ruby/network/Network.cc
M src/mem/ruby/network/Network.py
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/network/Network.cc
b/src/mem/ruby/network/Network.cc
index ba847e5..2f3a8a0 100644
--- a/src/mem/ruby/network/Network.cc
+++ b/src/mem/ruby/network/Network.cc
@@ -152,7 +152,9 @@
void
Network::init()
{
-m_data_msg_size = RubySystem::getBlockSizeBytes() + m_control_msg_size;
+fatal_if(params()->data_msg_size > RubySystem::getBlockSizeBytes(),
+ "Invalid network data message size");
+m_data_msg_size = params()->data_msg_size + m_control_msg_size;
}
uint32_t
diff --git a/src/mem/ruby/network/Network.py
b/src/mem/ruby/network/Network.py
index 5acad60..4e6ed25 100644
--- a/src/mem/ruby/network/Network.py
+++ b/src/mem/ruby/network/Network.py
@@ -25,6 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
+from m5.proxy import *
from m5.objects.ClockedObject import ClockedObject
from m5.objects.BasicLink import BasicLink
@@ -51,3 +52,8 @@
slave = VectorSlavePort("CPU slave port")
master = VectorMasterPort("CPU master port")
+
+data_msg_size = Param.Int(Parent.block_size_bytes,
+"Size of data messages. Defaults to the
parent "
+"RubySystem cache line size.")
+
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: added %(mod) operator to SLICC
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31260 )
Change subject: mem-ruby: added %(mod) operator to SLICC
..
mem-ruby: added %(mod) operator to SLICC
Change-Id: I9d1a10824ced3723d13e2843ad739ced72e476ce
Signed-off-by: Tiago Mück
---
M src/mem/slicc/ast/OperatorExprAST.py
M src/mem/slicc/parser.py
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/mem/slicc/ast/OperatorExprAST.py
b/src/mem/slicc/ast/OperatorExprAST.py
index 7752e9c..cab1369 100644
--- a/src/mem/slicc/ast/OperatorExprAST.py
+++ b/src/mem/slicc/ast/OperatorExprAST.py
@@ -64,7 +64,7 @@
elif self.op in ("<<", ">>"):
expected_types = [("int", "int", "int"),
("Cycles", "int", "Cycles")]
-elif self.op in ("+", "-", "*", "/"):
+elif self.op in ("+", "-", "*", "/", "%"):
expected_types = [("int", "int", "int"),
("Cycles", "Cycles", "Cycles"),
("Tick", "Tick", "Tick"),
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 721ca58..51a68d0 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -140,7 +140,7 @@
tokens = [ 'EQ', 'NE', 'LT', 'GT', 'LE', 'GE',
'LEFTSHIFT', 'RIGHTSHIFT',
'NOT', 'AND', 'OR',
- 'PLUS', 'DASH', 'STAR', 'SLASH',
+ 'PLUS', 'DASH', 'STAR', 'SLASH', 'MOD',
'INCR', 'DECR',
'DOUBLE_COLON', 'SEMI',
'ASSIGN', 'DOT',
@@ -165,6 +165,7 @@
t_AMP = r'&'
t_CONST = r'const'
t_SLASH = r'/'
+t_MOD = r'%'
t_DOUBLE_COLON = r'::'
t_SEMI = r';'
t_ASSIGN = r':='
@@ -180,7 +181,7 @@
('left', 'LT', 'GT', 'LE', 'GE'),
('left', 'RIGHTSHIFT', 'LEFTSHIFT'),
('left', 'PLUS', 'DASH'),
- ('left', 'STAR', 'SLASH'),
+('left', 'STAR', 'SLASH', 'MOD'),
('right', 'NOT', 'UMINUS'),
)
@@ -718,6 +719,7 @@
def p_expr__binary_op(self, p):
"""expr : expr STAR expr
| expr SLASH expr
+| expr MOD expr
| expr PLUS expr
| expr DASH expr
| expr LTexpr
--
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Gerrit-Change-Number: 31260
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: TBE table supports multiple entries
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31261 )
Change subject: mem-ruby: TBE table supports multiple entries
..
mem-ruby: TBE table supports multiple entries
allocateNext allows a new TBE to be allocated for the same address
before deallocating the current one. New entries are visible and
returned by lookup after the previous one is deallocated.
Change-Id: Ia97b1b328e1fa23b300b38402bdf381ee48b6ec7
Signed-off-by: Tiago Mück
---
M src/mem/ruby/structures/TBETable.hh
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/src/mem/ruby/structures/TBETable.hh
b/src/mem/ruby/structures/TBETable.hh
index b4a723b..1505743 100644
--- a/src/mem/ruby/structures/TBETable.hh
+++ b/src/mem/ruby/structures/TBETable.hh
@@ -42,6 +42,7 @@
#define __MEM_RUBY_STRUCTURES_TBETABLE_HH__
#include
+#include
#include
#include "mem/ruby/common/Address.hh"
@@ -51,17 +52,18 @@
{
public:
TBETable(int number_of_TBEs)
-: m_number_of_TBEs(number_of_TBEs)
+: m_size(0), m_number_of_TBEs(number_of_TBEs)
{
}
bool isPresent(Addr address) const;
+ENTRY* allocateNext(Addr address);
void allocate(Addr address);
void deallocate(Addr address);
bool
areNSlotsAvailable(int n, Tick current_time) const
{
-return (m_number_of_TBEs - m_map.size()) >= n;
+return (m_number_of_TBEs - m_size) >= n;
}
ENTRY *getNullEntry();
@@ -76,7 +78,8 @@
TBETable& operator=(const TBETable& obj);
// Data Members (m_prefix)
-std::unordered_map m_map;
+int m_size;
+std::unordered_map> m_map;
private:
int m_number_of_TBEs;
@@ -96,8 +99,8 @@
TBETable::isPresent(Addr address) const
{
assert(address == makeLineAddress(address));
-assert(m_map.size() <= m_number_of_TBEs);
-return !!m_map.count(address);
+assert(m_size <= m_number_of_TBEs);
+return m_map.count(address) > 0;
}
template
@@ -105,8 +108,17 @@
TBETable::allocate(Addr address)
{
assert(!isPresent(address));
-assert(m_map.size() < m_number_of_TBEs);
-m_map[address] = ENTRY();
+allocateNext(address);
+}
+
+template
+inline ENTRY*
+TBETable::allocateNext(Addr address)
+{
+assert(m_size < m_number_of_TBEs);
+m_map[address].emplace();
+++m_size;
+return &(m_map[address].back());
}
template
@@ -114,8 +126,12 @@
TBETable::deallocate(Addr address)
{
assert(isPresent(address));
-assert(m_map.size() > 0);
-m_map.erase(address);
+assert(m_size > 0);
+auto iter = m_map.find(address);
+iter->second.pop();
+if (iter->second.empty())
+ m_map.erase(iter);
+--m_size;
}
template
@@ -130,7 +146,8 @@
inline ENTRY*
TBETable::lookup(Addr address)
{
- if (m_map.find(address) != m_map.end()) return
&(m_map.find(address)->second);
+ if (m_map.find(address) != m_map.end())
+return &(m_map.find(address)->second.front());
return NULL;
}
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Allow same-cycle enqueue
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31255 )
Change subject: mem-ruby: Allow same-cycle enqueue
..
mem-ruby: Allow same-cycle enqueue
Messages may be enqueued and be ready in the same cycle.
Change-Id: Ib194e7b4b4ee4b06da1baea17c0eb743f650dfdd
Signed-off-by: Tiago Mück
---
M src/mem/ruby/network/MessageBuffer.cc
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mem/ruby/network/MessageBuffer.cc
b/src/mem/ruby/network/MessageBuffer.cc
index fb1d734..f2c952e 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -172,7 +172,6 @@
// Calculate the arrival time of the message, that is, the first
// cycle the message can be dequeued.
-assert(delta > 0);
Tick arrival_time = 0;
// random delays are inserted if either RubySystem level randomization
flag
@@ -193,7 +192,7 @@
}
// Check the arrival time
-assert(arrival_time > current_time);
+assert(arrival_time >= current_time);
if (m_strict_fifo) {
if (arrival_time < m_last_arrival_time) {
panic("FIFO ordering violated: %s name: %s current time: %d "
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: allow qualifiers in SLICC functions
ibutions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2009 The Hewlett-Packard Development Company # Copyright (c) 2017 Google Inc. # All rights reserved. @@ -132,7 +144,8 @@ 'INCR', 'DECR', 'DOUBLE_COLON', 'SEMI', 'ASSIGN', 'DOT', - 'IDENT', 'LIT_BOOL', 'FLOATNUMBER', 'NUMBER', 'STRING' ] + 'IDENT', 'LIT_BOOL', 'FLOATNUMBER', 'NUMBER', 'STRING', + 'AMP', 'CONST' ] tokens += reserved.values() t_EQ = r'==' @@ -149,6 +162,8 @@ t_PLUS = r'\+' t_DASH = r'-' t_STAR = r'\*' +t_AMP = r'&' +t_CONST = r'const' t_SLASH = r'/' t_DOUBLE_COLON = r'::' t_SEMI = r';' @@ -432,11 +447,19 @@ def p_param__pointer(self, p): "param : type STAR ident" -p[0] = ast.FormalParamAST(self, p[1], p[3], None, True) +p[0] = ast.FormalParamAST(self, p[1], p[3], None, "PTR") + +def p_param__ref(self, p): +"param : type AMP ident" +p[0] = ast.FormalParamAST(self, p[1], p[3], None, "REF") + +def p_param__const_ref(self, p): +"param : CONST type AMP ident" +p[0] = ast.FormalParamAST(self, p[1], p[3], None, "CONST_REF") def p_param__pointer_default(self, p): "param : type STAR ident ASSIGN STRING" -p[0] = ast.FormalParamAST(self, p[1], p[3], p[5], True) +p[0] = ast.FormalParamAST(self, p[1], p[3], p[5], "PTR") def p_param__default_number(self, p): "param : type ident ASSIGN NUMBER" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31259 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic6a18169a661b3e36710b2a9f8a0e6bc5fce40f8 Gerrit-Change-Number: 31259 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: added function to check addr range
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31263 )
Change subject: mem-ruby: added function to check addr range
..
mem-ruby: added function to check addr range
respondsTo checks if a controller address ranges includes a given
address.
Change-Id: I9a320011d93e7fd8df1ad3bda75c85d314261a99
Signed-off-by: Tiago Mück
---
M src/mem/ruby/slicc_interface/AbstractController.hh
1 file changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 750a620..5b43165 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -153,6 +153,13 @@
Stats::Histogram& getDelayVCHist(uint32_t index)
{ return *(m_delayVCHistogram[index]); }
+bool respondsTo(Addr addr)
+{
+for (auto &range: addrRanges)
+if (range.contains(addr)) return true;
+return false;
+}
+
/**
* Map an address to the correct MachineID
*
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix include dependency
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31258 )
Change subject: mem-ruby: fix include dependency
..
mem-ruby: fix include dependency
Removed include dependency between WriteMask and RubySystem.
Change-Id: I3e81267341e3875b1bb0fc3cb39f1a308e383dfd
Signed-off-by: Tiago Mück
---
M src/mem/ruby/common/WriteMask.cc
M src/mem/ruby/common/WriteMask.hh
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/mem/ruby/common/WriteMask.cc
b/src/mem/ruby/common/WriteMask.cc
index 4585077..54ba8ff 100644
--- a/src/mem/ruby/common/WriteMask.cc
+++ b/src/mem/ruby/common/WriteMask.cc
@@ -32,6 +32,11 @@
#include "mem/ruby/system/RubySystem.hh"
+WriteMask::WriteMask()
+: mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
+ mAtomic(false)
+{}
+
void
WriteMask::print(std::ostream& out) const
{
diff --git a/src/mem/ruby/common/WriteMask.hh
b/src/mem/ruby/common/WriteMask.hh
index e0eac5a..47705a0 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -46,16 +46,14 @@
#include
#include
+#include "base/amo.hh"
+#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
-#include "mem/ruby/system/RubySystem.hh"
class WriteMask
{
public:
-WriteMask()
- : mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
-mAtomic(false)
-{}
+WriteMask();
WriteMask(int size)
: mSize(size), mMask(size, false), mAtomic(false)
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: additional WriteMask methods
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31257 )
Change subject: mem-ruby: additional WriteMask methods
..
mem-ruby: additional WriteMask methods
Change-Id: Ib5d5f892075b38f46d1d802c043853f56e19ea12
Signed-off-by: Tiago Mück
---
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/protocol/RubySlicc_Exports.sm
2 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/src/mem/ruby/common/WriteMask.hh
b/src/mem/ruby/common/WriteMask.hh
index 0ba6989..e0eac5a 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2012-15 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -68,18 +80,18 @@
}
bool
-test(int offset)
+test(int offset) const
{
assert(offset < mSize);
return mMask[offset];
}
void
-setMask(int offset, int len)
+setMask(int offset, int len, bool val = true)
{
assert(mSize >= (offset + len));
for (int i = 0; i < len; i++) {
-mMask[offset + i] = true;
+mMask[offset + i] = val;
}
}
void
@@ -162,6 +174,33 @@
}
}
+void
+invMask(const WriteMask & writeMask)
+{
+assert(mSize == writeMask.mSize);
+for (int i = 0; i < mSize; i++) {
+mMask[i] = !writeMask.mMask.at(i);
+}
+}
+
+int
+firstBitSet(bool val, int offset = 0) const
+{
+for (int i = offset; i < mSize; ++i)
+if (mMask[i] == val)
+return i;
+return mSize;
+}
+
+int
+count(int offset = 0) const
+{
+int count = 0;
+for (int i = offset; i < mSize; ++i)
+count += mMask[i];
+return count;
+}
+
void print(std::ostream& out) const;
void
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index f1d17c8..077e76d 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019,2020 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -58,7 +58,16 @@
bool isFull();
bool isOverlap(WriteMask);
void orMask(WriteMask);
+ void invMask(WriteMask);
void fillMask();
+ void setMask(int,int);
+ bool getMask(int,int);
+ void setMask(int,int,bool);
+ int firstBitSet(bool);
+ int firstBitSet(bool,int);
+ int count();
+ int count(int);
+ bool test(int);
}
structure(DataBlock, external = "yes", desc="..."){
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: move AddrRange propagation to RubyPort
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31268 )
Change subject: mem-ruby: move AddrRange propagation to RubyPort
..
mem-ruby: move AddrRange propagation to RubyPort
Doing the master address range notification from the RubyPort.
This allows us the DMASequencer to be replaced by Sequencer in future
protocols.
Change-Id: I95edb54b39a8adf0cac5caf2b58e4a2efb573f56
Signed-off-by: Tiago Mück
---
M src/mem/ruby/system/DMASequencer.cc
M src/mem/ruby/system/RubyPort.cc
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mem/ruby/system/DMASequencer.cc
b/src/mem/ruby/system/DMASequencer.cc
index bad49c9..4c61dd2 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -56,9 +56,6 @@
{
RubyPort::init();
m_data_block_mask = mask(RubySystem::getBlockSizeBits());
-
-for (const auto &s_port : slave_ports)
-s_port->sendRangeChange();
}
RequestStatus
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index 0526e65..0a713b0 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -85,6 +85,8 @@
{
assert(m_controller != NULL);
m_mandatory_q_ptr = m_controller->getMandatoryQueue();
+for (const auto &s_port : slave_ports)
+s_port->sendRangeChange();
}
Port &
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Additional TBE table methods
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31272 )
Change subject: mem-ruby: Additional TBE table methods
..
mem-ruby: Additional TBE table methods
Allows checking the capacity and current size of the TBE table
Change-Id: I2f9bdfb50e2cee19d7fd8ea9c62d1dc8307b58e6
Signed-off-by: Tiago Mück
---
M src/mem/ruby/structures/TBETable.hh
1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/structures/TBETable.hh
b/src/mem/ruby/structures/TBETable.hh
index 1505743..7419c58 100644
--- a/src/mem/ruby/structures/TBETable.hh
+++ b/src/mem/ruby/structures/TBETable.hh
@@ -72,6 +72,10 @@
// Print cache contents
void print(std::ostream& out) const;
+int size() const { return m_size; }
+
+int capacity() const { return m_number_of_TBEs; }
+
private:
// Private copy constructor and assignment operator
TBETable(const TBETable& obj);
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add addressOffset util
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31270 )
Change subject: mem-ruby: add addressOffset util
..
mem-ruby: add addressOffset util
Returns the offset of an address with respect to a base address.
Looks unnecessary, but SLICC doesn't support casting and the '-'
operator for Addr types, so the alternative to this would be to add
more some helpers like 'addrToUint64' and 'uint64ToInt'.
Change-Id: I90480cec4c8b2e6bb9706f8b94ed33abe3c93e78
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Util.sm
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
2 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Util.sm
b/src/mem/ruby/protocol/RubySlicc_Util.sm
index b8b005a..70648ec 100644
--- a/src/mem/ruby/protocol/RubySlicc_Util.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Util.sm
@@ -37,6 +37,7 @@
int IDToInt(NodeID id);
int addressToInt(Addr addr);
Addr intToAddress(int addr);
+int addressOffset(Addr addr, Addr base);
int max_tokens();
Addr makeLineAddress(Addr addr);
int getOffset(Addr addr);
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index eec598a..d805e8f 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -87,6 +99,15 @@
return 1024;
}
+inline int
+addressOffset(Addr addr, Addr base)
+{
+assert(addr >= base);
+Addr offset = addr - base;
+assert(!(offset & 0x));
+return offset;
+}
+
/**
* This function accepts an address, a data block and a packet. If the
address
* range for the data block contains the address which the packet needs to
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: support for template types in structs
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31264 )
Change subject: mem-ruby: support for template types in structs
..
mem-ruby: support for template types in structs
Templated types can now be used within structures defined in SLICC.
Usage is similar to the TBETable: the templated type must have all
possible methods in it's SLICC definition. Eg.:
structure(Map, desc="Template map definition") {
MachineID lookup(Addr);
MachineID lookup(int);
}
structure(SomeType, desc="Some other struct definition") {
MachineID addrMap, template="";
MachineID intMap, template="";
}
Change-Id: I02a621cea5e4a89302762334651c6534c6574e9d
Signed-off-by: Tiago Mück
---
M src/mem/slicc/symbols/Type.py
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index fa5e79a..ee319cb 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
@@ -37,6 +49,9 @@
super(DataMember, self).__init__(symtab, ident, location, type,
code, pairs, machine)
self.init_code = init_code
+self.real_c_type = self.type.c_ident
+if "template" in pairs:
+self.real_c_type += pairs["template"]
class Enumeration(PairContainer):
def __init__(self, ident, pairs):
@@ -235,8 +250,9 @@
code('m_$ident = ${{dm["default"]}}; // default for
this field')
elif "default" in dm.type:
# Look for the type default
-tid = dm.type.c_ident
-code('m_$ident = ${{dm.type["default"]}}; // default
value of $tid')
+tid = dm.real_c_type
+code('m_$ident = ${{dm.type["default"]}};')
+code(' // default value of $tid')
else:
code('// m_$ident has no default')
code.dedent()
@@ -268,7 +284,7 @@
# Full init constructor
if not self.isGlobal:
-params = [ 'const %s& local_%s' % (dm.type.c_ident, dm.ident) \
+params = [ 'const %s& local_%s' % (dm.real_c_type, dm.ident) \
for dm in self.data_members.values() ]
params = ', '.join(params)
@@ -318,7 +334,7 @@
/** \\brief Const accessor method for ${{dm.ident}} field.
* \\return ${{dm.ident}} field
*/
-const ${{dm.type.c_ident}}&
+const ${{dm.real_c_type}}&
get${{dm.ident}}() const
{
return m_${{dm.ident}};
@@ -332,7 +348,7 @@
/** \\brief Non-const accessor method for ${{dm.ident}} field.
* \\return ${{dm.ident}} field
*/
-${{dm.type.c_ident}}&
+${{dm.real_c_type}}&
get${{dm.ident}}()
{
return m_${{dm.ident}};
@@ -345,7 +361,7 @@
code('''
/** \\brief Mutator method for ${{dm.ident}} field */
void
-set${{dm.ident}}(const ${{dm.type.c_ident}}& local_${{dm.ident}})
+set${{dm.ident}}(const ${{dm.real_c_type}}& local_${{dm.ident}})
{
m_${{dm.ident}} = local_${{dm.ident}};
}
@@ -375,7 +391,7 @@
if "desc" in dm:
code('/** ${{dm["desc"]}} */')
-code('$const${{dm.type.c_ident}} m_${{dm.ident}}$init;')
+code('$const${{dm.real_c_type}} m_${{dm.ident}}$init;')
# Prototypes for methods defined for the Type
for item in self.methods:
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: int to Cycle converter
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31266 )
Change subject: mem-ruby: int to Cycle converter
..
mem-ruby: int to Cycle converter
Change-Id: I493b16a0bdd01a4cef4891e273a376ebe9509fe8
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Util.sm
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Util.sm
b/src/mem/ruby/protocol/RubySlicc_Util.sm
index f509d09..b8b005a 100644
--- a/src/mem/ruby/protocol/RubySlicc_Util.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Util.sm
@@ -32,6 +32,7 @@
void error(std::string msg);
void assert(bool condition);
Cycles zero_time();
+Cycles intToCycles(int c);
NodeID intToID(int nodenum);
int IDToInt(NodeID id);
int addressToInt(Addr addr);
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index e3d4f0b..eec598a 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -46,6 +46,8 @@
inline Cycles zero_time() { return Cycles(0); }
+inline Cycles intToCycles(int c) { return Cycles(c); }
+
inline NodeID
intToID(int nodenum)
{
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Expose MessageBuffer methods
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31271 )
Change subject: mem-ruby: Expose MessageBuffer methods
..
mem-ruby: Expose MessageBuffer methods
SLICC interface for checking the capacity of MessageBuffers
Change-Id: I28e2d22a405d33fcbe6a183dffc31bd936fa26c4
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index cb24d3a..86895fc 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -48,7 +48,11 @@
// undefined declaration error.
//
-external_type(MessageBuffer, buffer="yes", inport="yes", outport="yes");
+structure(MessageBuffer, buffer="yes", inport="yes", outport="yes",
external = "yes", primitive="yes") {
+ bool areNSlotsAvailable(int n, Tick curTime);
+ int getSize(Tick curTime);
+}
+
external_type(Scalar, primitive="yes");
structure(OutPort, external = "yes", primitive="yes") {
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: sequencer callback for unique writes
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31269 )
Change subject: mem-ruby: sequencer callback for unique writes
..
mem-ruby: sequencer callback for unique writes
A controller may complete a write without obtaining a full copy of
the line. This patch adds a specific callback for this purpose that
prevents reads to be coalesced with a write on a potentially incomplete
line.
Change-Id: I3775f81699f38e406fee28f92c9c8e06deb3d528
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index adbe06e..cb24d3a 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -129,6 +129,7 @@
void writeCallback(Addr, DataBlock, bool, MachineType);
void writeCallback(Addr, DataBlock, bool, MachineType,
Cycles, Cycles, Cycles);
+ void writeUniqueCallback(Addr, DataBlock);
// ll/sc support
void writeCallbackScFail(Addr, DataBlock);
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index b6b1ae3..d7c3e15 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -340,7 +340,8 @@
const bool externalHit, const MachineType mach,
const Cycles initialRequestTime,
const Cycles forwardRequestTime,
- const Cycles firstResponseTime)
+ const Cycles firstResponseTime,
+ const bool noCoales)
{
//
// Free the whole list as we assume we have had the exclusive access
@@ -358,6 +359,15 @@
int aliased_loads = 0;
while (!seq_req_list.empty()) {
SequencerRequest &seq_req = seq_req_list.front();
+
+if (noCoales && !ruby_request) {
+// Do not process follow-up requests
+// (e.g. if full line no present)
+// Reissue to the cache hierarchy
+issueRequest(seq_req.pkt, seq_req.m_second_type);
+break;
+}
+
if (ruby_request) {
assert(seq_req.m_type != RubyRequestType_LD);
assert(seq_req.m_type != RubyRequestType_Load_Linked);
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 594b4f7..b4da03f 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -103,7 +103,15 @@
const MachineType mach = MachineType_NUM,
const Cycles initialRequestTime = Cycles(0),
const Cycles forwardRequestTime = Cycles(0),
- const Cycles firstResponseTime = Cycles(0));
+ const Cycles firstResponseTime = Cycles(0),
+ const bool noCoales = false);
+
+// Write callback that prevents coalescing
+void writeUniqueCallback(Addr address, DataBlock& data)
+{
+writeCallback(address, data, true, MachineType_NUM, Cycles(0),
+ Cycles(0), Cycles(0), true);
+}
void readCallback(Addr address,
DataBlock& data,
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: able to define resource stalls handlers
ce code or in binary form.
+#
# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
@@ -118,7 +130,9 @@
rcode = self.slicc.codeFormatter()
rcode.indent()
rcode.indent()
+machine.curr_in_port_code_gen = in_port
self.statements.generate(rcode, None)
+machine.curr_in_port_code_gen = None
in_port["c_code_in_port"] = str(rcode)
symtab.popFrame()
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Sequencer can be used without cache
omain=clk_domain,
ruby_system=ruby_system)
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index c83bb72..1e00f0f 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -109,7 +109,7 @@
clk_domain=clk_domain,
ruby_system=ruby_system)
-cpu_seq = RubySequencer(version=i, icache=l1i_cache,
+cpu_seq = RubySequencer(version=i,
dcache=l1d_cache,clk_domain=clk_domain,
ruby_system=ruby_system)
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index aa134f4..b6b1ae3 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -72,7 +72,6 @@
{
m_outstanding_count = 0;
-m_instCache_ptr = p->icache;
m_dataCache_ptr = p->dcache;
m_max_outstanding_requests = p->max_outstanding_requests;
m_deadlock_threshold = p->deadlock_threshold;
@@ -80,8 +79,6 @@
m_coreId = p->coreid; // for tracking the two CorePair sequencers
assert(m_max_outstanding_requests > 0);
assert(m_deadlock_threshold > 0);
-assert(m_instCache_ptr != NULL);
-assert(m_dataCache_ptr != NULL);
m_runningGarnetStandalone = p->garnet_standalone;
}
@@ -93,6 +90,7 @@
void
Sequencer::llscLoadLinked(const Addr claddr)
{
+assert(m_dataCache_ptr != NULL);
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (line) {
line->setLocked(m_version);
@@ -104,6 +102,7 @@
void
Sequencer::llscClearMonitor(const Addr claddr)
{
+assert(m_dataCache_ptr != NULL);
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (line && line->isLocked(m_version)) {
line->clearLocked();
@@ -115,6 +114,7 @@
bool
Sequencer::llscStoreConditional(const Addr claddr)
{
+assert(m_dataCache_ptr != NULL);
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (!line)
return false;
@@ -136,6 +136,7 @@
bool
Sequencer::llscCheckMonitor(const Addr address)
{
+assert(m_dataCache_ptr != NULL);
const Addr claddr = makeLineAddress(address);
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (!line)
@@ -747,7 +748,8 @@
void
Sequencer::evictionCallback(Addr address)
{
-llscClearMonitor(address);
+if (m_dataCache_ptr != NULL)
+llscClearMonitor(address);
ruby_eviction_callback(address);
}
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index ebca568..594b4f7 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -206,7 +206,6 @@
Cycles m_deadlock_threshold;
CacheMemory* m_dataCache_ptr;
-CacheMemory* m_instCache_ptr;
// The cache access latency for top-level caches (L0/L1). These are
// currently assessed at the beginning of each memory access through
the
diff --git a/src/mem/ruby/system/Sequencer.py
b/src/mem/ruby/system/Sequencer.py
index 781f77c..0a231a9 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2009 Advanced Micro Devices, Inc.
# All rights reserved.
#
@@ -58,7 +70,6 @@
cxx_class = 'Sequencer'
cxx_header = "mem/ruby/system/Sequencer.hh"
- icache = Param.RubyCache("")
dcache = Param.RubyCache("")
max_outstanding_requests = Param.Int(16,
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: expose transition info to actions
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31420 )
Change subject: mem-ruby: expose transition info to actions
..
mem-ruby: expose transition info to actions
SLICC compiler generates the curTransitionEvent and
curTransitionNextState functions, which allows actions to check which
event triggered the current transition and what's the next state.
Change-Id: I79c8c4f2839633b7fb3b23cbbdbb32f25db90eab
Signed-off-by: Tiago Mück
---
M src/mem/slicc/symbols/StateMachine.py
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 1f28069..90c74d2 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -380,6 +380,12 @@
code('''
Addr addr);
+${ident}_Event m_curTransitionEvent;
+${ident}_State m_curTransitionNextState;
+
+${ident}_Event curTransitionEvent() { return m_curTransitionEvent; }
+${ident}_State curTransitionNextState() { return m_curTransitionNextState;
}
+
int m_counters[${ident}_State_NUM][${ident}_Event_NUM];
int m_event_counters[${ident}_Event_NUM];
bool m_possible[${ident}_State_NUM][${ident}_Event_NUM];
@@ -1428,6 +1434,8 @@
code('''
Addr addr)
{
+m_curTransitionEvent = event;
+m_curTransitionNextState = next_state;
switch(HASH_FUN(state, event)) {
''')
@@ -1448,10 +1456,12 @@
# is determined before any actions of the transition
# execute, and therefore the next state calculation
cannot
# depend on any of the transitionactions.
-case('next_state = getNextState(addr);')
+case('next_state = getNextState(addr); '
+ 'm_curTransitionNextState = next_state;')
else:
ns_ident = trans.nextState.ident
-case('next_state = ${ident}_State_${ns_ident};')
+case('next_state = ${ident}_State_${ns_ident}; '
+ 'm_curTransitionNextState = next_state;')
actions = trans.actions
request_types = trans.request_types
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: functions for connecting sequencer ports
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31417 ) Change subject: mem-ruby: functions for connecting sequencer ports .. mem-ruby: functions for connecting sequencer ports Added functions for connecting the sequencer and cpu ports. Using these functions instead of wiring up the ports directly allow protocols to provide specialized sequencer implementations. For instance, connecting the cpu icache_port and dcache_port to different sequencer ports or to different sequencers. A follow-up patch will update the configurations to use these functions. Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b Signed-off-by: Tiago Mück --- M src/mem/ruby/system/Sequencer.py M tests/gem5/cpu_tests/ref/Bubblesort 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 0a231a9..d6e9bfb 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -81,6 +81,16 @@ # 99 is the dummy default value coreid = Param.Int(99, "CorePair core id") + def connectCpuPorts(self, cpu): + assert(isinstance(cpu, BaseCPU)) + cpu.connectAllPorts(self) + + def connectInstPort(self, object, portname): + setattr(object, portname, self.slave) + + def connectDataPort(self, object, portname): + setattr(object, portname, self.slave) + class DMASequencer(RubyPort): type = 'DMASequencer' cxx_header = "mem/ruby/system/DMASequencer.hh" diff --git a/tests/gem5/cpu_tests/ref/Bubblesort b/tests/gem5/cpu_tests/ref/Bubblesort index 79d2ae3..e69de29 100644 --- a/tests/gem5/cpu_tests/ref/Bubblesort +++ b/tests/gem5/cpu_tests/ref/Bubblesort @@ -1,6 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - - -Global frequency set at 1 ticks per second --5 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31417 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b Gerrit-Change-Number: 31417 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: change MessageBuffer randomization param
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31419 )
Change subject: mem-ruby: change MessageBuffer randomization param
..
mem-ruby: change MessageBuffer randomization param
There are cases in which we need to prevent randomization for a
specific buffer when enabled at the RubySystem level (e.g. a internal
trigger queue that requires zero latency enqueue, while other buffers
can be randomized).
This changes the randomization parameter to support enabling and
disabling randomization regardless of the RubySystem setting.
Change-Id: If7520153cc5864897fa42e8911a6f8acbcf01db5
Signed-off-by: Tiago Mück
---
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/network/MessageBuffer.py
3 files changed, 27 insertions(+), 9 deletions(-)
diff --git a/src/mem/ruby/network/MessageBuffer.cc
b/src/mem/ruby/network/MessageBuffer.cc
index 8fe59ea..a943ea5 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -174,9 +174,11 @@
// cycle the message can be dequeued.
Tick arrival_time = 0;
-// random delays are inserted if either RubySystem level randomization
flag
-// is turned on, or the buffer level randomization is set
-if (!RubySystem::getRandomization() && !m_randomization) {
+// random delays are inserted if the RubySystem level randomization
flag
+// is turned on and this buffer allows it
+if ((m_randomization == MessageRandomization::disabled) ||
+((m_randomization == MessageRandomization::ruby_system) &&
+ !RubySystem::getRandomization())) {
// No randomization
arrival_time = current_time + delta;
} else {
diff --git a/src/mem/ruby/network/MessageBuffer.hh
b/src/mem/ruby/network/MessageBuffer.hh
index f10c834..15e1b65 100644
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -254,7 +254,7 @@
uint64_t m_msg_counter;
int m_priority_rank;
const bool m_strict_fifo;
-const bool m_randomization;
+const MessageRandomization m_randomization;
int m_input_link_id;
int m_vnet_id;
diff --git a/src/mem/ruby/network/MessageBuffer.py
b/src/mem/ruby/network/MessageBuffer.py
index 689ec62..f477519 100644
--- a/src/mem/ruby/network/MessageBuffer.py
+++ b/src/mem/ruby/network/MessageBuffer.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2015 Mark D. Hill and David A. Wood.
# All rights reserved.
#
@@ -28,6 +40,13 @@
from m5.proxy import *
from m5.SimObject import SimObject
+# A MessageBuffer inserts random delays to enqueued messages when the
+# randomization param is set to 'enabled' or when globally enabled for the
+# RubySystem and the param is set to 'ruby_system' (default). 'disabled'
+# completely prevents randomization.
+class MessageRandomization(ScopedEnum):
+vals = ['disabled', 'enabled', 'ruby_system']
+
class MessageBuffer(SimObject):
type = 'MessageBuffer'
cxx_class = 'MessageBuffer'
@@ -35,10 +54,7 @@
ordered = Param.Bool(False, "Whether the buffer is ordered")
buffer_size = Param.Unsigned(0, "Maximum number of entries to buffer \
(0 allows infinite entries)")
-randomization = Param.Bool(False, "Insert random delays on message \
- enqueue times (enforced to have \
- random delays if RubySystem \
- randomization flag is True)")
-
+randomization = Param.MessageRandomization('ruby_system',
+ "Randomization parameter")
master = MasterPort("Master port to MessageBuffer receiver")
slave = SlavePort("Slave port from MessageBuffer sender")
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: detailed transaction latency profiling
sLatHist." +
+${ident}_Event_to_string(event));
+t->flags(Stats::pdf | Stats::total |
+ Stats::oneline | Stats::nozero);
+}
+for (${ident}_Event event = ${ident}_Event_FIRST;
+ event < ${ident}_Event_NUM; ++event) {
+m_inTransLatHist.emplace_back();
+for (${ident}_State initial_state = ${ident}_State_FIRST;
+ initial_state < ${ident}_State_NUM; ++initial_state) {
+m_inTransLatHist.back().emplace_back();
+for (${ident}_State final_state = ${ident}_State_FIRST;
+ final_state < ${ident}_State_NUM; ++final_state) {
+Stats::Histogram* t = new Stats::Histogram;
+m_inTransLatHist.back().back().push_back(t);
+t->init(5);
+t->name(name() + ".inTransLatHist." +
+${ident}_Event_to_string(event) + "." +
+${ident}_State_to_string(initial_state) + "." +
+${ident}_State_to_string(final_state));
+t->flags(Stats::pdf | Stats::total |
+ Stats::oneline | Stats::nozero);
+}
+}
+}
}
void
--
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[gem5-dev] Change in gem5/gem5[develop]: configs,tests: use Sequencer port connect methods
lave
-system.cpu[i].interrupts[0].int_slave = ruby_port.master
-system.cpu[i].itb.walker.port = ruby_port.slave
-system.cpu[i].dtb.walker.port = ruby_port.slave
+ruby_port.connectCpuPorts(system.cpu[i])
else:
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 7aca77f..12d3ce3 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -100,7 +100,7 @@
# Tie the cpu port to the ruby cpu ports and
# physmem, respectively
#
- cpus[i].port = ruby_port.slave
+ ruby_port.connectDataPort(cpus[i], 'port')
#
# Since the memtester is incredibly bursty, increase the deadlock
diff --git a/tests/configs/pc-simple-timing-ruby.py
b/tests/configs/pc-simple-timing-ruby.py
index 06a3efc..884fd7d 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -78,14 +78,7 @@
# create the interrupt controller
cpu.createInterruptController()
# Tie the cpu ports to the correct ruby system ports
-cpu.icache_port = system.ruby._cpu_ports[i].slave
-cpu.dcache_port = system.ruby._cpu_ports[i].slave
-cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
-cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
-
-cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
-cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
-cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
+system.ruby._cpu_ports[i].connectCpuPorts(cpu)
root = Root(full_system = True, system = system)
m5.ticks.setGlobalFrequency('1THz')
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 5c01cff..cf7c43b 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -101,11 +101,11 @@
# Tie the ruby tester ports to the ruby cpu read and write ports
#
if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
-tester.cpuInstDataPort = ruby_port.slave
+ruby_port.connectDataPort(tester, 'cpuInstDataPort')
elif ruby_port.support_data_reqs:
-tester.cpuDataPort = ruby_port.slave
+ruby_port.connectDataPort(tester, 'cpuDataPort')
elif ruby_port.support_inst_reqs:
-tester.cpuInstPort = ruby_port.slave
+ruby_port.connectInstPort(tester, 'cpuInstPort')
# Do not automatically retry stalled Ruby requests
ruby_port.no_retry_on_stall = True
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: more specialized address to node mapping
nterface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 5b43165..81c17d1 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017,2019 ARM Limited
+ * Copyright (c) 2017,2019,2020 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -44,6 +44,7 @@
#include
#include
#include
+#include
#include "base/addr_range.hh"
#include "base/callback.hh"
@@ -175,6 +176,21 @@
*/
MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
+/**
+ * Maps an address to the correct dowstream MachineID
+ *
+ * This function uses the local list of possible destinations instead
of
+ * querying the network.
+ *
+ * @param the destination address
+ * @param the type of the destination (optional)
+ * @return the MachineID of the destination
+ */
+MachineID mapAddressToDownstreamMachine(Addr addr,
+MachineType mtype = MachineType_NUM)
const;
+
+const NetDest& allDownstreamDest() const { return
downstreamDestinations; }
+
protected:
//! Profiles original cache requests including PUTs
void profileRequest(const std::string &request);
@@ -273,6 +289,15 @@
private:
/** The address range to which the controller responds on the CPU
side. */
const AddrRangeList addrRanges;
+
+struct AddrMapNode {
+NodeID id;
+AddrRangeList ranges;
+};
+std::unordered_multimap downstreamAddrMap;
+
+NetDest downstreamDestinations;
+
};
#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
diff --git a/src/mem/ruby/slicc_interface/Controller.py
b/src/mem/ruby/slicc_interface/Controller.py
index ae4263c..4647678 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017,2019 ARM Limited
+# Copyright (c) 2017,2019,2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -68,3 +68,8 @@
memory = MasterPort("Port for attaching a memory controller")
system = Param.System(Parent.any, "system object parameter")
+
+# These can be used by a protocol to enable reuse of the same machine
+# types to model different levels of the cache hierarchy
+downstream_destinations = VectorParam.RubyController([],
+"Possible destinations for requests sent towards
memory")
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: alternative interface for func. reads
ol
+$c_ident::functionalReadBuffers(PacketPtr& pkt, WriteMask &mask)
+{
+bool read = false;
+''')
+for var in self.objects:
+vtype = var.type
+if vtype.isBuffer:
+vid = "m_%s_ptr" % var.ident
+code('if ($vid->functionalRead(pkt, mask)) read = true;')
+
+ for var in self.config_parameters:
+vtype = var.type_ast.type
+if vtype.isBuffer:
+vid = "m_%s_ptr" % var.ident
+code('if ($vid->functionalRead(pkt, mask)) read = true;')
+
+code('''
+return read;
+}
''')
code.write(path, "%s.cc" % c_ident)
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache,python: Allow custom TLB and events in each prefetcher.
Isaac Sánchez Barrera has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32394 )
Change subject: mem-cache,python: Allow custom TLB and events in each
prefetcher.
..
mem-cache,python: Allow custom TLB and events in each prefetcher.
The `BasePrefetcher` python class had members `_events` and `_tlbs`
defined as lists, meaning that any call to `list.append` on them would
affect `_events` and `_tlbs` for all prefetchers, not just the calling
object. This change redefines them as `None` by default and sets the
value to a per-object empty list before inserting the first element.
Change-Id: I68feb1d6d78e2fa5e8775afba8c81c6dd0de6c60
Signed-off by: Isaac Sánchez Barrera
---
M src/mem/cache/prefetch/Prefetcher.py
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index f131ccf..d6a01b9 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -80,17 +80,21 @@
use_virtual_addresses = Param.Bool(False,
"Use virtual addresses for prefetching")
-_events = []
+_events = None
def addEvent(self, newObject):
+if not self._events:
+self._events = []
self._events.append(newObject)
# Override the normal SimObject::regProbeListeners method and
# register deferred event handlers.
def regProbeListeners(self):
-for tlb in self._tlbs:
-self.getCCObject().addTLB(tlb.getCCObject())
-for event in self._events:
- event.register()
+if self._tlbs:
+for tlb in self._tlbs:
+self.getCCObject().addTLB(tlb.getCCObject())
+if self._events:
+for event in self._events:
+event.register()
self.getCCObject().regProbeListeners()
def listenFromProbe(self, simObj, *probeNames):
@@ -99,10 +103,13 @@
if len(probeNames) <= 0:
raise TypeError("probeNames must have at least one element")
self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
-_tlbs = []
+
+_tlbs = None
def registerTLB(self, simObj):
if not isinstance(simObj, SimObject):
raise TypeError("argument must be a SimObject type")
+if not self._tlbs:
+self._tlbs = []
self._tlbs.append(simObj)
class MultiPrefetcher(BasePrefetcher):
--
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Gerrit-Owner: Isaac Sánchez Barrera
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache,python: Allow custom TLB and events in each prefetcher.
Isaac Sánchez Barrera has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32394 )
Change subject: mem-cache,python: Allow custom TLB and events in each
prefetcher.
..
mem-cache,python: Allow custom TLB and events in each prefetcher.
The `BasePrefetcher` python class had members `_events` and `_tlbs`
defined as lists, meaning that any call to `list.append` on them would
affect `_events` and `_tlbs` for all prefetchers, not just the calling
object. This change redefines them as instance members to fix the
problem.
Change-Id: I68feb1d6d78e2fa5e8775afba8c81c6dd0de6c60
Signed-off-by: Isaac Sánchez Barrera
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32394
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Nikos Nikoleris
---
M src/mem/cache/prefetch/Prefetcher.py
1 file changed, 7 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index f131ccf..c163028 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -80,7 +80,11 @@
use_virtual_addresses = Param.Bool(False,
"Use virtual addresses for prefetching")
-_events = []
+def __init__(self, **kwargs):
+super(BasePrefetcher, self).__init__(**kwargs)
+self._events = []
+self._tlbs = []
+
def addEvent(self, newObject):
self._events.append(newObject)
@@ -90,7 +94,7 @@
for tlb in self._tlbs:
self.getCCObject().addTLB(tlb.getCCObject())
for event in self._events:
- event.register()
+event.register()
self.getCCObject().regProbeListeners()
def listenFromProbe(self, simObj, *probeNames):
@@ -99,7 +103,7 @@
if len(probeNames) <= 0:
raise TypeError("probeNames must have at least one element")
self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
-_tlbs = []
+
def registerTLB(self, simObj):
if not isinstance(simObj, SimObject):
raise TypeError("argument must be a SimObject type")
--
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Gerrit-Change-Number: 32394
Gerrit-PatchSet: 4
Gerrit-Owner: Isaac Sánchez Barrera
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Isaac Sánchez Barrera
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: ZHENGRONG WANG
Gerrit-Reviewer: kokoro
Gerrit-CC: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86,cpu: Fix bpred by annotating branch instructions in x86
branchTarget
+using StaticInst::branchTarget;
};
}};
@@ -101,6 +107,17 @@
%(constructor)s;
%(cond_control_flag_init)s;
}
+
+X86ISA::PCState
+%(class_name)s::branchTarget(const X86ISA::PCState &branchPC) const
+{
+X86ISA::PCState pcs = branchPC;
+DPRINTF(X86, "Br branchTarget PC info: %s, Target: %d\n",
+pcs, (int16_t)target);
+pcs.nupc(target);
+pcs.uAdvance();
+return pcs;
+}
}};
output decoder {{
@@ -173,7 +190,8 @@
"else_code": "nuIP = nuIP;",
"cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
- "cond_control_flag_init": "flags[IsCondControl] = true"})
+ "cond_control_flag_init": "flags[IsCondControl] = true; \
+ flags[IsDirectControl] = true;"})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)
decoder_output += SeqOpConstructor.subst(iop)
@@ -191,7 +209,8 @@
{"code": "", "else_code": "",
"cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
- "cond_control_flag_init": ""})
+ "cond_control_flag_init": "flags[IsUncondControl] = true;\
+ flags[IsDirectControl] = true;"})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)
decoder_output += SeqOpConstructor.subst(iop)
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 968bbc7..cf3d601 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -747,8 +747,9 @@
DPRINTF(Decode,
"[tid:%i] [sn:%llu] "
-"Updating predictions: PredPC: %s\n",
-tid, inst->seqNum, target);
+ "Updating predictions: Wrong predicted target: %s \
+PredPC: %s\n",
+ tid, inst->seqNum, inst->readPredTarg(), target);
//The micro pc after an instruction level branch should be
0
inst->setPredTarg(target);
break;
--
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Gerrit-PatchSet: 2
Gerrit-Owner: Juan Manuel Cebrián González
Gerrit-Reviewer: Alexandru Duțu
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Juan Manuel Cebrián González
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Network can use custom data msg size
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31256 )
Change subject: mem-ruby: Network can use custom data msg size
..
mem-ruby: Network can use custom data msg size
The size for network data messages can be set using a configuration
parameter. This is necessary so line transfers may be split in multiple
messages at the protocol level.
Change-Id: I86a272de597b04a898071db412b921cbe1651ef0
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31256
Reviewed-by: Jason Lowe-Power
Reviewed-by: Srikant Bharadwaj
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/Network.cc
M src/mem/ruby/network/Network.hh
M src/mem/ruby/network/Network.py
3 files changed, 10 insertions(+), 7 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Srikant Bharadwaj: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/Network.cc
b/src/mem/ruby/network/Network.cc
index cda99b1..a676a38 100644
--- a/src/mem/ruby/network/Network.cc
+++ b/src/mem/ruby/network/Network.cc
@@ -55,6 +55,10 @@
m_virtual_networks = p->number_of_virtual_networks;
m_control_msg_size = p->control_msg_size;
+fatal_if(p->data_msg_size > p->ruby_system->getBlockSizeBytes(),
+ "%s: data message size > cache line size", name());
+m_data_msg_size = p->data_msg_size + m_control_msg_size;
+
params()->ruby_system->registerNetwork(this);
// Populate localNodeVersions with the version of each MachineType in
@@ -150,12 +154,6 @@
delete m_topology_ptr;
}
-void
-Network::init()
-{
-m_data_msg_size = RubySystem::getBlockSizeBytes() + m_control_msg_size;
-}
-
uint32_t
Network::MessageSizeType_to_int(MessageSizeType size_type)
{
diff --git a/src/mem/ruby/network/Network.hh
b/src/mem/ruby/network/Network.hh
index f151aed..371ceb8 100644
--- a/src/mem/ruby/network/Network.hh
+++ b/src/mem/ruby/network/Network.hh
@@ -82,7 +82,6 @@
{ return dynamic_cast(_params); }
virtual ~Network();
-void init() override;
static uint32_t getNumberOfVirtualNetworks() { return
m_virtual_networks; }
int getNumNodes() const { return m_nodes; }
diff --git a/src/mem/ruby/network/Network.py
b/src/mem/ruby/network/Network.py
index 8999ff1..5febaad 100644
--- a/src/mem/ruby/network/Network.py
+++ b/src/mem/ruby/network/Network.py
@@ -25,6 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
+from m5.proxy import *
from m5.objects.ClockedObject import ClockedObject
from m5.objects.BasicLink import BasicLink
@@ -53,3 +54,8 @@
slave = DeprecatedParam(in_port, '`slave` is now called `in_port`')
out_port = VectorRequestPort("CPU output port")
master = DeprecatedParam(out_port, '`master` is now called `out_port`')
+
+data_msg_size = Param.Int(Parent.block_size_bytes,
+"Size of data messages. Defaults to the
parent "
+"RubySystem cache line size.")
+
--
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Gerrit-Change-Number: 31256
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Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Srikant Bharadwaj
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Bradford Beckmann
Gerrit-CC: Matthew Poremba
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix include dependency
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31258 )
Change subject: mem-ruby: fix include dependency
..
mem-ruby: fix include dependency
Removed include dependency between WriteMask and RubySystem.
Change-Id: I3e81267341e3875b1bb0fc3cb39f1a308e383dfd
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31258
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/common/WriteMask.cc
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
3 files changed, 9 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/common/WriteMask.cc
b/src/mem/ruby/common/WriteMask.cc
index 4585077..54ba8ff 100644
--- a/src/mem/ruby/common/WriteMask.cc
+++ b/src/mem/ruby/common/WriteMask.cc
@@ -32,6 +32,11 @@
#include "mem/ruby/system/RubySystem.hh"
+WriteMask::WriteMask()
+: mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
+ mAtomic(false)
+{}
+
void
WriteMask::print(std::ostream& out) const
{
diff --git a/src/mem/ruby/common/WriteMask.hh
b/src/mem/ruby/common/WriteMask.hh
index 6e3ea29..f1e5f37 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -46,18 +46,16 @@
#include
#include
+#include "base/amo.hh"
+#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
-#include "mem/ruby/system/RubySystem.hh"
class WriteMask
{
public:
typedef std::vector> AtomicOpVector;
-WriteMask()
- : mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
-mAtomic(false)
-{}
+WriteMask();
WriteMask(int size)
: mSize(size), mMask(size, false), mAtomic(false)
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index 155d134..a5a18ff 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -55,6 +55,7 @@
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/common/WriteMask.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
inline Cycles zero_time() { return Cycles(0); }
--
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Gerrit-Change-Id: I3e81267341e3875b1bb0fc3cb39f1a308e383dfd
Gerrit-Change-Number: 31258
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Tiago Mück
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Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MessageBuffer capacity check
Tiago Mück has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31254 ) Change subject: mem-ruby: MessageBuffer capacity check .. mem-ruby: MessageBuffer capacity check Trip assert if call enqueue on a full message buffer. Change-Id: I842183d8bf2c681787f1b6ac23c95825095ad05d Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31254 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Matthew Poremba --- M src/mem/ruby/network/MessageBuffer.cc 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Matthew Poremba: Looks good to me, approved kokoro: Regressions pass diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc index 3db8515..fb1d734 100644 --- a/src/mem/ruby/network/MessageBuffer.cc +++ b/src/mem/ruby/network/MessageBuffer.cc @@ -225,6 +225,9 @@ // Increment the number of messages statistic m_buf_msgs++; +assert((m_max_size == 0) || + ((m_prio_heap.size() + m_stall_map_size) <= m_max_size)); + DPRINTF(RubyQueue, "Enqueue arrival_time: %lld, Message: %s\n", arrival_time, *(message.get())); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31254 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I842183d8bf2c681787f1b6ac23c95825095ad05d Gerrit-Change-Number: 31254 Gerrit-PatchSet: 4 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Bradford Beckmann Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Allow same-cycle enqueue
ot;)
out_port = RequestPort("Request port to MessageBuffer receiver")
master = DeprecatedParam(out_port, '`master` is now called `out_port`')
--
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Gerrit-Change-Id: Ib194e7b4b4ee4b06da1baea17c0eb743f650dfdd
Gerrit-Change-Number: 31255
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: additional WriteMask methods
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31257 )
Change subject: mem-ruby: additional WriteMask methods
..
mem-ruby: additional WriteMask methods
Change-Id: Ib5d5f892075b38f46d1d802c043853f56e19ea12
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31257
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/protocol/RubySlicc_Exports.sm
2 files changed, 51 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/common/WriteMask.hh
b/src/mem/ruby/common/WriteMask.hh
index 6a0a041..6e3ea29 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2012-15 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -69,18 +81,18 @@
}
bool
-test(int offset)
+test(int offset) const
{
assert(offset < mSize);
return mMask[offset];
}
void
-setMask(int offset, int len)
+setMask(int offset, int len, bool val = true)
{
assert(mSize >= (offset + len));
for (int i = 0; i < len; i++) {
-mMask[offset + i] = true;
+mMask[offset + i] = val;
}
}
void
@@ -163,6 +175,33 @@
}
}
+void
+setInvertedMask(const WriteMask & writeMask)
+{
+assert(mSize == writeMask.mSize);
+for (int i = 0; i < mSize; i++) {
+mMask[i] = !writeMask.mMask.at(i);
+}
+}
+
+int
+firstBitSet(bool val, int offset = 0) const
+{
+for (int i = offset; i < mSize; ++i)
+if (mMask[i] == val)
+return i;
+return mSize;
+}
+
+int
+count(int offset = 0) const
+{
+int count = 0;
+for (int i = offset; i < mSize; ++i)
+count += mMask[i];
+return count;
+}
+
void print(std::ostream& out) const;
void
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index ea61350..1b67dc6 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -58,7 +58,16 @@
bool isFull();
bool isOverlap(WriteMask);
void orMask(WriteMask);
+ void setInvertedMask(WriteMask);
void fillMask();
+ void setMask(int,int);
+ bool getMask(int,int);
+ void setMask(int,int,bool);
+ int firstBitSet(bool);
+ int firstBitSet(bool,int);
+ int count();
+ int count(int);
+ bool test(int);
}
structure(DataBlock, external = "yes", desc="..."){
--
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Gerrit-Change-Number: 31257
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix rcl implementation triggers "bits" assert
Eduardo José Gómez Hernández has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52803 )
Change subject: arch-x86: Fix rcl implementation triggers "bits" assert
..
arch-x86: Fix rcl implementation triggers "bits" assert
With some values of rotations and datasizes, is it possible to call
"bits" with first being smaller than seccond. To prevent it, rcl,
similar to other rotations had an if to check if the value to rotate
is bigger than 1, however, rcl was checking for 'shiftAmt' instead
of 'realShiftAmt'.
This was not detected before because:
1 - The assert triggered in "bits" is from a recent commit
2 - The result is correct.
Change-Id: I669f4e064e12b035538e5dd0cc61eb4546603512
---
M src/arch/x86/isa/microops/regop.isa
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/isa/microops/regop.isa
b/src/arch/x86/isa/microops/regop.isa
index e5f9e3d..338ded9 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -990,7 +990,7 @@
CCFlagBits flags = cfofBits;
uint64_t top = PSrcReg1 << realShiftAmt;
uint64_t bottom = flags.cf << (realShiftAmt - 1);
-if(shiftAmt > 1) {
+if(realShiftAmt > 1) {
bottom |= bits(PSrcReg1, dataSize * 8 - 1,
dataSize * 8 - realShiftAmt + 1);
}
--
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Gerrit-Change-Id: I669f4e064e12b035538e5dd0cc61eb4546603512
Gerrit-Change-Number: 52803
Gerrit-PatchSet: 1
Gerrit-Owner: Eduardo José Gómez Hernández
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix rcl implementation triggers "bits" assert
Eduardo José Gómez Hernández has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/52803 )
Change subject: arch-x86: Fix rcl implementation triggers "bits" assert
..
arch-x86: Fix rcl implementation triggers "bits" assert
With some values of rotations and datasizes, is it possible to call
"bits" with first being smaller than seccond. To prevent it, rcl,
similar to other rotations had an if to check if the value to rotate
is bigger than 1, however, rcl was checking for 'shiftAmt' instead
of 'realShiftAmt'.
This was not detected before because:
1 - The assert triggered in "bits" is from a recent commit
2 - The result is correct.
Change-Id: I669f4e064e12b035538e5dd0cc61eb4546603512
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52803
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/x86/isa/microops/regop.isa
1 file changed, 25 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa/microops/regop.isa
b/src/arch/x86/isa/microops/regop.isa
index e5f9e3d..338ded9 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -990,7 +990,7 @@
CCFlagBits flags = cfofBits;
uint64_t top = PSrcReg1 << realShiftAmt;
uint64_t bottom = flags.cf << (realShiftAmt - 1);
-if(shiftAmt > 1) {
+if(realShiftAmt > 1) {
bottom |= bits(PSrcReg1, dataSize * 8 - 1,
dataSize * 8 - realShiftAmt + 1);
}
--
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Gerrit-Change-Id: I669f4e064e12b035538e5dd0cc61eb4546603512
Gerrit-Change-Number: 52803
Gerrit-PatchSet: 2
Gerrit-Owner: Eduardo José Gómez Hernández
Gerrit-Reviewer: Eduardo José Gómez Hernández
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-vega,arch-gcn3: Implement S_MEMTIME instruction
Alexandru Duțu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53603 )
Change subject: arch-vega,arch-gcn3: Implement S_MEMTIME instruction
..
arch-vega,arch-gcn3: Implement S_MEMTIME instruction
Change-Id: I3e286eb6ff8af4097ad03d4066be79f73d938cea
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/gpu-compute/gpu_static_inst.hh
M src/arch/amdgpu/gcn3/insts/instructions.cc
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/src/arch/amdgpu/gcn3/insts/instructions.cc
b/src/arch/amdgpu/gcn3/insts/instructions.cc
index bb15957..9bc0369 100644
--- a/src/arch/amdgpu/gcn3/insts/instructions.cc
+++ b/src/arch/amdgpu/gcn3/insts/instructions.cc
@@ -5318,6 +5318,11 @@
Inst_SMEM__S_MEMTIME::Inst_SMEM__S_MEMTIME(InFmt_SMEM *iFmt)
: Inst_SMEM(iFmt, "s_memtime")
{
+// Unlike other SMEM instructions, S_MEMTIME does not actually
issue a
+// request to memory. To simplify the implementation, we model it
as an
+// ALU instruction.
+unsetFlag(SMEM);
+setFlag(ALU);
} // Inst_SMEM__S_MEMTIME
Inst_SMEM__S_MEMTIME::~Inst_SMEM__S_MEMTIME()
@@ -5328,7 +5333,10 @@
void
Inst_SMEM__S_MEMTIME::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+ScalarOperandU64 sdst(gpuDynInst, instData.SDATA);
+sdst = (ScalarRegU64) curTick() /
+ gpuDynInst->computeUnit()->clockPeriod();
+sdst.write();
}
Inst_SMEM__S_MEMREALTIME::Inst_SMEM__S_MEMREALTIME(InFmt_SMEM *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 1e07f0b..4650aa8 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -5841,6 +5841,11 @@
Inst_SMEM__S_MEMTIME::Inst_SMEM__S_MEMTIME(InFmt_SMEM *iFmt)
: Inst_SMEM(iFmt, "s_memtime")
{
+// Unlike other SMEM instructions, S_MEMTIME does not actually
issue a
+// request to memory. To simplify the implementation, we model it
as an
+// ALU instruction.
+unsetFlag(SMEM);
+setFlag(ALU);
} // Inst_SMEM__S_MEMTIME
Inst_SMEM__S_MEMTIME::~Inst_SMEM__S_MEMTIME()
@@ -5852,7 +5857,10 @@
void
Inst_SMEM__S_MEMTIME::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+ScalarOperandU64 sdst(gpuDynInst, instData.SDATA);
+sdst = (ScalarRegU64) curTick() /
+ gpuDynInst->computeUnit()->clockPeriod();
+sdst.write();
} // execute
// --- Inst_SMEM__S_MEMREALTIME class methods ---
diff --git a/src/gpu-compute/gpu_static_inst.hh
b/src/gpu-compute/gpu_static_inst.hh
index 8de6c89..a15e912 100644
--- a/src/gpu-compute/gpu_static_inst.hh
+++ b/src/gpu-compute/gpu_static_inst.hh
@@ -262,6 +262,7 @@
executed_as = enums::SC_ARG;
}
}
+void unsetFlag(Flags flag) { _flags[flag] = false; }
const std::string& opcode() const { return _opcode; }
const std::vector& srcOperands() const { return srcOps; }
--
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Fix O3 lsq_unit index variables type
t write(LSQRequest *request, uint8_t *data, ssize_t store_idx);
/** Returns the index of the head load instruction. */
int getLoadHead() { return loadQueue.head(); }
--
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Fix O3 lsq_unit index variables type
ors. */
/** @{ */
bool valid() const { return _valid; }
-uint32_t& size() { return _size; }
-const uint32_t& size() const { return _size; }
+size_t& size() { return _size; }
+const size_t& size() const { return _size; }
const DynInstPtr& instruction() const { return _inst; }
/** @} */
};
@@ -211,7 +211,7 @@
public:
/** Constructs an LSQ unit. init() must be called prior to use. */
-LSQUnit(uint32_t lqEntries, uint32_t sqEntries);
+LSQUnit(size_t lqEntries, size_t sqEntries);
/** We cannot copy LSQUnit because it has stats for which copy
* contructor is deleted explicitly. However, STL vector requires
@@ -485,7 +485,7 @@
*/
InstSeqNum stallingStoreIsn;
/** The index of the above store. */
-int stallingLoadIdx;
+size_t stallingLoadIdx;
/** The packet that needs to be retried. */
PacketPtr retryPkt;
@@ -539,10 +539,10 @@
public:
/** Executes the load at the given index. */
-Fault read(LSQRequest *request, int load_idx);
+Fault read(LSQRequest *request, ssize_t load_idx);
/** Executes the store at the given index. */
-Fault write(LSQRequest *request, uint8_t *data, int store_idx);
+Fault write(LSQRequest *request, uint8_t *data, ssize_t store_idx);
/** Returns the index of the head load instruction. */
int getLoadHead() { return loadQueue.head(); }
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: This commit fix the default privilege to M-mode
钟乘永 has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58049 )
Change subject: arch-riscv: This commit fix the default privilege to M-mode
..
arch-riscv: This commit fix the default privilege to M-mode
As the spec(The RISC-V Instruction Set Manual Volume II: Privileged
Architecture,
chapter 3) says, "M-mode is used for low-level access to a hardware platform
and is the first mode entered at reset."
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1206
Change-Id: Ia4f33b2401a3d30211738d061848a15e5b12cf62
---
M src/arch/riscv/process.cc
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index cbd13b0..361633d 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -102,7 +102,7 @@
argsInit(PageBytes);
for (ContextID ctx: contextIds)
-system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_M);
}
void
@@ -113,7 +113,7 @@
argsInit(PageBytes);
for (ContextID ctx: contextIds) {
auto *tc = system->threads[ctx];
-tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+tc->setMiscRegNoEffect(MISCREG_PRV, PRV_M);
PCState pc = tc->pcState().as();
pc.rv32(true);
tc->pcState(pc);
--
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Gerrit-Change-Id: Ia4f33b2401a3d30211738d061848a15e5b12cf62
Gerrit-Change-Number: 58049
Gerrit-PatchSet: 1
Gerrit-Owner: 钟乘永
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: RISCV call/ret instructions aren't decoded correctly
IsIndirectControl, IsUncondControl, IsCall);
+default: Jump::jalr_0({{
+Rd = NPC;
+NPC = (imm + Rs1) & (~0x1);
+}}, IsIndirectControl, IsUncondControl);
+}
+}
+default: decode RD {
+0x1: Jump::jalr_call_1({{
+Rd = NPC;
+NPC = (imm + Rs1) & (~0x1);
+}}, IsIndirectControl, IsUncondControl, IsCall);
+default: Jump::jalr_1({{
+Rd = NPC;
+NPC = (imm + Rs1) & (~0x1);
+}}, IsIndirectControl, IsUncondControl);
+}
+}
}
-0x1b: JOp::jal({{
-Rd = NPC;
-NPC = PC + imm;
-}}, IsDirectControl, IsUncondControl, IsCall);
+0x1b: decode RD{
+0x1: JOp::jal_call({{
+Rd = NPC;
+NPC = PC + imm;
+}}, IsDirectControl, IsUncondControl, IsCall);
+default: JOp::jal({{
+Rd = NPC;
+NPC = PC + imm;
+}}, IsDirectControl, IsUncondControl);
+}
0x1c: decode FUNCT3 {
format SystemOp {
@@ -1423,7 +1472,6 @@
} else {
STATUS status =
xc->readMiscReg(MISCREG_STATUS);
xc->setMiscReg(MISCREG_PRV, status.mpp);
-xc->setMiscReg(MISCREG_NMIE, 1);
status.mie = status.mpie;
status.mpie = 1;
status.mpp = PRV_U;
--
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Gerrit-Change-Id: I9728757c9f3f81bd498a0ba04664a003dbded3bf
Gerrit-Change-Number: 58209
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Gerrit-Owner: 钟乘永
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: RISCV call/ret instructions aren't decoded correctly
@@ -420,7 +463,7 @@
{'code': code, 'imm_code': 'imm = sext<12>(IMM12);',
'regs': ','.join(regs)}, opt_flags)
header_output = JumpDeclare.subst(iop)
-decoder_output = ImmConstructor.subst(iop)
+decoder_output = JumpConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = JumpExecute.subst(iop)
}};
@@ -450,7 +493,7 @@
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = BranchDeclare.subst(iop)
-decoder_output = ImmConstructor.subst(iop)
+decoder_output = JumpConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BranchExecute.subst(iop)
}};
--
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Gerrit-Change-Id: I9728757c9f3f81bd498a0ba04664a003dbded3bf
Gerrit-Change-Number: 58209
Gerrit-PatchSet: 6
Gerrit-Owner: 钟乘永
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jin Cui
Gerrit-Reviewer: kokoro
Gerrit-Reviewer: 钟乘永
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: queued prefetcher bug fix
Burak Öçalan has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46759 )
Change subject: mem-cache: queued prefetcher bug fix
..
mem-cache: queued prefetcher bug fix
In queued prefetcher, addToQueue function doesn't behave
correctly where the element must be added to the end of queue.
I fixed this bug.
Change-Id: I1eec129f827b6465e7cef874c551d96acbf18d5b
Signed-off-by: Burak Öçalan
Reported-by: Burak Öçalan
Tested-by: Burak Öçalan
---
M src/mem/cache/prefetch/queued.cc
1 file changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/mem/cache/prefetch/queued.cc
b/src/mem/cache/prefetch/queued.cc
index 2a74a17..221542a 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -475,6 +475,13 @@
if (queue.size() == 0) {
queue.emplace_back(dpp);
} else {
+/* Handle the case where the element should be added to end of
queue
+ separately */
+if (dpp <= queue.back()) {
+queue.insert(queue.end(), dpp);
+return;
+}
+
iterator it = queue.end();
do {
--it;
--
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Gerrit-Change-Id: I1eec129f827b6465e7cef874c551d96acbf18d5b
Gerrit-Change-Number: 46759
Gerrit-PatchSet: 1
Gerrit-Owner: Burak Öçalan
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: queued prefetcher bug fix
Burak Öçalan has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/46759 )
Change subject: mem-cache: queued prefetcher bug fix
..
mem-cache: queued prefetcher bug fix
In queued prefetcher, addToQueue function doesn't behave
correctly where the element must be added to the end of queue.
I fixed this bug.
Change-Id: I1eec129f827b6465e7cef874c551d96acbf18d5b
Signed-off-by: Burak Öçalan
Reported-by: Burak Öçalan
Tested-by: Burak Öçalan
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46759
Reviewed-by: Daniel Carvalho
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/cache/prefetch/queued.cc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/queued.cc
b/src/mem/cache/prefetch/queued.cc
index 2a74a17..db3ba2f 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -472,7 +472,7 @@
queue.erase(it);
}
-if (queue.size() == 0) {
+if ((queue.size() == 0) || (dpp <= queue.back())) {
queue.emplace_back(dpp);
} else {
iterator it = queue.end();
--
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Gerrit-Change-Id: I1eec129f827b6465e7cef874c551d96acbf18d5b
Gerrit-Change-Number: 46759
Gerrit-PatchSet: 6
Gerrit-Owner: Burak Öçalan
Gerrit-Reviewer: Burak Öçalan
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fixed M5InternalError when decoding certain bytes
Eduardo José Gómez Hernández has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49990 )
Change subject: arch-x86: Fixed M5InternalError when decoding certain bytes
..
arch-x86: Fixed M5InternalError when decoding certain bytes
0F38 is the two bytes prefixes to decode a three-byte opcode.
To prevent error, the two_bytes_opcode decoder will complain
if it tries to decode 38 as the opcode, because it is a prefix.
The decoder, will treat 38 as a prefix, preventing it to
end in the two_byte_opcode decoder.
However, using the VEX prefix is possible to reach this
forbidden state.
The set of bytes C4 01 01 38 00 will trigger the mentioned
M5InternalError.
The previous instruction is not valid, but it could be
decoded from an speculative path. In its place, a UD2
instructtion should be emitted.
Change-Id: I6b7c4b3593dd8e6e8ac99aaf306b8feeb7784b56
---
M src/arch/x86/decoder.cc
1 file changed, 10 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/decoder.cc b/src/arch/x86/decoder.cc
index 015a504..3020b1d 100644
--- a/src/arch/x86/decoder.cc
+++ b/src/arch/x86/decoder.cc
@@ -362,6 +362,16 @@
switch (emi.opcode.type) {
case TwoByteOpcode:
+ // Decoding garbage could lead in invalid instructions
+// that will never commit. This prevent certain 3 VEX opcodes
+// from reaching the decoder 'panic' of decoding 3 opcode
+// instructions using the 2 opcode decoder.
+if (emi.opcode.op == 0x38 || emi.opcode.op == 0x3A) {
+DPRINTF(Decoder, "Found VEX opcode redirecting to " \
+"TwoByteOpcode a reserved opcode for ThreeByteOpcode. "
+"Now, it will be converted into UD2.\n");
+emi.opcode.op = 0x39;
+}
return processOpcode(ImmediateTypeTwoByte, UsesModRMTwoByte);
case ThreeByte0F38Opcode:
return processOpcode(ImmediateTypeThreeByte0F38,
--
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Gerrit-Owner: Eduardo José Gómez Hernández
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fixed M5InternalError when decoding certain bytes
Eduardo José Gómez Hernández has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49990 )
Change subject: arch-x86: Fixed M5InternalError when decoding certain bytes
..
arch-x86: Fixed M5InternalError when decoding certain bytes
0F 38 is the two bytes prefixes to decode a three-byte opcode.
To prevent errors, the two_bytes_opcode decoder will complain
if it tries to decode 38 as the opcode, because it is a prefix.
The decoder, will treat 38 as a prefix, preventing it to
end in the two_byte_opcode decoder.
However, using the VEX prefix is possible to reach this
forbidden state.
The set of bytes C4 01 01 38 00 will trigger the mentioned
M5InternalError.
The previous instruction is not valid, but it could be
decoded from an speculative path. In its place, a UD2
instructtion should be emitted if the VEX prefix is
present.
Change-Id: I6b7c4b3593dd8e6e8ac99aaf306b8feeb7784b56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49990
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/bitfields.isa
2 files changed, 42 insertions(+), 8 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa/bitfields.isa b/src/arch/x86/isa/bitfields.isa
index 9522a8d..0404afc 100644
--- a/src/arch/x86/isa/bitfields.isa
+++ b/src/arch/x86/isa/bitfields.isa
@@ -86,5 +86,6 @@
def bitfield MODE_MODE mode.mode;
def bitfield MODE_SUBMODE mode.submode;
+def bitfield VEX_PRESENT vex.present;
def bitfield VEX_V vex.v;
def bitfield VEX_L vex.l;
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 48f46d4..549db47 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -354,14 +354,17 @@
0x6: Inst::UD2();
0x7: getsec();
}
-0x07: decode OPCODE_OP_BOTTOM3 {
-0x0: M5InternalError::error(
-{{"Three byte opcode shouldn't be handled by "
- "two_byte_opcodes.isa!"}});
-0x2: M5InternalError::error(
-{{"Three byte opcode shouldn't be handled by "
- "two_byte_opcodes.isa!"}});
-default: UD2();
+0x07: decode VEX_PRESENT {
+0x0: decode OPCODE_OP_BOTTOM3 {
+0x0: M5InternalError::error(
+{{"Three byte opcode shouldn't be handled by "
+ "two_byte_opcodes.isa!"}});
+0x2: M5InternalError::error(
+{{"Three byte opcode shouldn't be handled by "
+ "two_byte_opcodes.isa!"}});
+default: UD2();
+}
+0x1: UD2();
}
format Inst {
0x08: decode OPCODE_OP_BOTTOM3 {
--
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Gerrit-Change-Id: I6b7c4b3593dd8e6e8ac99aaf306b8feeb7784b56
Gerrit-Change-Number: 49990
Gerrit-PatchSet: 3
Gerrit-Owner: Eduardo José Gómez Hernández
Gerrit-Reviewer: Eduardo José Gómez Hernández
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: move AddrRange propagation to RubyPort
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31268 )
Change subject: mem-ruby: move AddrRange propagation to RubyPort
..
mem-ruby: move AddrRange propagation to RubyPort
Doing the master address range notification from the RubyPort.
This allows us the DMASequencer to be replaced by Sequencer in future
protocols.
Change-Id: I95edb54b39a8adf0cac5caf2b58e4a2efb573f56
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31268
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/system/DMASequencer.cc
M src/mem/ruby/system/RubyPort.cc
2 files changed, 2 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/system/DMASequencer.cc
b/src/mem/ruby/system/DMASequencer.cc
index 938044a..4c61dd2 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -56,9 +56,6 @@
{
RubyPort::init();
m_data_block_mask = mask(RubySystem::getBlockSizeBits());
-
-for (const auto &response_port : response_ports)
-response_port->sendRangeChange();
}
RequestStatus
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index 116f04f..2469710 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -86,6 +86,8 @@
{
assert(m_controller != NULL);
m_mandatory_q_ptr = m_controller->getMandatoryQueue();
+for (const auto &response_port : response_ports)
+response_port->sendRangeChange();
}
Port &
--
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Gerrit-Change-Number: 31268
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: sequencer callback for unique writes
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31269 )
Change subject: mem-ruby: sequencer callback for unique writes
..
mem-ruby: sequencer callback for unique writes
A controller may complete a write without obtaining a full copy of
the line. This patch adds a specific callback for this purpose that
prevents reads to be coalesced with a write on a potentially incomplete
line.
Change-Id: I3775f81699f38e406fee28f92c9c8e06deb3d528
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31269
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Bradford Beckmann
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
3 files changed, 21 insertions(+), 2 deletions(-)
Approvals:
Bradford Beckmann: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index b4854d4..a7b9d34 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -129,6 +129,7 @@
void writeCallback(Addr, DataBlock, bool, MachineType);
void writeCallback(Addr, DataBlock, bool, MachineType,
Cycles, Cycles, Cycles);
+ void writeUniqueCallback(Addr, DataBlock);
// ll/sc support
void writeCallbackScFail(Addr, DataBlock);
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 0614c11..6b50636 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -352,7 +352,8 @@
const bool externalHit, const MachineType mach,
const Cycles initialRequestTime,
const Cycles forwardRequestTime,
- const Cycles firstResponseTime)
+ const Cycles firstResponseTime,
+ const bool noCoales)
{
//
// Free the whole list as we assume we have had the exclusive access
@@ -370,6 +371,15 @@
int aliased_loads = 0;
while (!seq_req_list.empty()) {
SequencerRequest &seq_req = seq_req_list.front();
+
+if (noCoales && !ruby_request) {
+// Do not process follow-up requests
+// (e.g. if full line no present)
+// Reissue to the cache hierarchy
+issueRequest(seq_req.pkt, seq_req.m_second_type);
+break;
+}
+
if (ruby_request) {
assert(seq_req.m_type != RubyRequestType_LD);
assert(seq_req.m_type != RubyRequestType_Load_Linked);
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 4a5e281..e1a3c2d 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -103,7 +103,15 @@
const MachineType mach = MachineType_NUM,
const Cycles initialRequestTime = Cycles(0),
const Cycles forwardRequestTime = Cycles(0),
- const Cycles firstResponseTime = Cycles(0));
+ const Cycles firstResponseTime = Cycles(0),
+ const bool noCoales = false);
+
+// Write callback that prevents coalescing
+void writeUniqueCallback(Addr address, DataBlock& data)
+{
+writeCallback(address, data, true, MachineType_NUM, Cycles(0),
+ Cycles(0), Cycles(0), true);
+}
void readCallback(Addr address,
DataBlock& data,
--
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Gerrit-Change-Id: I3775f81699f38e406fee28f92c9c8e06deb3d528
Gerrit-Change-Number: 31269
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Alexandru Duțu
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: change MessageBuffer randomization param
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31419 )
Change subject: mem-ruby: change MessageBuffer randomization param
..
mem-ruby: change MessageBuffer randomization param
There are cases in which we need to prevent randomization for a
specific buffer when enabled at the RubySystem level (e.g. a internal
trigger queue that requires zero latency enqueue, while other buffers
can be randomized).
This changes the randomization parameter to support enabling and
disabling randomization regardless of the RubySystem setting.
Change-Id: If7520153cc5864897fa42e8911a6f8acbcf01db5
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31419
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/network/MessageBuffer.py
3 files changed, 15 insertions(+), 8 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/MessageBuffer.cc
b/src/mem/ruby/network/MessageBuffer.cc
index 8843694..00e8fea 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -176,9 +176,11 @@
assert((delta > 0) || m_allow_zero_latency);
Tick arrival_time = 0;
-// random delays are inserted if either RubySystem level randomization
flag
-// is turned on, or the buffer level randomization is set
-if (!RubySystem::getRandomization() && !m_randomization) {
+// random delays are inserted if the RubySystem level randomization
flag
+// is turned on and this buffer allows it
+if ((m_randomization == MessageRandomization::disabled) ||
+((m_randomization == MessageRandomization::ruby_system) &&
+ !RubySystem::getRandomization())) {
// No randomization
arrival_time = current_time + delta;
} else {
diff --git a/src/mem/ruby/network/MessageBuffer.hh
b/src/mem/ruby/network/MessageBuffer.hh
index 3887340..fc69d34 100644
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -248,7 +248,7 @@
uint64_t m_msg_counter;
int m_priority_rank;
const bool m_strict_fifo;
-const bool m_randomization;
+const MessageRandomization m_randomization;
const bool m_allow_zero_latency;
int m_input_link_id;
diff --git a/src/mem/ruby/network/MessageBuffer.py
b/src/mem/ruby/network/MessageBuffer.py
index 297835f..807ffb4 100644
--- a/src/mem/ruby/network/MessageBuffer.py
+++ b/src/mem/ruby/network/MessageBuffer.py
@@ -40,6 +40,13 @@
from m5.proxy import *
from m5.SimObject import SimObject
+# A MessageBuffer inserts random delays to enqueued messages when the
+# randomization param is set to 'enabled' or when globally enabled for the
+# RubySystem and the param is set to 'ruby_system' (default). 'disabled'
+# completely prevents randomization.
+class MessageRandomization(ScopedEnum):
+vals = ['disabled', 'enabled', 'ruby_system']
+
class MessageBuffer(SimObject):
type = 'MessageBuffer'
cxx_class = 'MessageBuffer'
@@ -47,10 +54,8 @@
ordered = Param.Bool(False, "Whether the buffer is ordered")
buffer_size = Param.Unsigned(0, "Maximum number of entries to buffer \
(0 allows infinite entries)")
-randomization = Param.Bool(False, "Insert random delays on message \
- enqueue times (enforced to have \
- random delays if RubySystem \
- randomization flag is True)")
+randomization = Param.MessageRandomization('ruby_system',
+ "Randomization parameter")
allow_zero_latency = Param.Bool(False, "Allows messages to be enqueued
\
with zero latency. This is
useful \
for internall trigger queues
and \
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If7520153cc5864897fa42e8911a6f8acbcf01db5
Gerrit-Change-Number: 31419
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: expose transition info to actions
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31420 )
Change subject: mem-ruby: expose transition info to actions
..
mem-ruby: expose transition info to actions
SLICC compiler generates the curTransitionEvent and
curTransitionNextState functions, which allows actions to check which
event triggered the current transition and what's the next state.
Change-Id: I79c8c4f2839633b7fb3b23cbbdbb32f25db90eab
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31420
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/slicc/symbols/StateMachine.py
1 file changed, 12 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 1399d00..c019e1b 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -380,6 +380,12 @@
code('''
Addr addr);
+${ident}_Event m_curTransitionEvent;
+${ident}_State m_curTransitionNextState;
+
+${ident}_Event curTransitionEvent() { return m_curTransitionEvent; }
+${ident}_State curTransitionNextState() { return m_curTransitionNextState;
}
+
int m_counters[${ident}_State_NUM][${ident}_Event_NUM];
int m_event_counters[${ident}_Event_NUM];
bool m_possible[${ident}_State_NUM][${ident}_Event_NUM];
@@ -1407,6 +1413,8 @@
code('''
Addr addr)
{
+m_curTransitionEvent = event;
+m_curTransitionNextState = next_state;
switch(HASH_FUN(state, event)) {
''')
@@ -1427,10 +1435,12 @@
# is determined before any actions of the transition
# execute, and therefore the next state calculation
cannot
# depend on any of the transitionactions.
-case('next_state = getNextState(addr);')
+case('next_state = getNextState(addr); '
+ 'm_curTransitionNextState = next_state;')
else:
ns_ident = trans.nextState.ident
-case('next_state = ${ident}_State_${ns_ident};')
+case('next_state = ${ident}_State_${ns_ident}; '
+ 'm_curTransitionNextState = next_state;')
actions = trans.actions
request_types = trans.request_types
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I79c8c4f2839633b7fb3b23cbbdbb32f25db90eab
Gerrit-Change-Number: 31420
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Bradford Beckmann
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: missing method in NetDest interface
Tiago Mück has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31262 ) Change subject: mem-ruby: missing method in NetDest interface .. mem-ruby: missing method in NetDest interface Change-Id: Ibf651c37c50174186daebebc06aa115e6bc2ed33 Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31262 Reviewed-by: Matthew Poremba Maintainer: Bradford Beckmann Tested-by: kokoro --- M src/mem/ruby/protocol/RubySlicc_Types.sm 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Matthew Poremba: Looks good to me, approved Bradford Beckmann: Looks good to me, approved kokoro: Regressions pass diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm b/src/mem/ruby/protocol/RubySlicc_Types.sm index 9c64732..b4854d4 100644 --- a/src/mem/ruby/protocol/RubySlicc_Types.sm +++ b/src/mem/ruby/protocol/RubySlicc_Types.sm @@ -111,6 +111,7 @@ bool isEmpty(); bool intersectionIsEmpty(Set); bool intersectionIsEmpty(NetDest); + MachineID smallestElement(); MachineID smallestElement(MachineType); NetDest OR(NetDest); NetDest AND(NetDest); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31262 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ibf651c37c50174186daebebc06aa115e6bc2ed33 Gerrit-Change-Number: 31262 Gerrit-PatchSet: 5 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Bradford Beckmann Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: int to Cycle converter
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31266 )
Change subject: mem-ruby: int to Cycle converter
..
mem-ruby: int to Cycle converter
Change-Id: I493b16a0bdd01a4cef4891e273a376ebe9509fe8
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31266
Reviewed-by: Jason Lowe-Power
Reviewed-by: Matthew Poremba
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Util.sm
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
2 files changed, 3 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Matthew Poremba: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Util.sm
b/src/mem/ruby/protocol/RubySlicc_Util.sm
index f509d09..b8b005a 100644
--- a/src/mem/ruby/protocol/RubySlicc_Util.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Util.sm
@@ -32,6 +32,7 @@
void error(std::string msg);
void assert(bool condition);
Cycles zero_time();
+Cycles intToCycles(int c);
NodeID intToID(int nodenum);
int IDToInt(NodeID id);
int addressToInt(Addr addr);
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index a5a18ff..b51b30c 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -59,6 +59,8 @@
inline Cycles zero_time() { return Cycles(0); }
+inline Cycles intToCycles(int c) { return Cycles(c); }
+
inline NodeID
intToID(int nodenum)
{
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I493b16a0bdd01a4cef4891e273a376ebe9509fe8
Gerrit-Change-Number: 31266
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: added function to check addr range
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31263 )
Change subject: mem-ruby: added function to check addr range
..
mem-ruby: added function to check addr range
respondsTo checks if a controller address ranges includes a given
address.
Change-Id: I9a320011d93e7fd8df1ad3bda75c85d314261a99
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31263
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Bradford Beckmann
---
M src/mem/ruby/slicc_interface/AbstractController.hh
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
Bradford Beckmann: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 98cb0a7..cbe92c0 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -153,6 +153,13 @@
Stats::Histogram& getDelayVCHist(uint32_t index)
{ return *(m_delayVCHistogram[index]); }
+bool respondsTo(Addr addr)
+{
+for (auto &range: addrRanges)
+if (range.contains(addr)) return true;
+return false;
+}
+
/**
* Map an address to the correct MachineID
*
--
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Gerrit-Change-Id: I9a320011d93e7fd8df1ad3bda75c85d314261a99
Gerrit-Change-Number: 31263
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Sequencer can be used without cache
/ruby/MOESI_CMP_token.py
@@ -117,7 +117,7 @@
clk_domain=clk_domain,
ruby_system=ruby_system)
-cpu_seq = RubySequencer(version=i, icache=l1i_cache,
+cpu_seq = RubySequencer(version=i,
dcache=l1d_cache, clk_domain=clk_domain,
ruby_system=ruby_system)
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index c83bb72..1e00f0f 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -109,7 +109,7 @@
clk_domain=clk_domain,
ruby_system=ruby_system)
-cpu_seq = RubySequencer(version=i, icache=l1i_cache,
+cpu_seq = RubySequencer(version=i,
dcache=l1d_cache,clk_domain=clk_domain,
ruby_system=ruby_system)
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index dbc85c4..0614c11 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -73,7 +73,6 @@
{
m_outstanding_count = 0;
-m_instCache_ptr = p->icache;
m_dataCache_ptr = p->dcache;
m_max_outstanding_requests = p->max_outstanding_requests;
m_deadlock_threshold = p->deadlock_threshold;
@@ -81,8 +80,6 @@
m_coreId = p->coreid; // for tracking the two CorePair sequencers
assert(m_max_outstanding_requests > 0);
assert(m_deadlock_threshold > 0);
-assert(m_instCache_ptr != NULL);
-assert(m_dataCache_ptr != NULL);
m_runningGarnetStandalone = p->garnet_standalone;
}
@@ -94,6 +91,8 @@
void
Sequencer::llscLoadLinked(const Addr claddr)
{
+fatal_if(m_dataCache_ptr == NULL,
+"%s must have a dcache object to support LLSC requests.", name());
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (line) {
line->setLocked(m_version);
@@ -105,6 +104,9 @@
void
Sequencer::llscClearMonitor(const Addr claddr)
{
+// clear monitor is called for all stores and evictions
+if (m_dataCache_ptr == NULL)
+return;
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (line && line->isLocked(m_version)) {
line->clearLocked();
@@ -116,6 +118,8 @@
bool
Sequencer::llscStoreConditional(const Addr claddr)
{
+fatal_if(m_dataCache_ptr == NULL,
+"%s must have a dcache object to support LLSC requests.", name());
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (!line)
return false;
@@ -137,6 +141,7 @@
bool
Sequencer::llscCheckMonitor(const Addr address)
{
+assert(m_dataCache_ptr != NULL);
const Addr claddr = makeLineAddress(address);
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (!line)
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 92fdab6..4a5e281 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -212,7 +212,6 @@
int m_max_outstanding_requests;
CacheMemory* m_dataCache_ptr;
-CacheMemory* m_instCache_ptr;
// The cache access latency for top-level caches (L0/L1). These are
// currently assessed at the beginning of each memory access through
the
diff --git a/src/mem/ruby/system/Sequencer.py
b/src/mem/ruby/system/Sequencer.py
index 0a28d36..0acd87a 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2009 Advanced Micro Devices, Inc.
# Copyright (c) 2020 ARM Limited
# All rights reserved.
@@ -76,7 +88,6 @@
cxx_class = 'Sequencer'
cxx_header = "mem/ruby/system/Sequencer.hh"
- icache = Param.RubyCache("")
dcache = Param.RubyCache("")
max_outstanding_requests = Param.Int(16,
--
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Gerrit-Change-Id: I04bd2711f8d0a7dfc952cff8e0020d2d1881cae1
Gerrit-Change-Number: 31267
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerri
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: support for template types in structs
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31264 )
Change subject: mem-ruby: support for template types in structs
..
mem-ruby: support for template types in structs
Templated types can now be used within structures defined in SLICC.
Usage is similar to the TBETable: the templated type must have all
possible methods in it's SLICC definition. Eg.:
structure(Map, desc="Template map definition") {
MachineID lookup(Addr);
MachineID lookup(int);
}
structure(SomeType, desc="Some other struct definition") {
MachineID addrMap, template="";
MachineID intMap, template="";
}
Change-Id: I02a621cea5e4a89302762334651c6534c6574e9d
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31264
Reviewed-by: Matthew Poremba
Reviewed-by: Bradford Beckmann
Maintainer: Bradford Beckmann
Tested-by: kokoro
---
M src/mem/slicc/symbols/Type.py
1 file changed, 23 insertions(+), 7 deletions(-)
Approvals:
Bradford Beckmann: Looks good to me, approved; Looks good to me, approved
Matthew Poremba: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index fa5e79a..ee319cb 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
@@ -37,6 +49,9 @@
super(DataMember, self).__init__(symtab, ident, location, type,
code, pairs, machine)
self.init_code = init_code
+self.real_c_type = self.type.c_ident
+if "template" in pairs:
+self.real_c_type += pairs["template"]
class Enumeration(PairContainer):
def __init__(self, ident, pairs):
@@ -235,8 +250,9 @@
code('m_$ident = ${{dm["default"]}}; // default for
this field')
elif "default" in dm.type:
# Look for the type default
-tid = dm.type.c_ident
-code('m_$ident = ${{dm.type["default"]}}; // default
value of $tid')
+tid = dm.real_c_type
+code('m_$ident = ${{dm.type["default"]}};')
+code(' // default value of $tid')
else:
code('// m_$ident has no default')
code.dedent()
@@ -268,7 +284,7 @@
# Full init constructor
if not self.isGlobal:
-params = [ 'const %s& local_%s' % (dm.type.c_ident, dm.ident) \
+params = [ 'const %s& local_%s' % (dm.real_c_type, dm.ident) \
for dm in self.data_members.values() ]
params = ', '.join(params)
@@ -318,7 +334,7 @@
/** \\brief Const accessor method for ${{dm.ident}} field.
* \\return ${{dm.ident}} field
*/
-const ${{dm.type.c_ident}}&
+const ${{dm.real_c_type}}&
get${{dm.ident}}() const
{
return m_${{dm.ident}};
@@ -332,7 +348,7 @@
/** \\brief Non-const accessor method for ${{dm.ident}} field.
* \\return ${{dm.ident}} field
*/
-${{dm.type.c_ident}}&
+${{dm.real_c_type}}&
get${{dm.ident}}()
{
return m_${{dm.ident}};
@@ -345,7 +361,7 @@
code('''
/** \\brief Mutator method for ${{dm.ident}} field */
void
-set${{dm.ident}}(const ${{dm.type.c_ident}}& local_${{dm.ident}})
+set${{dm.ident}}(const ${{dm.real_c_type}}& local_${{dm.ident}})
{
m_${{dm.ident}} = local_${{dm.ident}};
}
@@ -375,7 +391,7 @@
if "desc" in dm:
code('/** ${{dm["desc"]}} */')
-code('$const${{dm.type.c_ident}} m_${{dm.ident}}$init;')
+code('$const${{dm.real_c_type}} m_${{dm.ident}}$init;')
# Prototypes for methods defined for the Type
for item in self.methods:
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: added %(mod) operator to SLICC
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31260 )
Change subject: mem-ruby: added %(mod) operator to SLICC
..
mem-ruby: added %(mod) operator to SLICC
Change-Id: I9d1a10824ced3723d13e2843ad739ced72e476ce
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31260
Reviewed-by: Jason Lowe-Power
Reviewed-by: John Alsop
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/slicc/ast/OperatorExprAST.py
M src/mem/slicc/parser.py
2 files changed, 5 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
John Alsop: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/mem/slicc/ast/OperatorExprAST.py
b/src/mem/slicc/ast/OperatorExprAST.py
index 7752e9c..cab1369 100644
--- a/src/mem/slicc/ast/OperatorExprAST.py
+++ b/src/mem/slicc/ast/OperatorExprAST.py
@@ -64,7 +64,7 @@
elif self.op in ("<<", ">>"):
expected_types = [("int", "int", "int"),
("Cycles", "int", "Cycles")]
-elif self.op in ("+", "-", "*", "/"):
+elif self.op in ("+", "-", "*", "/", "%"):
expected_types = [("int", "int", "int"),
("Cycles", "Cycles", "Cycles"),
("Tick", "Tick", "Tick"),
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 643eec6..13dde9a 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -128,7 +128,7 @@
tokens = [ 'EQ', 'NE', 'LT', 'GT', 'LE', 'GE',
'LEFTSHIFT', 'RIGHTSHIFT',
'NOT', 'AND', 'OR',
- 'PLUS', 'DASH', 'STAR', 'SLASH',
+ 'PLUS', 'DASH', 'STAR', 'SLASH', 'MOD',
'INCR', 'DECR',
'DOUBLE_COLON', 'SEMI',
'ASSIGN', 'DOT',
@@ -150,6 +150,7 @@
t_DASH = r'-'
t_STAR = r'\*'
t_SLASH = r'/'
+t_MOD = r'%'
t_DOUBLE_COLON = r'::'
t_SEMI = r';'
t_ASSIGN = r':='
@@ -165,7 +166,7 @@
('left', 'LT', 'GT', 'LE', 'GE'),
('left', 'RIGHTSHIFT', 'LEFTSHIFT'),
('left', 'PLUS', 'DASH'),
- ('left', 'STAR', 'SLASH'),
+('left', 'STAR', 'SLASH', 'MOD'),
('right', 'NOT', 'UMINUS'),
)
@@ -695,6 +696,7 @@
def p_expr__binary_op(self, p):
"""expr : expr STAR expr
| expr SLASH expr
+| expr MOD expr
| expr PLUS expr
| expr DASH expr
| expr LTexpr
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I9d1a10824ced3723d13e2843ad739ced72e476ce
Gerrit-Change-Number: 31260
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: detailed transaction latency profiling
s/StateMachine.py
@@ -854,6 +854,36 @@
}
}
}
+for (${ident}_Event event = ${ident}_Event_FIRST;
+ event < ${ident}_Event_NUM; ++event) {
+Stats::Histogram* t = new Stats::Histogram;
+m_outTransLatHist.push_back(t);
+t->init(5);
+t->name(name() + ".outTransLatHist." +
+${ident}_Event_to_string(event));
+t->flags(Stats::pdf | Stats::total |
+ Stats::oneline | Stats::nozero);
+}
+for (${ident}_Event event = ${ident}_Event_FIRST;
+ event < ${ident}_Event_NUM; ++event) {
+m_inTransLatHist.emplace_back();
+for (${ident}_State initial_state = ${ident}_State_FIRST;
+ initial_state < ${ident}_State_NUM; ++initial_state) {
+m_inTransLatHist.back().emplace_back();
+for (${ident}_State final_state = ${ident}_State_FIRST;
+ final_state < ${ident}_State_NUM; ++final_state) {
+Stats::Histogram* t = new Stats::Histogram;
+m_inTransLatHist.back().back().push_back(t);
+t->init(5);
+t->name(name() + ".inTransLatHist." +
+${ident}_Event_to_string(event) + "." +
+${ident}_State_to_string(initial_state) + "." +
+${ident}_State_to_string(final_state));
+t->flags(Stats::pdf | Stats::total |
+ Stats::oneline | Stats::nozero);
+}
+}
+}
}
void
--
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Gerrit-Change-Id: Ib528641b9676c68907b5989b6a09bfe91373f9c9
Gerrit-Change-Number: 31421
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add addressOffset util
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31270 )
Change subject: mem-ruby: add addressOffset util
..
mem-ruby: add addressOffset util
Returns the offset of an address with respect to a base address.
Looks unnecessary, but SLICC doesn't support casting and the '-'
operator for Addr types, so the alternative to this would be to add
more some helpers like 'addrToUint64' and 'uint64ToInt'.
Change-Id: I90480cec4c8b2e6bb9706f8b94ed33abe3c93e78
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31270
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Util.sm
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
2 files changed, 11 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Util.sm
b/src/mem/ruby/protocol/RubySlicc_Util.sm
index b8b005a..70648ec 100644
--- a/src/mem/ruby/protocol/RubySlicc_Util.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Util.sm
@@ -37,6 +37,7 @@
int IDToInt(NodeID id);
int addressToInt(Addr addr);
Addr intToAddress(int addr);
+int addressOffset(Addr addr, Addr base);
int max_tokens();
Addr makeLineAddress(Addr addr);
int getOffset(Addr addr);
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index b51b30c..b568425 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -169,6 +169,16 @@
}
}
+inline int
+addressOffset(Addr addr, Addr base)
+{
+assert(addr >= base);
+Addr offset = addr - base;
+// sanity checks if fits in an int
+assert(offset < INT_MAX);
+return offset;
+}
+
/**
* This function accepts an address, a data block and a packet. If the
address
* range for the data block contains the address which the packet needs to
--
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Gerrit-Change-Number: 31270
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: more specialized address to node mapping
dr);
+return entry.begin()->second;
+} else {
+auto j = entry.find(mtype);
+fatal_if(j == entry.end(),
+ "%s: couldn't find mapping for address %x\n", name(), addr);
+return j->second;
+}
+}
+
+
bool
AbstractController::MemoryPort::recvTimingResp(PacketPtr pkt)
{
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 28103f9..2f33556 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017,2019 ARM Limited
+ * Copyright (c) 2017,2019,2020 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -44,8 +44,10 @@
#include
#include
#include
+#include
#include "base/addr_range.hh"
+#include "base/addr_range_map.hh"
#include "base/callback.hh"
#include "mem/packet.hh"
#include "mem/qport.hh"
@@ -175,6 +177,22 @@
*/
MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
+/**
+ * Maps an address to the correct dowstream MachineID (i.e. the
component
+ * in the next level of the cache hierarchy towards memory)
+ *
+ * This function uses the local list of possible destinations instead
of
+ * querying the network.
+ *
+ * @param the destination address
+ * @param the type of the destination (optional)
+ * @return the MachineID of the destination
+ */
+MachineID mapAddressToDownstreamMachine(Addr addr,
+MachineType mtype = MachineType_NUM)
const;
+
+const NetDest& allDownstreamDest() const { return
downstreamDestinations; }
+
protected:
//! Profiles original cache requests including PUTs
void profileRequest(const std::string &request);
@@ -338,6 +356,13 @@
private:
/** The address range to which the controller responds on the CPU
side. */
const AddrRangeList addrRanges;
+
+typedef std::unordered_map AddrMapEntry;
+
+AddrRangeMap downstreamAddrMap;
+
+NetDest downstreamDestinations;
+
};
#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
diff --git a/src/mem/ruby/slicc_interface/Controller.py
b/src/mem/ruby/slicc_interface/Controller.py
index 1f9c0db..ee6ca60 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017,2019 ARM Limited
+# Copyright (c) 2017,2019,2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -71,3 +71,8 @@
"memory output to the main memory is now called `memory_out_port`")
system = Param.System(Parent.any, "system object parameter")
+
+# These can be used by a protocol to enable reuse of the same machine
+# types to model different levels of the cache hierarchy
+downstream_destinations = VectorParam.RubyController([],
+"Possible destinations for requests sent towards
memory")
--
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Gerrit-Change-Number: 31415
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Bradford Beckmann
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Expose MessageBuffer methods
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31271 )
Change subject: mem-ruby: Expose MessageBuffer methods
..
mem-ruby: Expose MessageBuffer methods
SLICC interface for checking the capacity of MessageBuffers
Change-Id: I28e2d22a405d33fcbe6a183dffc31bd936fa26c4
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31271
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
1 file changed, 9 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index a7b9d34..af7c017 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -48,7 +48,15 @@
// undefined declaration error.
//
-external_type(MessageBuffer, buffer="yes", inport="yes", outport="yes");
+structure(MessageBuffer, buffer="yes", inport="yes", outport="yes",
+ external = "yes", primitive="yes") {
+ // NOTE: it's recommended to use SLICC's built in resource stall
management.
+ // These functions are mostly for including resource utilization info
+ // in debug traces dumped by the protocol.
+ bool areNSlotsAvailable(int n, Tick curTime);
+ int getSize(Tick curTime);
+}
+
external_type(Scalar, primitive="yes");
structure(OutPort, external = "yes", primitive="yes") {
--
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Gerrit-Change-Number: 31271
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: allow qualifiers in SLICC functions
re implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2009 The Hewlett-Packard Development Company # Copyright (c) 2017 Google Inc. # All rights reserved. @@ -132,7 +144,8 @@ 'INCR', 'DECR', 'DOUBLE_COLON', 'SEMI', 'ASSIGN', 'DOT', - 'IDENT', 'LIT_BOOL', 'FLOATNUMBER', 'NUMBER', 'STRING' ] + 'IDENT', 'LIT_BOOL', 'FLOATNUMBER', 'NUMBER', 'STRING', + 'AMP', 'CONST' ] tokens += reserved.values() t_EQ = r'==' @@ -149,6 +162,8 @@ t_PLUS = r'\+' t_DASH = r'-' t_STAR = r'\*' +t_AMP = r'&' +t_CONST = r'const' t_SLASH = r'/' t_MOD = r'%' t_DOUBLE_COLON = r'::' @@ -433,11 +448,19 @@ def p_param__pointer(self, p): "param : type STAR ident" -p[0] = ast.FormalParamAST(self, p[1], p[3], None, True) +p[0] = ast.FormalParamAST(self, p[1], p[3], None, "PTR") + +def p_param__ref(self, p): +"param : type AMP ident" +p[0] = ast.FormalParamAST(self, p[1], p[3], None, "REF") + +def p_param__const_ref(self, p): +"param : CONST type AMP ident" +p[0] = ast.FormalParamAST(self, p[1], p[3], None, "CONST_REF") def p_param__pointer_default(self, p): "param : type STAR ident ASSIGN STRING" -p[0] = ast.FormalParamAST(self, p[1], p[3], p[5], True) + p[0] = ast.FormalParamAST(self, p[1], p[3], p[5], "PTR") def p_param__default_number(self, p): "param : type ident ASSIGN NUMBER" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31259 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic6a18169a661b3e36710b2a9f8a0e6bc5fce40f8 Gerrit-Change-Number: 31259 Gerrit-PatchSet: 5 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: base: Fix `AddrRange::addIntlvBits(Addr)` and new test.
Isaac Sánchez Barrera has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37175 )
Change subject: base: Fix `AddrRange::addIntlvBits(Addr)` and new test.
..
base: Fix `AddrRange::addIntlvBits(Addr)` and new test.
The methods `AddrRange::removeIntlvBits(Addr)` and
`AddrRange::addIntlvBits(Addr)` should be the inverse of one another,
but the latter did not insert the blanks for filling the removed bits in
the correct positions. Since the masks are ordered increasingly by the
position of the least significant bit of each mask, the lowest bit that
has to be inserted at each iteration is always `intlv_bit`, not needing
to be shifted to the left or right. The bits that need to be copied
from the input address are `intlv_bit-1..0` at each iteration.
A new `AddrRangeTest.AddRemoveInterleavBitsAcrossContiguousRange` test
has been added to include a case in which the previous code fails but
the corrected code passes.
This function is not used anywhere other than the tests and the class
`ChannelAddr`. However, it is needed to implement efficiently multibank
caches in the classic mode.
Change-Id: I7d626a1f6ecf09a230fc18810d2dad2104d1a865
Signed-off-by: Isaac Sánchez Barrera
---
M src/base/addr_range.hh
M src/base/addr_range.test.cc
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index e333b32..8a811d4 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -523,9 +523,10 @@
const int intlv_bit = masks_lsb[i];
if (intlv_bit > 0) {
// on every iteration we add one bit from the input
-// address, and therefore the lowest invtl_bit has
-// also shifted to the left by i positions.
-a = insertBits(a << 1, intlv_bit + i - 1, 0, a);
+// address, but the lowest invtl_bit in the iteration is
+// always in the right position because they are sorted
+// increasingly from the LSB
+a = insertBits(a << 1, intlv_bit - 1, 0, a);
} else {
a <<= 1;
}
diff --git a/src/base/addr_range.test.cc b/src/base/addr_range.test.cc
index 34921d8..13b32a5 100644
--- a/src/base/addr_range.test.cc
+++ b/src/base/addr_range.test.cc
@@ -784,6 +784,34 @@
}
}
+TEST(AddrRangeTest, AddRemoveInterleavBitsAcrossContiguousRange)
+{
+/*
+ * This purpose of this test is to ensure that removing then adding
+ * interleaving bits has no net effect.
+ * E.g.:
+ * addr_range.addIntlvBits(add_range.removeIntlvBits(an_address))
should
+ * always return an_address.
+ */
+Addr start = 0x0;
+Addr end = 0x1;
+std::vector masks;
+masks.push_back(1 << 2);
+masks.push_back(1 << 3);
+masks.push_back(1 << 4);
+uint8_t intlv_match = 0x7;
+AddrRange r(start, end, masks, intlv_match);
+
+for (Addr i = 0; i < 0xFFF; i++) {
+Addr removedBits = r.removeIntlvBits(i);
+/*
+ * As intlv_match = 0x7, all the interleaved bits should be set.
+ */
+EXPECT_EQ(i | (1 << 2) | (1 << 3) | (1 << 4),
+ r.addIntlvBits(removedBits));
+}
+}
+
TEST(AddrRangeTest, InterleavingAddressesGetOffset)
{
Addr start = 0x0002;
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Add support for interleaved caches.
TRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Declaration of a set associative indexing policy.
+ */
+
+#ifndef __MEM_CACHE_INDEXING_POLICIES_INTLV_SET_ASSOCIATIVE_HH__
+#define __MEM_CACHE_INDEXING_POLICIES_INTLV_SET_ASSOCIATIVE_HH__
+
+#include "mem/cache/tags/indexing_policies/set_associative.hh"
+#include "params/IntlvSetAssociative.hh"
+
+/**
+ * An interleaved set associative indexing policy.
+ * @sa \ref gem5MemorySystem "gem5 Memory System"
+ *
+ * The set associative indexing policy has an immutable/identity mapping,
so a
+ * value x is always mapped to set x, independent of the way, that is,
+ * Hash(A, 0) = Hash(A, 1) = Hash(A, N-1), where N is the number of ways.
+ *
+ * For example, let's assume address A maps to set 3 on way 0. This policy
+ * makes so that A is also mappable to set 3 on every other way. Visually,
the
+ * possible locations of A are, for a table with 4 ways and 8 sets:
+ *Way 0 1 2 3
+ * Set _ _ _ _
+ *0 |_| |_| |_| |_|
+ *1 |_| |_| |_| |_|
+ *2 |_| |_| |_| |_|
+ *3 |X| |X| |X| |X|
+ *4 |_| |_| |_| |_|
+ *5 |_| |_| |_| |_|
+ *6 |_| |_| |_| |_|
+ *7 |_| |_| |_| |_|
+ *
+ * In this case, we are considering an interleaved cache, so the bits for
the
+ * interleave need to be taken into account.
+ */
+class IntlvSetAssociative : public SetAssociative
+{
+ protected:
+/**
+ * The address range defining the interleave policy.
+ */
+const AddrRange addrRange;
+
+/**
+ * Apply a hash function to calculate address set.
+ *
+ * @param addr The address to calculate the set for.
+ * @return The set index for given combination of address and way.
+ */
+uint32_t extractSet(const Addr addr) const override;
+
+ public:
+/**
+ * Convenience typedef.
+ */
+typedef IntlvSetAssociativeParams Params;
+
+/**
+ * Construct and initialize this policy.
+ */
+IntlvSetAssociative(const Params &p);
+
+/**
+ * Destructor.
+ */
+~IntlvSetAssociative() {};
+
+/**
+ * Generate the tag from the given address.
+ *
+ * @param addr The address to get the tag from.
+ * @return The tag of the address.
+ */
+Addr extractTag(const Addr addr) const override;
+
+/**
+ * Regenerate an entry's address from its tag and assigned indexing
bits.
+ *
+ * @param tag The tag bits.
+ * @param entry The entry.
+ * @return the entry's original address.
+ */
+Addr regenerateAddr(const Addr tag, const ReplaceableEntry* entry)
const
+
override;
+};
+
+#endif //__MEM_CACHE_INDEXING_POLICIES_INTLV_SET_ASSOCIATIVE_HH__
--
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[gem5-dev] Change in gem5/gem5[develop]: base: Fix `AddrRange::addIntlvBits(Addr)` and new test.
Isaac Sánchez Barrera has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37175 )
Change subject: base: Fix `AddrRange::addIntlvBits(Addr)` and new test.
..
base: Fix `AddrRange::addIntlvBits(Addr)` and new test.
The methods `AddrRange::removeIntlvBits(Addr)` and
`AddrRange::addIntlvBits(Addr)` should be the inverse of one another,
but the latter did not insert the blanks for filling the removed bits in
the correct positions. Since the masks are ordered increasingly by the
position of the least significant bit of each mask, the lowest bit that
has to be inserted at each iteration is always `intlv_bit`, not needing
to be shifted to the left or right. The bits that need to be copied
from the input address are `intlv_bit-1..0` at each iteration.
The test `AddrRangeTest.AddRemoveInterleavBitsAcrossRange` has been
updated have masks below bit 12, making the old code not pass the test.
A new `AddrRangeTest.AddRemoveInterleavBitsAcrossContiguousRange` test
has been added to include a case in which the previous code fails. The
corrected code passes both tests.
This function is not used anywhere other than the tests and the class
`ChannelAddr`. However, it is needed to efficiently implement
interleaved caches in the classic mode.
Change-Id: I7d626a1f6ecf09a230fc18810d2dad2104d1a865
Signed-off-by: Isaac Sánchez Barrera
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37175
Tested-by: kokoro
Reviewed-by: Nikos Nikoleris
Reviewed-by: Bobby R. Bruce
Maintainer: Nikos Nikoleris
Maintainer: Bobby R. Bruce
---
M src/base/addr_range.hh
M src/base/addr_range.test.cc
2 files changed, 35 insertions(+), 6 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index e333b32..8a811d4 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -523,9 +523,10 @@
const int intlv_bit = masks_lsb[i];
if (intlv_bit > 0) {
// on every iteration we add one bit from the input
-// address, and therefore the lowest invtl_bit has
-// also shifted to the left by i positions.
-a = insertBits(a << 1, intlv_bit + i - 1, 0, a);
+// address, but the lowest invtl_bit in the iteration is
+// always in the right position because they are sorted
+// increasingly from the LSB
+a = insertBits(a << 1, intlv_bit - 1, 0, a);
} else {
a <<= 1;
}
diff --git a/src/base/addr_range.test.cc b/src/base/addr_range.test.cc
index 34921d8..f2d4efa 100644
--- a/src/base/addr_range.test.cc
+++ b/src/base/addr_range.test.cc
@@ -769,8 +769,8 @@
std::vector masks;
masks.push_back(1 << 2);
masks.push_back(1 << 3);
-masks.push_back(1 << 16);
-masks.push_back(1 << 30);
+masks.push_back(1 << 7);
+masks.push_back(1 << 11);
uint8_t intlv_match = 0xF;
AddrRange r(start, end, masks, intlv_match);
@@ -779,7 +779,35 @@
/*
* As intlv_match = 0xF, all the interleaved bits should be set.
*/
-EXPECT_EQ(i | (1 << 2) | (1 << 3) | (1 << 16) | (1 << 30),
+EXPECT_EQ(i | (1 << 2) | (1 << 3) | (1 << 7) | (1 << 11),
+ r.addIntlvBits(removedBits));
+}
+}
+
+TEST(AddrRangeTest, AddRemoveInterleavBitsAcrossContiguousRange)
+{
+/*
+ * This purpose of this test is to ensure that removing then adding
+ * interleaving bits has no net effect.
+ * E.g.:
+ * addr_range.addIntlvBits(add_range.removeIntlvBits(an_address))
should
+ * always return an_address.
+ */
+Addr start = 0x0;
+Addr end = 0x1;
+std::vector masks;
+masks.push_back(1 << 2);
+masks.push_back(1 << 3);
+masks.push_back(1 << 4);
+uint8_t intlv_match = 0x7;
+AddrRange r(start, end, masks, intlv_match);
+
+for (Addr i = 0; i < 0xFFF; i++) {
+Addr removedBits = r.removeIntlvBits(i);
+/*
+ * As intlv_match = 0x7, all the interleaved bits should be set.
+ */
+EXPECT_EQ(i | (1 << 2) | (1 << 3) | (1 << 4),
r.addIntlvBits(removedBits));
}
}
--
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Gerrit-Change-Id: I7d626a1f6ecf09a230fc18810d2dad2104d1a865
Gerrit-Change-Number: 37175
Gerrit-PatchSet: 5
Gerrit-Owner: Isaac Sánchez Barrera
Gerr
[gem5-dev] Change in gem5/gem5[develop]: base: Prevent undefined behavior in not interleaved `AddrRange`s.
Isaac Sánchez Barrera has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37617 )
Change subject: base: Prevent undefined behavior in not interleaved
`AddrRange`s.
..
base: Prevent undefined behavior in not interleaved `AddrRange`s.
If an `AddrRange` is not interleaved, return the input address in
`removeIntlvBits` and `addIntlvBits` to prevent undefined behavior. It
allows to use these methods in all cases without having to check manually
whether the range is interleaved.
Change-Id: Ic6ac8c4e52b09417bc41aa9380a24319c34e0b35
Signed-off-by: Isaac Sánchez Barrera
---
M src/base/addr_range.hh
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index 8a811d4..7572d97 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -473,12 +473,18 @@
* -
*
* @param a the input address
- * @return the new address
+ * @return the new address, or the input address if not interleaved
*
* @ingroup api_addr_range
*/
inline Addr removeIntlvBits(Addr a) const
{
+// Directly return the address if the range is not interleaved
+// to prevent undefined behavior.
+if (!interleaved()) {
+return a;
+}
+
// Get the LSB set from each mask
int masks_lsb[masks.size()];
for (int i = 0; i < masks.size(); i++) {
@@ -511,6 +517,12 @@
*/
inline Addr addIntlvBits(Addr a) const
{
+// Directly return the address if the range is not interleaved
+// to prevent undefined behavior.
+if (!interleaved()) {
+return a;
+}
+
// Get the LSB set from each mask
int masks_lsb[masks.size()];
for (int i = 0; i < masks.size(); i++) {
--
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[gem5-dev] Change in gem5/gem5[develop]: base: Prevent undefined behavior in not interleaved `AddrRange`s.
Isaac Sánchez Barrera has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37617 )
Change subject: base: Prevent undefined behavior in not interleaved
`AddrRange`s.
..
base: Prevent undefined behavior in not interleaved `AddrRange`s.
If an `AddrRange` is not interleaved, return the input address in
`removeIntlvBits` and `addIntlvBits` to prevent undefined behavior. It
allows to use these methods in all cases without having to check
manually whether the range is interleaved.
Change-Id: Ic6ac8c4e52b09417bc41aa9380a24319c34e0b35
Signed-off-by: Isaac Sánchez Barrera
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37617
Maintainer: Bobby R. Bruce
Tested-by: kokoro
Reviewed-by: Nikos Nikoleris
---
M src/base/addr_range.hh
1 file changed, 13 insertions(+), 1 deletion(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index 8a811d4..7572d97 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -473,12 +473,18 @@
* -
*
* @param a the input address
- * @return the new address
+ * @return the new address, or the input address if not interleaved
*
* @ingroup api_addr_range
*/
inline Addr removeIntlvBits(Addr a) const
{
+// Directly return the address if the range is not interleaved
+// to prevent undefined behavior.
+if (!interleaved()) {
+return a;
+}
+
// Get the LSB set from each mask
int masks_lsb[masks.size()];
for (int i = 0; i < masks.size(); i++) {
@@ -511,6 +517,12 @@
*/
inline Addr addIntlvBits(Addr a) const
{
+// Directly return the address if the range is not interleaved
+// to prevent undefined behavior.
+if (!interleaved()) {
+return a;
+}
+
// Get the LSB set from each mask
int masks_lsb[masks.size()];
for (int i = 0; i < masks.size(); i++) {
--
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Gerrit-Change-Id: Ic6ac8c4e52b09417bc41aa9380a24319c34e0b35
Gerrit-Change-Number: 37617
Gerrit-PatchSet: 4
Gerrit-Owner: Isaac Sánchez Barrera
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Isaac Sánchez Barrera
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-CC: Daniel Carvalho
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: add resource stalls to MSI protocol
k definitions
// Output ports. This defines the message types that will flow ocross
the
@@ -406,7 +468,10 @@
// The "mandatory queue" is the port/queue from the CPU or other
processor.
// This is *always* a RubyRequest
-in_port(mandatory_in, RubyRequest, mandatoryQueue) {
+// If this queue triggers an event that triggers a resource stall,
+// the mandatory_in_stall_handler functions is called to handle the
stall.
+in_port(mandatory_in, RubyRequest, mandatoryQueue,
+rsc_stall_handler=mandatory_in_stall_handler) {
if (mandatory_in.isReady(clockEdge())) {
// Block all requests if there is already an outstanding
request
// that has the same line address. This is unblocked when we
@@ -444,6 +509,19 @@
}
}
+bool mandatory_in_stall_handler() {
+peek(mandatory_in, RubyRequest) {
+DPRINTF(RubyResourceStalls,
+"Resource stall in mandatory queue, msg: %s\n", in_msg);
+}
+// The handler should return 'true' to indicate the stall was
handled
+// and we can keep processing messages from this queue in this
cycle.
+// When it returns 'false' (or if no handler was defined), the
actual
+// resource stall is generated.
+// In this case we do nothing special to handle it so returns
false.
+return false;
+}
+
/*/
// Below are all of the actions that might be taken on a transition.
@@ -699,7 +777,10 @@
// examples of transition statements.
// Within the transition statement is a set of action to take during
the
// transition. These actions are executed atomically (i.e., all or
nothing)
-transition(I, Load, IS_D) {
+// Notice the "{TagArrayRead,DataArrayRead}" annotation in the
transition
+// declaration. If the cache tag/data arrays are not available a
resource
+// stall is generated.
+transition(I, Load, IS_D) {TagArrayRead, DataArrayRead} {
// Make sure there is room in the cache to put the block whenever
the
// miss returns. Otherwise we could deadlock.
allocateCacheBlock;
@@ -712,7 +793,7 @@
popMandatoryQueue;
}
-transition(I, Store, IM_AD) {
+transition(I, Store, IM_AD) {TagArrayRead, DataArrayRead} {
allocateCacheBlock;
allocateTBE;
sendGetM;
@@ -729,7 +810,9 @@
}
// Similarly, on either DataDirNoAcks or DataOwner we should go to S
-transition(IS_D, {DataDirNoAcks, DataOwner}, S) {
+transition(IS_D, {DataDirNoAcks, DataOwner}, S)
+{TagArrayWrite, DataArrayWrite}
+{
writeDataToCache;
deallocateTBE;
externalLoadHit;
@@ -740,7 +823,9 @@
stall;
}
-transition({IM_AD, SM_AD}, {DataDirNoAcks, DataOwner}, M) {
+transition({IM_AD, SM_AD}, {DataDirNoAcks, DataOwner}, M)
+{TagArrayWrite, DataArrayWrite}
+{
writeDataToCache;
deallocateTBE;
externalStoreHit;
@@ -758,7 +843,7 @@
popResponseQueue;
}
-transition({IM_A, SM_A}, LastInvAck, M) {
+transition({IM_A, SM_A}, LastInvAck, M) {TagArrayWrite,
DataArrayWrite} {
deallocateTBE;
externalStoreHit;
popResponseQueue;
@@ -769,7 +854,7 @@
popMandatoryQueue;
}
-transition(S, Store, SM_AD) {
+transition(S, Store, SM_AD) {TagArrayRead, DataArrayRead} {
allocateTBE;
sendGetM;
popMandatoryQueue;
@@ -801,7 +886,7 @@
popResponseQueue;
}
-transition(M, Store) {
+transition(M, Store) {DataArrayWrite} {
storeHit;
forwardEviction;
popMandatoryQueue;
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: functions for connecting sequencer ports
Tiago Mück has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31417 ) Change subject: mem-ruby: functions for connecting sequencer ports .. mem-ruby: functions for connecting sequencer ports Added functions for connecting the sequencer and cpu ports. Using these functions instead of wiring up the ports directly allow protocols to provide specialized sequencer implementations. For instance, connecting the cpu icache_port and dcache_port to different sequencer ports or to different sequencers. A follow-up patch will update the configurations to use these functions. Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31417 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/mem/ruby/system/Sequencer.py 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 0e23fc0..f56574c 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -99,6 +99,32 @@ # 99 is the dummy default value coreid = Param.Int(99, "CorePair core id") + def connectCpuPorts(self, cpu): + """ + Helper for connecting all cpu memory request output ports to this + object's in_ports. + This assumes the provided cpu object is an instance of BaseCPU. Non-cpu + objects should use connectInstPort and connectDataPort. + """ + import m5.objects + assert(isinstance(cpu, m5.objects.BaseCPU)) + # this connects all cpu mem-side ports to self.in_ports + cpu.connectAllPorts(self) + + def connectIOPorts(self, piobus): + """ + Helper for connecting this object's IO request and response ports to the + provided bus object. Usually a iobus object is used to wireup IO + components in a full system simulation. Incoming/Outgoing IO requests do + not go though the SLICC protocol so the iobus must be connected to the + sequencer directly. + """ + import m5.defines + self.pio_request_port = piobus.cpu_side_ports + self.mem_request_port = piobus.cpu_side_ports + if m5.defines.buildEnv['TARGET_ISA'] == "x86": + self.pio_response_port = piobus.mem_side_ports + class RubyHTMSequencer(RubySequencer): type = 'RubyHTMSequencer' cxx_class = 'HTMSequencer' -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31417 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b Gerrit-Change-Number: 31417 Gerrit-PatchSet: 7 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Bradford Beckmann Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: configs,tests: use Sequencer port connect methods
nterrupts[0].int_master = self.sequencers[i].slave
-cpu.interrupts[0].int_slave = self.sequencers[i].master
+self.sequencers[i].connectCpuPorts(cpu)
class L1Cache(L1Cache_Controller):
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 86d5748..8aa99be 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -226,11 +226,7 @@
# Connect the cpu sequencers and the piobus
if piobus != None:
for cpu_seq in cpu_sequencers:
-cpu_seq.pio_master_port = piobus.slave
-cpu_seq.mem_master_port = piobus.slave
-
-if buildEnv['TARGET_ISA'] == "x86":
-cpu_seq.pio_slave_port = piobus.master
+cpu_seq.connectIOPorts(piobus)
ruby.number_of_virtual_networks =
ruby.network.number_of_virtual_networks
ruby._cpu_ports = cpu_sequencers
diff --git a/tests/configs/pc-simple-timing-ruby.py
b/tests/configs/pc-simple-timing-ruby.py
index c78033b..884fd7d 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -78,14 +78,7 @@
# create the interrupt controller
cpu.createInterruptController()
# Tie the cpu ports to the correct ruby system ports
-cpu.icache_port = system.ruby._cpu_ports[i].slave
-cpu.dcache_port = system.ruby._cpu_ports[i].slave
-cpu.mmu.connectWalkerPorts(
-system.ruby._cpu_ports[i].slave, system.ruby._cpu_ports[i].slave)
-
-cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
-cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
-cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
+system.ruby._cpu_ports[i].connectCpuPorts(cpu)
root = Root(full_system = True, system = system)
m5.ticks.setGlobalFrequency('1THz')
--
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Gerrit-Change-Id: I1e931ff0fc93f393cb36fbb8769ea4b48e1a1e86
Gerrit-Change-Number: 31418
Gerrit-PatchSet: 7
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: able to define resource stalls handlers
f generate(self, code, return_type, **kwargs):
actual_type, ecode = self.expr_ast.inline(True)
code('return $ecode;')
diff --git a/src/mem/slicc/ast/StallAndWaitStatementAST.py
b/src/mem/slicc/ast/StallAndWaitStatementAST.py
index ad261e2..04d9e20 100644
--- a/src/mem/slicc/ast/StallAndWaitStatementAST.py
+++ b/src/mem/slicc/ast/StallAndWaitStatementAST.py
@@ -37,7 +37,7 @@
def __repr__(self):
return "[StallAndWaitStatementAst: %r]" % self.in_port
-def generate(self, code, return_type):
+def generate(self, code, return_type, **kwargs):
self.in_port.assertType("InPort")
self.address.assertType("Addr")
diff --git a/src/mem/slicc/ast/StatementListAST.py
b/src/mem/slicc/ast/StatementListAST.py
index 1475c5c..9d74e66 100644
--- a/src/mem/slicc/ast/StatementListAST.py
+++ b/src/mem/slicc/ast/StatementListAST.py
@@ -37,9 +37,9 @@
def __repr__(self):
return "[StatementListAST: %r]" % self.statements
-def generate(self, code, return_type):
+def generate(self, code, return_type, **kwargs):
for statement in self.statements:
-statement.generate(code, return_type)
+statement.generate(code, return_type, **kwargs)
def findResources(self, resources):
for statement in self.statements:
diff --git a/src/mem/slicc/ast/StaticCastAST.py
b/src/mem/slicc/ast/StaticCastAST.py
index 71280ba..4c66486 100644
--- a/src/mem/slicc/ast/StaticCastAST.py
+++ b/src/mem/slicc/ast/StaticCastAST.py
@@ -37,7 +37,7 @@
def __repr__(self):
return "[StaticCastAST: %r]" % self.expr_ast
-def generate(self, code):
+def generate(self, code, **kwargs):
actual_type, ecode = self.expr_ast.inline(True)
if self.type_modifier == "pointer":
code('static_cast<${{self.type_ast.type.c_ident}} *>($ecode)')
diff --git a/src/mem/slicc/ast/TypeFieldEnumAST.py
b/src/mem/slicc/ast/TypeFieldEnumAST.py
index b9a8ae8..f554990 100644
--- a/src/mem/slicc/ast/TypeFieldEnumAST.py
+++ b/src/mem/slicc/ast/TypeFieldEnumAST.py
@@ -38,7 +38,7 @@
def __repr__(self):
return "[TypeFieldEnum: %r]" % self.field_id
-def generate(self, type):
+def generate(self, type, **kwargs):
if str(type) == "State":
self.error("States must in a State Declaration, not a normal
enum.")
diff --git a/src/mem/slicc/ast/TypeFieldStateAST.py
b/src/mem/slicc/ast/TypeFieldStateAST.py
index deac143..ff1ae97 100644
--- a/src/mem/slicc/ast/TypeFieldStateAST.py
+++ b/src/mem/slicc/ast/TypeFieldStateAST.py
@@ -40,7 +40,7 @@
def __repr__(self):
return "[TypeFieldState: %r]" % self.field_id
-def generate(self, type):
+def generate(self, type, **kwargs):
if not str(type) == "State":
self.error("State Declaration must be of type State.")
diff --git a/src/mem/slicc/ast/VarExprAST.py
b/src/mem/slicc/ast/VarExprAST.py
index 19a619b..f555c72 100644
--- a/src/mem/slicc/ast/VarExprAST.py
+++ b/src/mem/slicc/ast/VarExprAST.py
@@ -60,7 +60,7 @@
"'%s' is expected to be type '%s' not '%s'",
self.var.ident, expected_type, self.var.type)
-def generate(self, code):
+def generate(self, code, **kwargs):
fix = code.nofix()
code("${{self.var.code}}")
code.fix(fix)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31265
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3481d130d5eb411e6760a54d098d3da5de511c86
Gerrit-Change-Number: 31265
Gerrit-PatchSet: 6
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Fix lsq unit address limit overflow
周耀阳 has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/38935 ) Change subject: cpu-o3: Fix lsq unit address limit overflow .. cpu-o3: Fix lsq unit address limit overflow Change-Id: I036e0fc7fe421d8536a6d627f0f76ff5c609bbc7 --- M src/cpu/o3/lsq_unit.hh 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index dbe15e6..8b10370 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -753,14 +753,17 @@ // Check if the store data is within the lower and upper bounds of // addresses that the request needs. auto req_s = req->mainRequest()->getVaddr(); -auto req_e = req_s + req->mainRequest()->getSize(); +auto req_e = req_s - 1 + req->mainRequest()->getSize(); auto st_s = store_it->instruction()->effAddr; -auto st_e = st_s + store_size; +auto st_e = st_s - 1 + store_size; bool store_has_lower_limit = req_s >= st_s; -bool store_has_upper_limit = req_e <= st_e; -bool lower_load_has_store_part = req_s < st_e; -bool upper_load_has_store_part = req_e > st_s; +// bool store_has_upper_limit = req_e <= st_e; +bool store_has_upper_limit = +req_s - store_size <= st_s - req->mainRequest()->getSize(); + +bool lower_load_has_store_part = req_s <= st_e; +bool upper_load_has_store_part = req_e >= st_s; auto coverage = AddrRangeCoverage::NoAddrRangeCoverage; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/38935 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I036e0fc7fe421d8536a6d627f0f76ff5c609bbc7 Gerrit-Change-Number: 38935 Gerrit-PatchSet: 1 Gerrit-Owner: 周耀阳 Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Implementation of s_sleep
when the
barrier is
// the last instruction in the instruction buffer.
@@ -143,7 +152,8 @@
// through this logic and always return not ready.
if (!(ii->isBarrier() || ii->isNop() || ii->isReturn() ||
ii->isBranch() ||
ii->isALU() || ii->isLoad() || ii->isStore() || ii->isAtomic() ||
- ii->isEndOfKernel() || ii->isMemSync() || ii->isFlat())) {
+ ii->isEndOfKernel() || ii->isMemSync() || ii->isFlat() ||
+ ii->isSleep())) {
panic("next instruction: %s is of unknown type\n",
ii->disassemble());
}
diff --git a/src/gpu-compute/scoreboard_check_stage.hh
b/src/gpu-compute/scoreboard_check_stage.hh
index c45ea75..714c761 100644
--- a/src/gpu-compute/scoreboard_check_stage.hh
+++ b/src/gpu-compute/scoreboard_check_stage.hh
@@ -64,6 +64,7 @@
NRDY_WF_STOP,
NRDY_IB_EMPTY,
NRDY_WAIT_CNT,
+NRDY_SLEEP,
NRDY_BARRIER_WAIT,
NRDY_VGPR_NRDY,
NRDY_SGPR_NRDY,
diff --git a/src/gpu-compute/wavefront.cc b/src/gpu-compute/wavefront.cc
index b7ff95a..00c4fd9 100644
--- a/src/gpu-compute/wavefront.cc
+++ b/src/gpu-compute/wavefront.cc
@@ -49,7 +49,7 @@
maxIbSize(p.max_ib_size), _gpuISA(*this),
vmWaitCnt(-1), expWaitCnt(-1), lgkmWaitCnt(-1),
vmemInstsIssued(0), expInstsIssued(0), lgkmInstsIssued(0),
-barId(WFBarrier::InvalidID)
+sleepCnt(0), barId(WFBarrier::InvalidID)
{
lastTrace = 0;
execUnitId = -1;
@@ -653,6 +653,20 @@
}
bool
+Wavefront::isOldestInstSleep()
+{
+if (instructionBuffer.empty())
+return false;
+
+GPUDynInstPtr ii = instructionBuffer.front();
+
+if (ii->isSleep()) {
+return true;
+}
+return false;
+}
+
+bool
Wavefront::isOldestInstWaitcnt()
{
if (instructionBuffer.empty())
@@ -1282,6 +1296,32 @@
return true;
}
+bool
+Wavefront::sleepDone()
+{
+assert(status == S_STALLED_SLEEP);
+
+// if the sleep count has not been set, then the sleep instruction has
not
+// been executed yet, so we will return true without setting the
wavefront
+// status
+if (sleepCnt == 0)
+return false;
+
+sleepCnt--;
+if (sleepCnt != 0)
+return false;
+
+status = S_RUNNING;
+return true;
+}
+
+void
+Wavefront::setSleepTime(int sleep_time)
+{
+assert(sleepCnt == 0);
+sleepCnt = sleep_time;
+}
+
void
Wavefront::setWaitCnts(int vm_wait_cnt, int exp_wait_cnt, int
lgkm_wait_cnt)
{
diff --git a/src/gpu-compute/wavefront.hh b/src/gpu-compute/wavefront.hh
index 80fc324..414240c 100644
--- a/src/gpu-compute/wavefront.hh
+++ b/src/gpu-compute/wavefront.hh
@@ -66,6 +66,9 @@
S_RUNNING,
// wavefront is stalled
S_STALLED,
+
+S_STALLED_SLEEP,
+
/**
* wavefront has unsatisfied wait counts
*
@@ -132,6 +135,7 @@
bool isGmInstruction(GPUDynInstPtr ii);
bool isLmInstruction(GPUDynInstPtr ii);
bool isOldestInstWaitcnt();
+bool isOldestInstSleep();
bool isOldestInstGMem();
bool isOldestInstLMem();
bool isOldestInstPrivMem();
@@ -314,6 +318,9 @@
/** Freeing VRF space */
void freeRegisterFile();
+bool sleepDone();
+void setSleepTime(int sleep_time);
+
TheGpuISA::GPUISA&
gpuISA()
{
@@ -353,6 +360,7 @@
int vmemInstsIssued;
int expInstsIssued;
int lgkmInstsIssued;
+int sleepCnt;
status_e status;
Addr _pc;
VectorMask _execMask;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4811c318ac2c76c485e2bfd9d93baa1205ecf183
Gerrit-Change-Number: 39115
Gerrit-PatchSet: 1
Gerrit-Owner: Alexandru Duțu
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: python: more readable Ruby dot topology
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41093 )
Change subject: python: more readable Ruby dot topology
..
python: more readable Ruby dot topology
Controllers may have the same name under different parents, thus
the controller full path is used as label. To avoid long and redundant
labels, common prefixes and suffixes are removed from the path.
Change-Id: Id793b59a4c38f3425ae5348138ae1d74c823edd7
---
M src/python/m5/util/dot_writer_ruby.py
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/src/python/m5/util/dot_writer_ruby.py
b/src/python/m5/util/dot_writer_ruby.py
index 9356a94..4123cac 100644
--- a/src/python/m5/util/dot_writer_ruby.py
+++ b/src/python/m5/util/dot_writer_ruby.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2019 ARM Limited
+# Copyright (c) 2019,2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -90,9 +90,24 @@
)
connected[link.dst_node.path()] = link.src_node.path()
+# Find common prefixes and sufixes to generate names
+paths = [link.ext_node.path() for link in network.ext_links]
+rpaths = [link.ext_node.path()[::-1] for link in network.ext_links]
+preffix = os.path.commonprefix(paths)
+suffix = os.path.commonprefix(rpaths)[::-1]
+def strip_right(text, suffix):
+if not text.endswith(suffix):
+return text
+return text[:len(text)-len(suffix)]
+def strip_left(text, prefix):
+if not text.startswith(prefix):
+return text
+return text[len(prefix):]
+
+
for link in network.ext_links:
ctrl = link.ext_node
-label = ctrl._name
+label = strip_right(strip_left(ctrl.path(), preffix), suffix)
if hasattr(ctrl, '_node_type'):
label += ' (' + ctrl._node_type + ')'
callgraph.add_node(
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id793b59a4c38f3425ae5348138ae1d74c823edd7
Gerrit-Change-Number: 41093
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück
Gerrit-MessageType: newchange
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