Re: [gem5-users] gem5 stable release proposal [PLEASE VOTE!]
Hello, - I think master should be stable. - I think gem5 should be released three times per year. Regards, -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E301, Campus de Beaulieu, 35042 Rennes Cedex, France - Original Message - > From: "Jason Lowe-Power" > To: "gem5 Developer List" , "gem5 users mailing list" > > Sent: Monday, December 16, 2019 8:50:12 PM > Subject: [gem5-users] gem5 stable release proposal [PLEASE VOTE!] > Hi all, > > As many of you have seen on gem5-dev, we are going to be adding a > "stable" version of gem5. Below is the current proposal. There are a > couple of points below where there has not been general consensus > reached. We would appreciate feedback *from everyone in the community* > on the points where a decision hasn't been made below. gem5 is a > community-driven project, and we need feedback to make sure we're > making community-focused decisions. > > We will be introducing a new "stable" branch type to gem5. We are > doing this for the following reasons: > - Provide a way for developers to communicate major changes to the > code. We will be providing detailed release notes for each stable > release. > - Increase our test coverage. At each stable release, we will test a > large number of "common" benchmarks and configurations and publicize > the current state of gem5. > - Provide a way for researchers to communicate to the rest of the > community information about their simulation infrastructure (e.g., in > a paper you can say which version of gem5 you used). > > On the stable version of gem5, we will provide bugfixes until the > next release, but we will not make any API changes or add new > features. > > We would like your feedback on the following two questions: > > **Which branch should be default?** > > We can either have the master branch in git be the "stable" or the > "development" branch. If master is the stable branch, then it's easier > for users to get the most recent stable branch. If master is the > development branch, it's more familiar and easier for most developers. > Either way, we will be updating all of the documentation to make it > clear. > > Please let us know which you prefer by replying "I think master should > be stable" or "I think master should be development". > > **How often should we create a new gem5 release?** > > We can have a gem5 release once per year (likely in April) or three > times per year (April, August, and December). Once per year means that > if you use the stable branch you will get updates less frequently. > Three times per year will mean there are more releases to choose from > (but a newer release should always be better). On the development > side, I don't think one will be more work than the other. Once per > year means more backporting, and three times per year means more > testing and time spent on releases. > > Please let us know which you prefer by replying "I think gem5 should > be released once per year" or "I think gem5 should be released three > times per year." > > > > > A couple of notes to everyone who's been following the discussion on > the gem5-dev mailing list: > - We have dropped the proposal for major vs minor releases. Note that > there was some pushback on having only major releases when this was > proposed on the gem5 roadmap, but it sounded like the consensus was to > drop minor releases for now. > - We will still allow feature branches *in rare circumstances*. This > will be by request only (send mail to gem5-dev if you would like to > discuss adding a new branch), and the goal will be integration within > a few months. All code review will still happen in the open on gerrit. > The benefits will be > 1) rebases won't be required as you can just make changes to the head > of the branch > 2) many features take more than a few months to implement, so if it's > not ready by a release it can be pushed to the next > 3) large changes won't be hidden in AMD or Arm-specific repositories > and *anyone* will be able to request a branch. > > Thanks everyone for the discussions so far! It would be most useful to > hear back by the end of the week. However, I don't expect any concrete > actions will be taken until after the holidays. > > Cheers, > Jason > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Use checkpoints that have been created from older GEM5 version
Hello, for upgrading checkpoints you can use the "cpt_upgrader.py" in util/cpt_upgraders. Normally, this will do, unless some upgrade is not implemented already. Then you have to create alone the equivalent upgrader to call. Hope it helps. -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France - Original Message - > From: "Michail Mavropoulos" > To: "gem5 users mailing list" > Sent: Friday, July 19, 2019 4:03:06 PM > Subject: [gem5-users] Use checkpoints that have been created from older GEM5 > version > Hello, > > I have created checkpoints, for SPEC2006 benchmarks, from older GEM5 > version (mercurial head id 10500:5e0a421e2031) and I need to import > them into the final GEM5 version (git head > 4d4c38c7c02aca9922d7f30f2f399bbe94c034eb59). > > Unforunately, when I try to run a full system simulation I get the > following: > fatal: Can't unserialize 'system.apicbridge:currPwrState' > > Is it a checkpoint issue or a configuration issue? > Should I re-create the checkpoints from the latest GEM5 version? > > I run the following command: > ./build/X86/gem5.opt -i configs/example/fs.py --kernel=kernel_path > --disk-image=disk_path --warmup-insts=20 --maxinsts=100 > --checkpoint-dir=spec_checkpoints/astar/lakes/ -r 1 --bench=astar_lakes > --cpu-type=AtomicSimpleCPU --mem-size=2048MB > --restore-with-cpu=DerivO3CPU > > Thank you, > mmavrop > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] questions about template policies in O3CPU
Hello, the lsq_unit, as long as other basic parts in the pipeline (i.e., fetch, decode etc) are generally defined as template classes as you said. The equivalent *.c files instantiate the object by calling with a specific argument, in this case with the "O3CPUImpl" argument. These .c files are the ones that include the necessary header files and are given as source for compilation in the SConscript file, for instance in the one in the o3 folder, when it comes to the o3 model. Hope it helps. Regards, -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France > From: "yuan" > To: "gem5 users mailing list" > Sent: Tuesday, July 16, 2019 10:59:46 PM > Subject: [gem5-users] questions about template policies in O3CPU > Hi, all, > I am trying to understand the O3CPU code. But I find that the template policy > is > heavily used in O3CPU and I am quiet confused about this part. Like the load > store queue, the lsq_unit.hh file has all the class declaration of lsq_unit, > but in the lsq_unit.cc file, there is only one statement “template class > LSQUnit;”. My understanding is that all the functions in > lsq_unint.hh are actually defined/implemented in lsq_unit_impl.hh files. The > O3CPUImpl is actually defined in impl.hh file. But what the lsq_unit.cc file > is > actually doing? And what is the design model behind this template usage? Does > anyone know about this part. Thanks so much. > Best regards. > Yuan > Sent from [ https://go.microsoft.com/fwlink/?LinkId=550986 | Mail ] for > Windows > 10 > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] SPECCPU 2006 application crashes on x86 gem5
Hello, it is normal to get these warnings for unimplemented instructions. However, in my experience, these warnings are not the case for aborting. Normally some panic message follows, but maybe not related to this "warn". For instance, there is the case of avx instructions that are not implemented and will abort the execution : [ https://gem5-users.gem5.narkive.com/jO22f7kV/spec2017-on-gem5-se-mode | https://gem5-users.gem5.narkive.com/jO22f7kV/spec2017-on-gem5-se-mode ] Regards, -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France > From: "Shyam Murthy" > To: "gem5 users mailing list" > Sent: Sunday, June 30, 2019 7:02:37 PM > Subject: [gem5-users] SPECCPU 2006 application crashes on x86 gem5 > Hi All, > I am trying to run some of the FP applications from SPECCPU 2006. However, for > some of these applications (like povray, tonto), I get an error that says: > warn: instruction 'movntdq_Mo_Vo' unimplemented. > I am compiling these applications on my machine, and then running them on x86 > gem5. My machine uses gcc version 7.4.0. I tried using gcc version 5.5 > (already > installed on my machine), but the problem persists. > Any suggestions as to what I can do to fix this? > Thanks, > Shyam > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] On checkpointing while using custom config file
Hello, I have done something similar, taking a checkpoint after booting the image. However, I use only the "m5 exit" command instead of the "m5 checkpoint" and I take checkpoints using AtomicSimple and the fs.py. You can replace "checkpoint" with "exit" to see if it works for your configuration. In order this to work, you HAVE to use the option "--checkpoint-at-end" in your gem5 command. You can also specify a path for the checkpoint output to have a clear result by using "--checkpoint-dir=PATH_TO_DIR". This way, after booting, gem5 exits and with the above option a checkpoint is triggered. Example .rcS script : . /sbin/m5 exit runspec --config=myconfig.cfg --size=test --noreportable --tune=base --iterations=1 mcf echo "mcf done!" /sbin/m5 exit After you can restore your checkpoint and continue execution using the same .rcS script, it will actually continue after the first m5 exit, which is just after booting. Hope it helps, -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France > From: "Sethu Jose" > To: "gem5 users mailing list" > Sent: Sunday, April 28, 2019 3:03:52 AM > Subject: [gem5-users] On checkpointing while using custom config file > Hi, > I'm trying out X86 full system simulation in GEM5 as explained in the tutorial > found in this link: > [ http://learning.gem5.org/book/part5/fs_config.html | > http://learning.gem5.org/book/part5/fs_config.html ] > I'm doing full system simulation using TimingSimpleCPU with X86. I would like > to > take checkpoint once the system has booted up. The command I use to run the > simulation is as follows: > build/X86/gem5.opt configs/full_system/run.py --script=path/to/script > With this, the system boots up and executes the script. > I plan to take checkpoint right after booting up the system. Hence, I have > added > the following line to the script: > > echo "Creating checkpoint..." > /sbin/m5 checkpoint > echo "Checkpoint created!" > echo "Started mcf ..." > runspec --config=myconfig.cfg --size=test --noreportable --tune=base > --iterations=1 mcf > echo "mcf done!" > /sbin/m5 exit > > With this, the simulation exits when running /sbin/m5 stating the exit cause > as > checkpoint. However, no checkpoint folders are created in the working > directory. Neither does the restore command work. I have tried take checkpoint > by running /sbin/m5 exit in the booted up system terminal. This also causes > the > simulation to exit without creating any checkpoint folders. > As I'm new to GEM5, could you please provide any insights on this issue? Is > there any specific code that I need to add to my config file to make it take > checkpoint? > Thanks in advance for any help. > Regards, > Sethu > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Switching off AVX-512 for running SPEC 2017 in SE mode
Hello, I want to run the SPEC 2017 workloads in SE mode(X86), but when I do many of them run into an error about an unrecognised instruction. After some search I found this thread in the list : https://gem5-users.gem5.narkive.com/jO22f7kV/spec2017-on-gem5-se-mode where there was described exactly the same problem. The unrecognised instruction seems to be an AVX-512 one. I actually dumbed the assembly code of the binaries and I see some of them, so as instructed I compile benchmarks with "-mno-avx -mno-avx512f .." and many other flags to switch off these AVX instructions, but still the problem is the same. Maybe the question is not that gem5-relevant, but if somebody has successfully disabled these instructions and run in SE (X86) the SPEC 2017 benchmarks, would be of great help. Thank you in advance, -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Problem on restoring checkpoint while using O3CPU in Full System mode
Hello Taeklim, your problem sounds to me the same as the one I keep having. In my case, I searches a bit more and then I found that as you said instruction count does not increase because execution falls into an infinite loop of the same page fault (Microcode_ROM related.) I give you here the link to the thread of my emails when I first asked about the problem : [ https://www.mail-archive.com/gem5-users@gem5.org/msg16145.html | https://www.mail-archive.com/gem5-users@gem5.org/msg16145.html ] Unfortunately, I do not have the solution , but it would be very nice if you could also just use the flags I mention (--debug-flags=Exec,LocalApic,Faults) to see if the problem is related with the same issue. Looking forward for any feedback. Regards, -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France > From: "Taeklim Kim" > To: "gem5 users mailing list" > Sent: Thursday, December 20, 2018 1:12:38 AM > Subject: [gem5-users] Problem on restoring checkpoint while using O3CPU in > Full > System mode > Hi all, > I'm currently using X86 Full system mode. > Firstly, I tried to make a checkpoint while running SPEC CPU by > AtomicSimpleCPU, > and I got it. After that, I did restoring checkpoint by adding an option > '--cpu-type=DerivO3CPU', and also added the cache option. > However, if I run(restoring) by O3CPU, the simulation didn't keep running, it > just hanged and nothing changed. I also added some 'printf()' at > 'src/cpu/o3/cpu.cc', 'FullO3CPU::instDone()' to check the count of > instruction, nothing changed. > I'm also tried just restoring to Atomic, not O3, but in this case, the > simulation works fine. I'm not sure why this is hanging when I restore O3. > Below is the command line that I used for restoring O3. > /home/workspace/gem5_fs/build/X86/gem5.opt > /home/workspace/gem5_fs/configs/example/fs.py -n 1 > --disk-image=/home/workspace/fs_image/disks/ubuntu-16.04-v3.6.img > --kernel=/home/taeklim/workspace/fs_image/binaries/vmlinux-4.14.53-prof > --sys-clock=1GHz --cpu-clock=4GHz --mem-size=4096MB --mem-type=DDR3_1600_8x8 > --restore-with-cpu=DerivO3CPU --cpu-type=DerivO3CPU --caches > --checkpoint-dir=/home/workspace/gem5_fs/m5out/ --at-instruction -r > 977530554357000 > Your help will be appreciated. > Best, > Taeklim > ᐧ > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Microcode_ROM page fault not handled
Hello, I find it relevant to inform also, that this problem has been encountered with a fresh pull of gem5 commit: 2045a5c199c7c7597684c5d7501d5fb55aff9608 with no extra modifications. The same repo I used it to take the checkpoints uniformly for SPEC CPU 2017. The process I follow is that I use the "AtomicSimpleCPU" cpu-type to sequentially take the checkpoints. That is, a checkpoint is created at instruction "N" , then gem5 exits and then I restore the checkpoint N to continue the process and take the next checkpoint at instruction "N+period". Hence, this way each checkpoint is tested to be restored and normally work with AtomicSimpleCPU. Here is the gem5 command for taking the checkpoints : ./build/X86/gem5.opt --redirect-stdout --redirect-stderr --outdir=outdir /configs/example/fs.py --cpu-type=AtomicSimpleCPU -n 1 --mem-type=DDR4_2400_16x4 --mem-size=8GB --fastmem --sys-clock=4GHz --cpu-clock=4GHz --kernel=/path_to_kernel/vmlinux-4-15 --disk-image=/path_to_image/ubuntu-min-16-04.img --checkpoint-dir=/chpts_dir --checkpoint-restore=N --at-instruction --take-checkpoints=N+period --checkpoint-at-end The same process I have done it both for ARM and for x86 using fs.py . However, this stack-related problem does not show up for ARM but it does in many of the checkpoints taken for the different benchmarks. I can only see the problem maybe in the way that I created the equivalent Ubuntu image for x86 ( just following Jason's tutorial http://www.lowepower.com/jason/setting-up-gem5-full-system.html ) or there could be a problem with the way a checkpoint saves the current state when it is taken for x86. How is the stack saved and restored between the checkpoints (and I assume it is used/simulated when restoring with AtomicSimpleCPU)? I mention here again the gem5 command I use to restore the checkpoints with DerivO3CPU : ./build/X86/gem5.opt -r -e -d /path_to_outdir configs/example/fs.py --cpu-type= DerivO3CPU -n 1 --caches --l2cache --l3cache --mem-type=DDR4_2400_16x4 --mem-size=8GB --sys-clock=4GHz --cpu-clock=4GHz --maxinsts=15000 --kernel=/path_to_kernel/vmlinux-4-15 --disk-image=/path_to_image/ubuntu-min-16-04.img --checkpoint-dir=/path_to_cpt_dir/ -r N --at-instruction As everything has been done with the official gem5 code, even if it is a problem of my configuration(image, kernel) or of the SPEC benchmarks, I think there should had been a way to detect and stop/exit gem5 when a page fault goes into an infinite loop. I would appreciate any feedback regarding this point. -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France > From: "Kleovoulos Kalaitzidis" > To: "gem5 users mailing list" > Sent: Tuesday, November 13, 2018 2:31:30 AM > Subject: Re: [gem5-users] Microcode_ROM page fault not handled > Hello, > thank you a lot for your answer Gabe. I see what you mean that the stack seems > to be bad and I was trying to investigate why. > In order to have a quick try (and affected by the kernel-related problem of > this > thread I had mentioned : > https://www.mail-archive.com/gem5-users@gem5.org/msg13058.html ) > I built another kernel version, the 4.8.13 and I restored my checkpoints with > that one. You can find a part of the output attached here. I see again that > the > Microcode_ROM > keeps repeating for a page fault at the same address as before : > 0xfe001fd0. Though this time it seems to be more specific to me, since > it is related > with the kernel function "wake_up_new_task" which I found to be called at the > "do_fork" one. I can not really understand why stack does not play well with > some of the benchmarks, since I use the same way to take my checkpoints and > then restore them respectively. If this different output in comparison with > the > previous one can give an idea to someone please let me know. Thank you a lot > for your help. > -- > Kleovoulos Kalaitzidis > Doctorant - Équipe PACAP > Centre de recherche INRIA Rennes - Bretagne Atlantique > Bâtiment 12E, Bureau E321, Campus de Beaulieu, > 35042 Rennes Cedex, France >> From: "Gabe Black" >> To: "gem5 users mailing list" >> Sent: Monday, November 12, 2018 10:48:19 PM >> Subject: Re: [gem5-users] Microcode_ROM page fault not handled >> The microcode that's executing is in src/arch/x86/isa/insts/romutil.py I >> think, >> and it looks like your stack is bad. That's where the vectoring microcode >> checks to see that it will be able to write out the interrupt stack frame, >> and >> it apparently can't. That triggers another page fault, and it has the same >> problem. You'
Re: [gem5-users] Microcode_ROM page fault not handled
Hello, thank you a lot for your answer Gabe. I see what you mean that the stack seems to be bad and I was trying to investigate why. In order to have a quick try (and affected by the kernel-related problem of this thread I had mentioned : https://www.mail-archive.com/gem5-users@gem5.org/msg13058.html ) I built another kernel version, the 4.8.13 and I restored my checkpoints with that one. You can find a part of the output attached here. I see again that the Microcode_ROM keeps repeating for a page fault at the same address as before : 0xfe001fd0. Though this time it seems to be more specific to me, since it is related with the kernel function "wake_up_new_task" which I found to be called at the "do_fork" one. I can not really understand why stack does not play well with some of the benchmarks, since I use the same way to take my checkpoints and then restore them respectively. If this different output in comparison with the previous one can give an idea to someone please let me know. Thank you a lot for your help. -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France > From: "Gabe Black" > To: "gem5 users mailing list" > Sent: Monday, November 12, 2018 10:48:19 PM > Subject: Re: [gem5-users] Microcode_ROM page fault not handled > The microcode that's executing is in src/arch/x86/isa/insts/romutil.py I > think, > and it looks like your stack is bad. That's where the vectoring microcode > checks to see that it will be able to write out the interrupt stack frame, and > it apparently can't. That triggers another page fault, and it has the same > problem. You'll need to determine why your stack ends up out of whack, or why > that code might not be handling the stack in an exactly correct way which > makes > it fault when it shouldn't. > Gabe > On Mon, Nov 12, 2018 at 8:25 AM Kleovoulos Kalaitzidis < [ > mailto:kleovoulos.kalaitzi...@inria.fr | kleovoulos.kalaitzi...@inria.fr ] > > wrote: >> Hello, >> just to give more detail, I have attached here a part of the simout file >> before >> the first appearance of the page fault that after keeps >> executing. >> -- >> Kleovoulos Kalaitzidis >> Doctorant - Équipe PACAP >> Centre de recherche INRIA Rennes - Bretagne Atlantique >> Bâtiment 12E, Bureau E321, Campus de Beaulieu, >> 35042 Rennes Cedex, France >>> From: "Kleovoulos Kalaitzidis" < [ mailto:kleovoulos.kalaitzi...@inria.fr | >>> kleovoulos.kalaitzi...@inria.fr ] > >>> To: "gem5 users mailing list" < [ mailto:gem5-users@gem5.org | >>> gem5-users@gem5.org ] > >>> Sent: Monday, November 12, 2018 4:09:56 PM >>> Subject: [gem5-users] Microcode_ROM page fault not handled >>> Hello everyone, >>> I am currently using FS mode to simulate and execute SPEC benchmarks. The >>> image >>> I use is an Ubuntu-16.04 and the kernel I built for that is vmlinux-4-15. >>> To settle up the FS simulation environment, create the image file and build >>> the >>> kernel I have followed Jason's instructions from here: [ >>> http://www.lowepower.com/jason/setting-up-gem5-full-system.html | >>> http://www.lowepower.com/jason/setting-up-gem5-full-system.html ] >>> I run my simulations with x86 and I have already taken some checkpoints for >>> FS, >>> so now I use them to restore and execute the benchmarks. However, after some >>> testing >>> I found out that most of them after some time following the restore they >>> execute >>> infinite loops of micro ops without proceeding in the total benchmark >>> execution, because the number of executed instructions >>> would not change (after some printing within execution) >>> The gem5 command to restore first checkpoint is here : /build/X86/gem5.opt >>> --redirect-stdout --redirect-stderr --outdir=/outdir /configs/example/fs.py >>> --cpu-type=DerivO3CPU -n 1 --caches --l2cache --mem-type=DDR4_2400_16x4 >>> --mem-size=8GB --sys-clock=4GHz --cpu-clock=4GHz >>> --kernel=/path_to_kernel/vmlinux-4-15 >>> --disk-image=/path_to_image/ubuntu-min-16-04.img >>> --checkpoint-dir=/path_to_checkpoint_dir/ -r 1 >>> To tackle the problem I found the aforementioned recurring loop of micro >>> ops and >>> I saw that it keeps executing micro ops related with instruction >>> Microcode_ROM >>> After some search I found this older thread where someone else had a quite >>> similar problem : [ >>> https://www.ma
Re: [gem5-users] Microcode_ROM page fault not handled
Hello, just to give more detail, I have attached here a part of the simout file before the first appearance of the page fault that after keeps executing. -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France > From: "Kleovoulos Kalaitzidis" > To: "gem5 users mailing list" > Sent: Monday, November 12, 2018 4:09:56 PM > Subject: [gem5-users] Microcode_ROM page fault not handled > Hello everyone, > I am currently using FS mode to simulate and execute SPEC benchmarks. The > image > I use is an Ubuntu-16.04 and the kernel I built for that is vmlinux-4-15. > To settle up the FS simulation environment, create the image file and build > the > kernel I have followed Jason's instructions from here: > http://www.lowepower.com/jason/setting-up-gem5-full-system.html > I run my simulations with x86 and I have already taken some checkpoints for > FS, > so now I use them to restore and execute the benchmarks. However, after some > testing > I found out that most of them after some time following the restore they > execute > infinite loops of micro ops without proceeding in the total benchmark > execution, because the number of executed instructions > would not change (after some printing within execution) > The gem5 command to restore first checkpoint is here : /build/X86/gem5.opt > --redirect-stdout --redirect-stderr --outdir=/outdir /configs/example/fs.py > --cpu-type=DerivO3CPU -n 1 --caches --l2cache --mem-type=DDR4_2400_16x4 > --mem-size=8GB --sys-clock=4GHz --cpu-clock=4GHz > --kernel=/path_to_kernel/vmlinux-4-15 > --disk-image=/path_to_image/ubuntu-min-16-04.img > --checkpoint-dir=/path_to_checkpoint_dir/ -r 1 > To tackle the problem I found the aforementioned recurring loop of micro ops > and > I saw that it keeps executing micro ops related with instruction Microcode_ROM > After some search I found this older thread where someone else had a quite > similar problem : > https://www.mail-archive.com/gem5-users@gem5.org/msg13058.html > So I followed same pattern, I used the --debug-flags=Exec,LocalApic,Faults > and I > get this output : > 32985546164250: system.switch_cpus T0 : @__do_page_fault+716.32930 : > Microcode_ROM : ldst t0, HS:[t6] : MemRead : A=0xfe001fd0 > 32985546172500: system.switch_cpus T0 : @__do_page_fault+716.32890 : > Microcode_ROM : slli t4, t1, 0x4 : IntAlu : D=0x00e0 > 32985546172750: system.switch_cpus T0 : @__do_page_fault+716.32891 : > Microcode_ROM : ld t2, IDTR:[t4 + 0x8] : MemRead : D=0x > A=0xfee8 > 32985546173000: system.switch_cpus T0 : @__do_page_fault+716.32892 : > Microcode_ROM : ld t4, IDTR:[t4] : MemRead : D=0x81a08e1015d0 > A=0xfee0 > 32985546173250: system.switch_cpus T0 : @__do_page_fault+716.32893 : > Microcode_ROM : chks , t4b, 0x3 : IntAlu : > 32985546173500: system.switch_cpus T0 : @__do_page_fault+716.32894 : > Microcode_ROM : srli t10, t4, 0x10 : IntAlu : D=0x81a08e10 > 32985546173750: system.switch_cpus T0 : @__do_page_fault+716.32895 : > Microcode_ROM : andi t5, t10, 0xf8 : IntAlu : D=0x0010 > 32985546174000: system.switch_cpus T0 : @__do_page_fault+716.32896 : > Microcode_ROM : andi t0w, t10w, 0x4 : IntAlu : D=0x0020 > 32985546174250: system.switch_cpus T0 : @__do_page_fault+716.32897 : > Microcode_ROM : br 0x8084 : No_OpClass : > 32985546176500: system.switch_cpus T0 : @__do_page_fault+716.32900 : > Microcode_ROM : ld t3, TSG:[t5] : MemRead : D=0x00af9b00 > A=0xfe001010 > 32985546176750: system.switch_cpus T0 : @__do_page_fault+716.32901 : > Microcode_ROM : chks , t3, 0x7 : IntAlu : > 32985546177000: system.switch_cpus T0 : @__do_page_fault+716.32902 : > Microcode_ROM : wrdl %ctrl145, t3, t10 : IntAlu : D=0xabd0 > 32985546177250: system.switch_cpus T0 : @__do_page_fault+716.32903 : > Microcode_ROM : wrdh t9, t4, t2 : IntAlu : D=0x81a015d0 > 32985546177500: system.switch_cpus T0 : @__do_page_fault+716.32904 : > Microcode_ROM : rdsel t11b, t11b, %ctrl128 : IntAlu : D=0x > 32985546177750: system.switch_cpus T0 : @__do_page_fault+716.32905 : > Microcode_ROM : rdattr t10, %ctrl184, : IntAlu : D=0xabd0 > 32985546178000: system.switch_cpus T0 : @__do_page_fault+716.32906 : > Microcode_ROM : andi t10, t10, 0x3 : IntAlu : D=0x > 32985546178250: system.switch_cpus T0 : @__do_page_fault+716.32907 : > Microcode_ROM : rdattr t5, %ctrl179, : IntAlu : D=0xabd0 > 32985546178500: system.switch_cpus T0 : @__do_page_fault+716.32908 : > Microcode_ROM : andi t5, t5, 0x3 : IntAlu : D=0x > 3298
[gem5-users] Microcode_ROM page fault not handled
+716.32915 : Microcode_ROM : br 0x8098 : No_OpClass : 32985546217500: system.switch_cpus T0 : @__do_page_fault+716.32916 : Microcode_ROM : mov t6, t6, rsp : IntAlu : D=0xfe002000 32985546217750: system.switch_cpus T0 : @__do_page_fault+716.32917 : Microcode_ROM : br 0x8099 : No_OpClass : 32985546219750: system.switch_cpus T0 : @__do_page_fault+716.32921 : Microcode_ROM : andi t6b, t6b, 0xf0 : IntAlu : D=0xfe002000 3298554622: system.switch_cpus T0 : @__do_page_fault+716.32922 : Microcode_ROM : subi t6, t6, 0x30 : IntAlu : D=0xfe001fd0 32985546220250: system.switch_cpus T0 : @__do_page_fault+716.32923 : Microcode_ROM : wrip , t0, t9 : IntAlu : 3298554650: system.switch_cpus T0 : @__do_page_fault+716.32924 : Microcode_ROM : srli t5, t4, 0x10 : IntAlu : D=0x81a08e10 32985546222500: system.switch_cpus T0 : @__do_page_fault+716.32925 : Microcode_ROM : andi t5, t5, 0xff : IntAlu : D=0x0010 32985546222750: system.switch_cpus T0 : @__do_page_fault+716.32926 : Microcode_ROM : wrdl %ctrl140, t3, t5 : IntAlu : D=0xabd0 32985546226500: system.switch_cpus T0 : @__do_page_fault+716.32927 : Microcode_ROM : limm t10, 0 : IntAlu : D=0x 32985546226750: system.switch_cpus T0 : @__do_page_fault+716.32928 : Microcode_ROM : rdsel t10w, t10w, %ctrl127 : IntAlu : D=0x0010 32985546227000: system.switch_cpus T0 : @__do_page_fault+716.32929 : Microcode_ROM : wrsel %ctrl127, t5w, : IntAlu : D=0x0010 32985546231500: Page-Fault: RIP 0x81057b6c: vector 14: #PF(0x3) at 0xfe001fd0 This page fault keeps happening all over again and the execution never continues. For some benchmarks it happens not far after restoring the checkpoint, for others it happens later and for some others it may even never appear. I have to also mention that the checkpoint which I restore is taken in a reasonable time after the benchmark execution start (around 2% of committed instructions) using AtomicSimpleCPU. Then I restore with DerivO3CPU or another cpu type of mine, always derived from DerivO3CPU. I am sorry for the long email, I tried to be as descriptive and comprehensive as possible. I would really appreciate your help because my knowledge over gem5 can not really help me solve this. I am looking forward to hearing from anyone having any idea... Thank you a lot in advance. -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Device Tree Blob(dtb) file to use with aarch64
Hello, I want to simulate gem5 full-system with armv8 and to do that I have downloaded the latest ARM full-system (aarch-system-20180409). Since I am heading for armv8, I got to use the image for aarch64-ubuntu and then the kernel vmlinux.vexpress_emm64 together wth binary boot_emm.arm64. What I am not sure is which dtb file I should combine with them in order to have a correct system simulation. For machine-type VExpress_EMM64 the FSConfig.py file has as default the "vexpress.aarch64.20140821.dtb" so I thought I will find the equivalent in the folder of 2018. I do not see something matching exactly and I did not find a lot of documentation so I would be grateful if somebody can help. Thank you in advace, Kind regards -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] How to associate a kernel offset to a linux image for full system simulation?
Hello, this is an older thread and the beginning of my effort to set up FS simulation for running SPEC benchmarks on x86 gem5. To do that, I totally followed the instructions given by Jason in his site : http://www.lowepower.com/jason/setting-up-gem5-full-system.html and I created an image of ubuntu-16.04 and the kernel version 4.8.13(using the config file provided by Jason). I also installed in the image the needed gem5-guest-tools. I can normally boot my image with qemu so then I went through to check that gem5 is also booting, before I use any .rcS files. I run the gem5 cmd: ./build/X86gem5.opt ./configs/example/fs.py --kernel=path_to_kernel --disk-image=path_to_ubuntu_image --cpu-type=AtomicSimpleCPU -n 1 --mem-size=2GB -fastmem --sys-clock=4GHz --cpu-clock=4GHz and then I do the telnet connection in another shell : telnet 127.0.0.1 3456 The connection is normally attached and the boot process starts. In around 10 min the file system is mounted and also the message "Welcome to Ubuntu.16.04" appears. Though, the boot process is not done yet and it keeps going for a lot of time. After around 5 hours it prints the message : Started gem5 init script. Starting Set console scheme... And then "Connection closed by foreign host" because on the part of the shell that gem5 cmd was executed, the command was killed. Except from the part that at the end the image did not boot, it even got 5 hours to reach this point. On my web search, it is mentioned that the boot up process normally would take 30 min. Can somebody help me on what I miss here please? Taking so long to boot (and not booting also after all) does not seem to be normal. Has anybody built a linux image and a kernel that they play along together and work normally with gem5. I would be grateful if somebody could give me his advice. Thank you very much in advance, -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France > From: "Kleovoulos Kalaitzidis" > To: "gem5 users mailing list" > Sent: Tuesday, July 31, 2018 4:18:07 PM > Subject: Re: [gem5-users] How to associate a kernel offset to a linux image > for > full system simulation? > Hello, > thank you for your reply. Sorry for not mentioning the gem5 command, I > thought I > could omit it since > it is the basic/default. So, the command line is : > build/X86/build.opt configs/example/fs.py --kernel=/path_to_kernel > --disk-image==/path_to_image > In the fs.py file the command line option for kernel was already set to : > root=/dev/hda1 by default, > and you were right I changed that to the existing partition. But I am still > facing a segfault . > Hence, I will try to tackle it in another angle and if i find something > specific > and useful I will reply again. > Thanks again. > -- > Kleovoulos Kalaitzidis > Doctorant - Équipe PACAP > Centre de recherche INRIA Rennes - Bretagne Atlantique > Bâtiment 12E, Bureau E321, Campus de Beaulieu, > 35042 Rennes Cedex, France >> From: "Ciro Santilli" >> To: "gem5 users mailing list" >> Sent: Monday, July 30, 2018 5:31:26 PM >> Subject: Re: [gem5-users] How to associate a kernel offset to a linux image >> for >> full system simulation? >> Did you try to set the kernel command line option as the kernel suggested? >> root=/dev/hda2 >> root=/dev/sda2 >> Picking 2 as it is the larger partition. >> I recommend always giving the full gem5 command line when posting here. >> On Mon, Jul 30, 2018 at 4:00 PM, Kleovoulos Kalaitzidis < [ >> mailto:kleovoulos.kalaitzi...@inria.fr | kleovoulos.kalaitzi...@inria.fr ] > >> wrote: >>> I am trying to setup Gem5 for full system simulation on x86. Following >>> Jason's >>> tutorial, I have generated the image file for ubuntu 18.04. >>> Then for the kernel I did the following steps (with Jason's config): >>> make oldconfig >>> make vmlinux >>> This creates an executable called vmlinux which I use as the kernel for >>> fs.py. >>> After trying to run it and creating the telnet session, I get the following >>> errors (extracted the end of the messages): >>> Using kernel 4.8.13: >>> List of all partitions: >>> [ callto:0100%2016384 | 0100 16384 ] ram0 (driver?) >>> [ callto:0101%2016384 | 0101 16384 ] ram1 (driver?) >>> [ callto:0102%2016384 | 0102 16384 ] ram2 (driver?) >>> [ callto:0103%2016384 | 0103 16384 ] ram3 (driver?) >>> [ callto:0104%2016384 | 0104 16384 ] ram4 (driver?) >>> [ callto:0105%2016384 |
Re: [gem5-users] How to associate a kernel offset to a linux image for full system simulation?
Hello, thank you for your reply. Sorry for not mentioning the gem5 command, I thought I could omit it since it is the basic/default. So, the command line is : build/X86/build.opt configs/example/fs.py --kernel=/path_to_kernel --disk-image==/path_to_image In the fs.py file the command line option for kernel was already set to : root=/dev/hda1 by default, and you were right I changed that to the existing partition. But I am still facing a segfault . Hence, I will try to tackle it in another angle and if i find something specific and useful I will reply again. Thanks again. -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France From: "Ciro Santilli" To: "gem5 users mailing list" Sent: Monday, July 30, 2018 5:31:26 PM Subject: Re: [gem5-users] How to associate a kernel offset to a linux image for full system simulation? BQ_BEGIN Did you try to set the kernel command line option as the kernel suggested? root=/dev/hda2 root=/dev/sda2 Picking 2 as it is the larger partition. I recommend always giving the full gem5 command line when posting here. On Mon, Jul 30, 2018 at 4:00 PM, Kleovoulos Kalaitzidis < [ mailto:kleovoulos.kalaitzi...@inria.fr | kleovoulos.kalaitzi...@inria.fr ] > wrote: BQ_BEGIN I am trying to setup Gem5 for full system simulation on x86. Following Jason's tutorial, I have generated the image file for ubuntu 18.04. Then for the kernel I did the following steps (with Jason's config): make oldconfig make vmlinux This creates an executable called vmlinux which I use as the kernel for fs.py. After trying to run it and creating the telnet session, I get the following errors (extracted the end of the messages): Using kernel 4.8.13: List of all partitions: [ callto:0100%2016384 | 0100 16384 ] ram0 (driver?) [ callto:0101%2016384 | 0101 16384 ] ram1 (driver?) [ callto:0102%2016384 | 0102 16384 ] ram2 (driver?) [ callto:0103%2016384 | 0103 16384 ] ram3 (driver?) [ callto:0104%2016384 | 0104 16384 ] ram4 (driver?) [ callto:0105%2016384 | 0105 16384 ] ram5 (driver?) [ callto:0106%2016384 | 0106 16384 ] ram6 (driver?) [ callto:0107%2016384 | 0107 16384 ] ram7 (driver?) [ callto:0108%2016384 | 0108 16384 ] ram8 (driver?) [ callto:0109%2016384 | 0109 16384 ] ram9 (driver?) 010a 16384 ram10 (driver?) 010b 16384 ram11 (driver?) 010c 16384 ram12 (driver?) 010d 16384 ram13 (driver?) 010e 16384 ram14 (driver?) 010f 16384 ram15 (driver?) [ callto:0300%208192000 | 0300 8192000 ] hda driver: ide-gd [ callto:0301%201024 | 0301 1024 ] hda1 b3e8ba38-c801-461b-a765-d4ccb929b5df [ callto:0302%208188928 | 0302 8188928 ] hda2 b68ea151-df09-44cf-8b99-0875407a5b25 No filesystem could mount root, tried: ext3 ext4 ext2 fuseblk Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(3,1) CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.13 #1 Hardware name: , BIOS 06/08/2008 0001 811e0a97 88001e5bc000 816ea24b 810ae1b3 8810 88001ec57ec0 88001ec57e58 88001ec57eb0 88001ec57ec8 0012 Call Trace: [] ? dump_stack+0x5d/0x79 [] ? panic+0xd3/0x20b [] ? mount_block_root+0x2a4/0x2bb [] ? prepare_namespace+0x161/0x197 [] ? kernel_init_freeable+0x182/0x18b [] ? kernel_init+0x5/0xe6 [] ? ret_from_fork+0x1f/0x40 [] ? rest_init+0x69/0x69 Kernel Offset: disabled ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(3,1) Using Kernel 4.17.9: [ 0.413939] VFS: Cannot open root device "hda1" or unknown-block(0,0): error -6 [ 0.413951] Please append a correct "root=" boot option; here are the available partitions: [ 0.413966] [ callto:0800%208192000 | 0800 8192000 ] sda [ 0.413967] driver: sd [ 0.413982] [ callto:0801%201024 | 0801 1024 ] sda1 b3e8ba38-c801-461b-a765-d4ccb929b5df [ 0.413983] [ 0.414000] [ callto:0802%208188928 | 0802 8188928 ] sda2 b68ea151-df09-44cf-8b99-0875407a5b25 [ 0.414001] [ 0.414018] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0) The problem seems to be during the creation of the kernel, where I do not install any driver. Jason mentions that I should probably need to install some drivers/software, but they are not specified. >From what I've seen on the internet it is likely to be a filesystem driver >missing or an incompatibility of kernel and linux version. Would anyone be able to give directions on how to understand and solve this issue? -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E
[gem5-users] How to associate a kernel offset to a linux image for full system simulation?
I am trying to setup Gem5 for full system simulation on x86. Following Jason's tutorial, I have generated the image file for ubuntu 18.04. Then for the kernel I did the following steps (with Jason's config): make oldconfig make vmlinux This creates an executable called vmlinux which I use as the kernel for fs.py. After trying to run it and creating the telnet session, I get the following errors (extracted the end of the messages): Using kernel 4.8.13: List of all partitions: [ callto:0100 16384 | 0100 16384 ] ram0 (driver?) [ callto:0101 16384 | 0101 16384 ] ram1 (driver?) [ callto:0102 16384 | 0102 16384 ] ram2 (driver?) [ callto:0103 16384 | 0103 16384 ] ram3 (driver?) [ callto:0104 16384 | 0104 16384 ] ram4 (driver?) [ callto:0105 16384 | 0105 16384 ] ram5 (driver?) [ callto:0106 16384 | 0106 16384 ] ram6 (driver?) [ callto:0107 16384 | 0107 16384 ] ram7 (driver?) [ callto:0108 16384 | 0108 16384 ] ram8 (driver?) [ callto:0109 16384 | 0109 16384 ] ram9 (driver?) 010a 16384 ram10 (driver?) 010b 16384 ram11 (driver?) 010c 16384 ram12 (driver?) 010d 16384 ram13 (driver?) 010e 16384 ram14 (driver?) 010f 16384 ram15 (driver?) [ callto:0300 8192000 | 0300 8192000 ] hda driver: ide-gd [ callto:0301 1024 | 0301 1024 ] hda1 b3e8ba38-c801-461b-a765-d4ccb929b5df [ callto:0302 8188928 | 0302 8188928 ] hda2 b68ea151-df09-44cf-8b99-0875407a5b25 No filesystem could mount root, tried: ext3 ext4 ext2 fuseblk Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(3,1) CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.13 #1 Hardware name: , BIOS 06/08/2008 0001 811e0a97 88001e5bc000 816ea24b 810ae1b3 8810 88001ec57ec0 88001ec57e58 88001ec57eb0 88001ec57ec8 0012 Call Trace: [] ? dump_stack+0x5d/0x79 [] ? panic+0xd3/0x20b [] ? mount_block_root+0x2a4/0x2bb [] ? prepare_namespace+0x161/0x197 [] ? kernel_init_freeable+0x182/0x18b [] ? kernel_init+0x5/0xe6 [] ? ret_from_fork+0x1f/0x40 [] ? rest_init+0x69/0x69 Kernel Offset: disabled ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(3,1) Using Kernel 4.17.9: [ 0.413939] VFS: Cannot open root device "hda1" or unknown-block(0,0): error -6 [ 0.413951] Please append a correct "root=" boot option; here are the available partitions: [ 0.413966] [ callto:0800 8192000 | 0800 8192000 ] sda [ 0.413967] driver: sd [ 0.413982] [ callto:0801 1024 | 0801 1024 ] sda1 b3e8ba38-c801-461b-a765-d4ccb929b5df [ 0.413983] [ 0.414000] [ callto:0802 8188928 | 0802 8188928 ] sda2 b68ea151-df09-44cf-8b99-0875407a5b25 [ 0.414001] [ 0.414018] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0) The problem seems to be during the creation of the kernel, where I do not install any driver. Jason mentions that I should probably need to install some drivers/software, but they are not specified. >From what I've seen on the internet it is likely to be a filesystem driver >missing or an incompatibility of kernel and linux version. Would anyone be able to give directions on how to understand and solve this issue? -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Adding a new resource
Hello, if I clearly understood your question you can do that in the SConscript file in the o3 folder. For any new structure you want to add create the equivalent files .hh/.cc (and maybe _impl.hh) and make this structure compile by including a corespondent line in the SConscript file. And then normally use it within the other structures in the pipeline. Hope it helps. -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France - Original Message - > From: "Pawan Joshi" <pawanjoshi...@gmail.com> > To: gem5-users@gem5.org > Sent: Friday, March 16, 2018 6:54:33 PM > Subject: [gem5-users] Adding a new resource > Hello all > I am working on adding a new value predictor structure in the O3 CPU, but > cannot seem to find the 'resources' directory where I have to code in my > model. Where will this directory be - src/cpu/o3 doesn't have it. > Thanks > Pawan > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Is it a way to change the behavior of "load" and "store"?
Hello, if you want to do that for a typical detailed simulation, then I suggest that you change the way a load/store is scheduled for execution in the pipeline, and not the actual ISA. However, this requires a lot of synchronisation since in the timing simulation in gem5 loads and stores are actually requests and responds between memory and the pipeline. In folder /src/arch/arm/isa/insts/ and in files ldr64.isa/str64.isa you can check the decoded loads and stores and then search for their actual way of execution in the generated files (/build/ARM/arch/arm/generated/exec-ns.cc.inc). There you can find all decoded instructions and their implementation. Though these apply for a detailed/timing simulation, I am not sure if it helps. Good luck! -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France - Original Message - > From: "IL Ne" <nedni...@gmail.com> > To: m5-us...@m5sim.org > Sent: Sunday, February 25, 2018 10:05:43 AM > Subject: [gem5-users] Is it a way to change the behavior of "load" and > "store"? > Hi, > I know that dealing with memory instruction is complicated, which involves > things like iew, lsq. In my work, I want to make the memory access process > to be accomplished instantaniously, meanwhile functional simulation should > still be right. > For example, Macroop ADD contains microops like ld and st, which will takes > several cycles. Simply delete it will get error infomation while simulating. > Is it a way to make it happen without taking any time? > Wei Wang > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] How to define which source Reg is the one stored in memory? (for ARM AArch64)
Hello, I am simulating an OoO architecture using AArch64 and FS timing mode. I need to clarify which register index represents the register that is stored to the memory, when a store instruction is executed. Is there any way to be aware of which source register (index) is the one that represents the register to be stored? While trying to clarify that I investigated the following: In file /src/arch/arm/isa/insts/str64.isa one can find all possible store instructions, and then find their decoded form in /src/arch/arm/isa/formats/aarch64.isa by searching their name (for instance "STRW64"). Also, in the generated files one can see in detail the implementation of the instructions (/build/ARM/arch/arm/generated/exec-ns.cc.inc). A typical store instruction calls the "writeMemTiming", with argument "Mem". This function is implemented in the file src/arch/generic/memhelpers.hh, where w e see that "mem" represents the actual data that will be stored in the "addr" space. Moreover, again in the generated file, we see that in typical stores, a "XDest" variable is defined and reads the data from the source register index 1, and then it is assigned to the aforementioned variable "Mem" that will be transfered to the memory. However, in floating point this is not the case, because misc registers are involved, and the stored data are read from a different index than 1. And also, in cases of store pairs (sdp) two different registers are stored to a double address space, but this could be adapted if there would be a norm for the others. So, from the above I try to extract a formula that could define which source register is the one to be stored. I would be grateful if someone knows something better to share it with me. Thank you very much in advance and sorry for the long-complicated mail. -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Datatype (data-width) of NEON operations for ARM in Gem5
Hello,
I could suggest a way that I have been using for checking access width of load
instructions but I am not sure it could fit for Neon instructions.
So, normally the produced/built file in the generated folder "exec-ns.cc.inc"
contains all the information in detail for any instruction. But you have to
find the macro-representation of the instruction by the decoder files in the
../src/arch/arm/isa and match the instruction name with the macro presented in
the generated file. And following the decoder you can find out how the
instruction is decoded depending on the bit representation, and you can use the
same pattern of the decoder
to identify an instruction beyond strcompare. So, for a given instruction you
can find its macro in the decoder, grep it in the generated files to see its
actual implementation and
sizes etc.
I hope it helps.
--
Kleovoulos Kalaitzidis
Doctorant - Équipe PACAP
Centre de recherche INRIA Rennes - Bretagne Atlantique
Bâtiment 12E, Bureau E321, Campus de Beaulieu,
35042 Rennes Cedex, France
- Original Message -
> From: "Gokul Subramanian Ravi" <gr...@wisc.edu>
> To: gem5-users@gem5.org
> Sent: Friday, June 9, 2017 9:17:35 PM
> Subject: [gem5-users] Datatype (data-width) of NEON operations for ARM in
> Gem5
> Hello all,
> I'm trying to optimize execution for ARM NEON instructions via Gem5 and for
> that I need to be able to identify the data-width of the executing NEON
> operations.
> From the ARM site, the instructions are as follows:
> VADD{cond}.datatype {Qd}, Qn, Qm > where datatype is I8, I16, I32, or
> I64.
> I'm identifying different instructions by performing "
> inst->staticInst->disassemble(..)" and then I do some string comparisons to
> figure out instructions I'm interested in. But for NEON instructions, the
> disassemble() doesn't tell me the "datatype".
> Can someone provide pointers as to how I can identify the datatype? I'm
> guessing I can get something from src/arch/arm/* but not sure what I should
> be looking at. Thank you!
> Best,
> Gokul Subramanian Ravi ,
> Graduate Student,
> ECE Dept.,
> University of Wisconsin-Madison
> ___
> gem5-users mailing list
> gem5-users@gem5.org
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Re: [gem5-users] Fetch buffer and Instruction queue
Hello, the fetchBufferSize as it is mentioned in the code, it can be actually even smaller than a cache line. It holds the fetched instructions and it should be equal or bigger than the product fetchWidth*instSize. The fetched instructions are placed in this queue and by the end of the stage are placed to the timeBuffer to decode stage. Then the decoded ones follow rename by the equivalent timeBuffer again until reaching the IEW stage. And there, according to my understanding, in the "dispatchInsts" the instructions coming from rename are issued and placed in the unified scheduler-IQ/LSQ, from where they are actually executed. Hope it helps. -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France - Original Message - > From: "Ayman Moussa" <ayman.mouss...@imperial.ac.uk> > To: "gem5 users mailing list" <gem5-users@gem5.org> > Sent: Tuesday, May 30, 2017 7:50:54 PM > Subject: Re: [gem5-users] Fetch buffer and Instruction queue > I have evaluated the source code and found that fetchBufferSize is just a > buffer for cache lines it seems. But I am confused; > Where do decoded instructions go to? If the Instruction Queue is the unified > scheduler, where are the the instructions issued from? > Help much appreciated > Thanks > From: gem5-users <gem5-users-boun...@gem5.org> on behalf of Moussa, Ayman > <ayman.mouss...@imperial.ac.uk> > Sent: 30 May 2017 17:23:46 > To: gem5 users mailing list > Subject: [gem5-users] Fetch buffer and Instruction queue > Hi > I have a few simple questions about the parameters in the O3 CPU model. > I have read http://gem5.org/O3CPU and I am unsure if the Instruction Queue > the same as the unified scheduler/reservation station? If so, does > "fetchBufferSize" represent the maxmimum number of instructions in the fetch > buffer? > O3CPU - gem5 > gem5.org > The O3CPU is our new detailed model for the v2.0 release. It is an out of > order CPU model loosely based on the Alpha 21264. This page will give you a > general overview ... > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Default functional units
Hello, and you are welcome. I would suggest that you change the number of "count" to the needed one and add only potentially new categories of FU in the FUList. IprPort () has to do with IprAccess and a search within the code shows that it has to do with prefetching instructions. That's what I know. -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France - Original Message - > From: "Ayman Moussa" <ayman.mouss...@imperial.ac.uk> > To: "gem5 users mailing list" <gem5-users@gem5.org> > Sent: Monday, May 29, 2017 2:09:19 PM > Subject: Re: [gem5-users] Default functional units > Hi > Thank you for your reply. I had assumed that only 1 of each functional unit > was being created so I added two more IntALU() and FP_ALU() to the > DefaultFUPool(). I guess this doubled the amount of units right? Do you know > what the IprPort () unit does/stands for? I was unable to find any reference > to it online or anywhere else. > Thanks > From: gem5-users <gem5-users-boun...@gem5.org> on behalf of Kleovoulos > Kalaitzidis <kleovoulos.kalaitzi...@inria.fr> > Sent: 29 May 2017 09:00:34 > To: gem5 users mailing list > Subject: Re: [gem5-users] Default functional units > Hello, > the "count" value corresponds to the number of instances of the equivalent > unit, just as you understood. > It does not "override" something, but defines the number of the specific FU > that will be created and > pushed in the fuPool. I suggest you to have a look in the file "fu_pool.cc" > in the main constructor > and it will become clear to you. > Kind regards, > -- > Kleovoulos Kalaitzidis > Doctorant - Équipe PACAP > Centre de recherche INRIA Rennes - Bretagne Atlantique > Bâtiment 12E, Bureau E321, Campus de Beaulieu, > 35042 Rennes Cedex, France > - Original Message - > > From: "Ayman Moussa" <ayman.mouss...@imperial.ac.uk> > > > To: "gem5 users mailing list" <gem5-users@gem5.org> > > > Sent: Thursday, May 25, 2017 10:02:31 PM > > > Subject: [gem5-users] Default functional units > > > In src/cpu/o3/ FUPool.py , the DefaultFUPool() contains one of each > > functional unit: > > > class DefaultFUPool(FUPool): > > > FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), > > > SIMD_Unit(), WritePort(), RdWrPort(), IprPort() ] > > > However there is a "count" parameter in each class definition in > > > FuncUnitConfig.py that varies for each unit i.e > > > class IntALU(FUDesc): > > > opList = [ OpDesc(opClass='IntAlu') ] > > > count = 6 > > > class FP_ALU(FUDesc): > > > opList = [ OpDesc(opClass='FloatAdd', opLat=2), > > > OpDesc(opClass='FloatCmp', opLat=2), > > > OpDesc(opClass='FloatCvt', opLat=2) ] > > > count = 4 > > > etc > > > I'm confused by what this means. In the default pool, do we only have 1 of > > each functional unit or does the parameter "count" override the number of > > units for that class i.e count=6 means there will be 6 Integer ALUs?? I > > have > > looked at config.ini but I cannot tell how many functional units there are. > > > I'm writing this for my thesis and I would really appreciate if someone > > could > > clear this up for me. > > > Thanks > > > Ayman > > > ___ > > > gem5-users mailing list > > > gem5-users@gem5.org > > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Default functional units
Hello, the "count" value corresponds to the number of instances of the equivalent unit, just as you understood. It does not "override" something, but defines the number of the specific FU that will be created and pushed in the fuPool. I suggest you to have a look in the file "fu_pool.cc" in the main constructor and it will become clear to you. Kind regards, -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France - Original Message - > From: "Ayman Moussa" <ayman.mouss...@imperial.ac.uk> > To: "gem5 users mailing list" <gem5-users@gem5.org> > Sent: Thursday, May 25, 2017 10:02:31 PM > Subject: [gem5-users] Default functional units > In src/cpu/o3/ FUPool.py , the DefaultFUPool() contains one of each > functional unit: > class DefaultFUPool(FUPool): > FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), > SIMD_Unit(), WritePort(), RdWrPort(), IprPort() ] > However there is a "count" parameter in each class definition in > FuncUnitConfig.py that varies for each unit i.e > class IntALU(FUDesc): > opList = [ OpDesc(opClass='IntAlu') ] > count = 6 > class FP_ALU(FUDesc): > opList = [ OpDesc(opClass='FloatAdd', opLat=2), > OpDesc(opClass='FloatCmp', opLat=2), > OpDesc(opClass='FloatCvt', opLat=2) ] > count = 4 > etc > I'm confused by what this means. In the default pool, do we only have 1 of > each functional unit or does the parameter "count" override the number of > units for that class i.e count=6 means there will be 6 Integer ALUs?? I have > looked at config.ini but I cannot tell how many functional units there are. > I'm writing this for my thesis and I would really appreciate if someone could > clear this up for me. > Thanks > Ayman > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
