Re: [gem5-users] simObject clocks and global simulation clock
Ticks is the basic unit of time in gem5. gem5 uses this for synchronization. Every system cycle is made up of n number of ticks ticks. For a system unit with frequency = 2 GHZ, one cycle = 500 ticks On Tue, Dec 16, 2014 at 7:04 PM, Anny via gem5-users wrote: > > Hi all, > > I have a question about clocks on gem5. In gem5, it seems that there is a > global simulation clock and every simObject has a clock domain. The eventq > is sorted in time. When two objects with two different clocks schedule two > events on eventq, how the order is determined since the two objects have > different clocks? Are all objects synchronious? it seems that everything in > the system is based of one clock (global simulation clock)? It is binding. > > > Best, > Anny. > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Waking up instructions dependent on load
Hi I am working with ARM SE mode. Suppose we have: ldr r4,[r2,#8] add r1 r4,r1 It looks to me that the dependent add instruction is woken up only after load instruction is written back to memory. Also write back of load instruction happens after commit. I would like to know if this is correct. Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Re-Executing LAS Conflicts
Hi Andreas and Arthur It would be really helpful if you can provide some hints. Thanks! On Mon, Dec 1, 2014 at 10:56 PM, Vanchinathan Venkataramani < dcsv...@gmail.com> wrote: > Hi Arthur > > Thanks a lot for your reply. > > Your interpretation of LAS is what I require. > > I want to replay execution starting from the Load. It will be really > helpful if you can give me hints on how to replay execution from this load > instruction. > > Thanks > > On Mon, Dec 1, 2014 at 10:54 PM, Vanchinathan Venkataramani < > dcsv...@nus.edu.sg> wrote: > >> Hi Arthur >> >> Thanks a lot for your reply. >> >> Your interpretation of LAS is what I require. >> >> I want to replay execution starting from the Load. It will be really >> helpful if you can give me hints on how to replay execution from this load >> instruction. >> >> Thanks >> >> >> On Mon, Dec 1, 2014 at 10:01 PM, Arthur Perais >> wrote: >> >>> Okay, the next comments assume that you are talking about a load that >>> executed before an older store writing to the same address executed, and >>> therefore got the wrong value. If what you call LAS refers to something >>> else, disregard that. >>> >>> From what I gathered, the only replay mechanism currently implemented in >>> the o3 CPU is there to deal with partial matches with store-to-load >>> forwarding. >>> For instance, when a load needs data that is part written by a store, >>> and part in the dcache. In that case, the instruction is replayed when the >>> store writes to the dcache (the mechanism is actually coarser than that but >>> you get the idea). >>> >>> If you want selective replay for memory order violation (which is okay >>> but quite complex in my opinion), you need to implement it yourself. This >>> entails : >>> - Getting all the instructions you need to replay (through register >>> dependencies and memory dependencies). >>> - Restore their state (clear the Issued flag, clear the Executed flag, >>> and so on). >>> - Restore dependencies which is non trivial since wakeDependents in >>> inst_queue_impl.hh clears dependencies in dep_graph.hh when waking up >>> insts. This means that you need to retain dependencies even after >>> instructions have issued. You also need to deal with memory dependencies. >>> - How do you replay? From the IQ? if so, then you can't free the IQ >>> entry upon issue. If not, then you need a particular buffer to replay >>> instructions from. >>> >>> If you want non-selective replay, this should be easier, although >>> dependencies still have to be restored and you have to deal with the >>> question of where the instructions are replayed from. >>> >>> Hope this helps, and if anyone sees a gross mistake in what I said, do >>> not hesitate. >>> >>> Le 01/12/2014 14:47, Vanchinathan Venkataramani via gem5-users a écrit : >>> >>> Hi Andreas >>> >>> In ARM O3CPU, when there is a load after store violation, the younger >>> instructions are being squashed and re-fetched again. >>> >>> Is it possible to re-execute these instructions instead of squashing >>> all the younger instructions? >>> >>> Thanks >>> >>> >>> >>> ___ >>> gem5-users mailing >>> listgem5-users@gem5.orghttp://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >>> >>> >>> -- >>> Arthur Perais >>> INRIA Bretagne Atlantique >>> Bâtiment 12E, Bureau E303, Campus de Beaulieu >>> 35042 Rennes, France >>> >>> >> > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Re-Executing LAS Conflicts
Hi Arthur Thanks a lot for your reply. Your interpretation of LAS is what I require. I want to replay execution starting from the Load. It will be really helpful if you can give me hints on how to replay execution from this load instruction. Thanks On Mon, Dec 1, 2014 at 10:54 PM, Vanchinathan Venkataramani < dcsv...@nus.edu.sg> wrote: > Hi Arthur > > Thanks a lot for your reply. > > Your interpretation of LAS is what I require. > > I want to replay execution starting from the Load. It will be really > helpful if you can give me hints on how to replay execution from this load > instruction. > > Thanks > > > On Mon, Dec 1, 2014 at 10:01 PM, Arthur Perais > wrote: > >> Okay, the next comments assume that you are talking about a load that >> executed before an older store writing to the same address executed, and >> therefore got the wrong value. If what you call LAS refers to something >> else, disregard that. >> >> From what I gathered, the only replay mechanism currently implemented in >> the o3 CPU is there to deal with partial matches with store-to-load >> forwarding. >> For instance, when a load needs data that is part written by a store, and >> part in the dcache. In that case, the instruction is replayed when the >> store writes to the dcache (the mechanism is actually coarser than that but >> you get the idea). >> >> If you want selective replay for memory order violation (which is okay >> but quite complex in my opinion), you need to implement it yourself. This >> entails : >> - Getting all the instructions you need to replay (through register >> dependencies and memory dependencies). >> - Restore their state (clear the Issued flag, clear the Executed flag, >> and so on). >> - Restore dependencies which is non trivial since wakeDependents in >> inst_queue_impl.hh clears dependencies in dep_graph.hh when waking up >> insts. This means that you need to retain dependencies even after >> instructions have issued. You also need to deal with memory dependencies. >> - How do you replay? From the IQ? if so, then you can't free the IQ entry >> upon issue. If not, then you need a particular buffer to replay >> instructions from. >> >> If you want non-selective replay, this should be easier, although >> dependencies still have to be restored and you have to deal with the >> question of where the instructions are replayed from. >> >> Hope this helps, and if anyone sees a gross mistake in what I said, do >> not hesitate. >> >> Le 01/12/2014 14:47, Vanchinathan Venkataramani via gem5-users a écrit : >> >> Hi Andreas >> >> In ARM O3CPU, when there is a load after store violation, the younger >> instructions are being squashed and re-fetched again. >> >> Is it possible to re-execute these instructions instead of squashing >> all the younger instructions? >> >> Thanks >> >> >> >> ___ >> gem5-users mailing >> listgem5-users@gem5.orghttp://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> >> >> -- >> Arthur Perais >> INRIA Bretagne Atlantique >> Bâtiment 12E, Bureau E303, Campus de Beaulieu >> 35042 Rennes, France >> >> > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Re-Executing LAS Conflicts
Hi Andreas In ARM O3CPU, when there is a load after store violation, the younger instructions are being squashed and re-fetched again. Is it possible to re-execute these instructions instead of squashing all the younger instructions? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Dumping stats every N cycles
I want to dump the counter statistics every N cycles into a file. I saw some old posts on using periodicStatDump. I tried calling periodicStatDump(N) in se.py. This makes the simulation halt and the stats is never updated. I would like to know if I'm doing something wrong. Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Computing CPI Stack
Hi all I would like to know how I can build up the CPI stack from gem5 statistics. Thanks in advance ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Heterogeneous system in FS mode
Hi all I'm trying to create a heterogeneous system with 1 2-way 2 4-way and 1 8-way core in arm-detailed FS mode. Following is the change I made in fs.py: cpus = [] for i in xrange(4): if(i == 0): cpus.append(2-way) elif (i == 1): cpus.append(4-way) elif (i == 2): cpus.append(4-way) elif (i == 3): cpus.append(4-way) test_sys.cpu = cpus However when I'm trying to create a check point, I'm getting the following error: "break event panic triggered" Is there something I'm missing? Thanks V Vanchinathan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Writing to float Register File
Hi all I'm trying to understand floating point register files. There are two functions responsible for reading and writing floating pointregisters. 1. setFloatReg 2. setFloatRegBits I'm not able to understand under what scenarios each of these functions are called. Thanks V Vanchinathan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Running Assembly code on ARM SE mode
Hi all Is it possible to write my own assembly code containing around 10-15 instructions and run it on gem5 without converting it into a binary with header and footer code? Thanks in advance. V Vanchinathan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] svc Instruction
At the end of svc instruction, R0 is being updated. On what case is R0 changed? Thanks V Vanchinathan On Thu, Aug 28, 2014 at 2:20 PM, Vanchinathan Venkataramani < dcsv...@nus.edu.sg> wrote: > At the end of svc instruction, R0 is being updated. On what case is R0 > changed? > > Thanks > V Vanchinathan > > > On Wed, Aug 27, 2014 at 5:23 PM, Vanchinathan Venkataramani < > dcsv...@gmail.com> wrote: > >> Hi all >> >> I would like to know how svc (trap) instruction is implemented in gem5. >> >> In particular I want to know on what condition the register values are >> changed when svc syscall is present. >> >> Thanks a lot! >> > > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] svc Instruction
Hi all I would like to know how svc (trap) instruction is implemented in gem5. In particular I want to know on what condition the register values are changed when svc syscall is present. Thanks a lot! ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Cross bars and buses in classic memory model
I would like to know if a bus that has header_cycles = 0 will behave similar to a cross-bar. Also, is it possible to replace the bus between L1 D and L2 D with a cross bar in classic memory model. Any help is really appreciated. Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Having multi-ported L1 Cache
Thanks a lot for your prompt reply. I'm currently having L1 shared between two cores. The dcache_port on each CPU is connected to a bus which is in turn connected to L1 D Cache. My understanding was that there can't be memory accesses from both the CPU's in the same cycle (even if it belonged to two different cache lines). However, if the L1 D cache has one dedicated port for each CPU, then the accesses can be parallelized. Thanks a lot! V Vanchinathan On Mon, Jul 21, 2014 at 8:38 PM, Andreas Hansson wrote: > Hi, > > It is not obvious what you are trying to achieve here. Could you shed > some more details on what you are after? Are you looking for more bandwidth > to the L1 (if is already infinite)? Are you looking to have more > outstanding transactions (it is already a parameter)? Are you looking to > share the L1 between to cores (if so use a bus/crossbar)? > > Andreas > > > From: Vanchinathan Venkataramani via gem5-users > Reply-To: Vanchinathan Venkataramani , gem5 users > mailing list > Date: Monday, 21 July 2014 12:16 > To: gem5 users mailing list > Subject: [gem5-users] Having multi-ported L1 Cache > > I would like to know if it is possible to connect the dcache_port of a > CPU to separate ports on L1 Cache in classic memory model. > > Currently L1 cache has a single cpu_side port. I wanted to know if the > functionality will be correct if I change this to a vector instead and > connect each of the CPU dcache_port to this. > > Thanks > V Vanchinathan > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Having multi-ported L1 Cache
I would like to know if it is possible to connect the dcache_port of a CPU to separate ports on L1 Cache in classic memory model. Currently L1 cache has a single cpu_side port. I wanted to know if the functionality will be correct if I change this to a vector instead and connect each of the CPU dcache_port to this. Thanks V Vanchinathan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Wrong decoding of instructions
I was able to figure out that wrong encoding of instructions was happening using the Exec trace, My thought was that changing the pipeline code of gem5, will not affect fetching of instructions. Hence, I was not sure on how I need to go about to find the bug. Thanks V Vanchinathan On Mon, Jul 21, 2014 at 12:44 AM, Ali Saidi wrote: > Why don’t you compare the un-modified trace (with —debug-flags=Exec) to > the modified one? > > Ali > > On Jul 20, 2014, at 11:06 AM, Vanchinathan Venkataramani via gem5-users < > gem5-users@gem5.org> wrote: > > > I'm trying to execute a binary on ARM gem5 O3CPU model. I made some > modification to the code. > > > > Now, some instructions wrongly get encoded as four micro-ops. I'm not > sure how I should go about for debugging this problem. > > > > Any help is really appreciated. > > > > Thanks a lot! > > ___ > > gem5-users mailing list > > gem5-users@gem5.org > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Wrong decoding of instructions
I'm trying to execute a binary on ARM gem5 O3CPU model. I made some modification to the code. Now, some instructions wrongly get encoded as four micro-ops. I'm not sure how I should go about for debugging this problem. Any help is really appreciated. Thanks a lot! ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Shared LSQ
Hi all I am trying to sharing the LSQ between all cores in O3CPU. After reading python and C++ files, I understand that LSQ is part of dcacheport and IEW stage of a CPU. Also lsq need to be associated with a CPU. Using the same lsq pointer doesn't work. Is there any other way to solve this problem? Any help is highly appreciated. Thanks a lot Thanks V Vanchinathan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Task migration of an application
I am trying to migrate a task from one CPU to another on ARM SE mode. I understand that a lot of attributes need to be copied from one CPU to another. Is there a check list of things that I need to copy? Thanks V Vanchinathan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Reading wrong data from Cache
Since 10 is the last value written to address A, it has to read 10 from address A. However it reads value 20 from Address A On Mon, May 5, 2014 at 11:56 AM, GE ZHIGUO via gem5-users < gem5-users@gem5.org> wrote: > What did you mean by no data written to address A? > > > > > > *From:* gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of > *Vanchinathan > Venkataramani via gem5-users > *Sent:* Sunday, May 04, 2014 12:06 AM > *To:* gem5 users mailing list > *Subject:* [gem5-users] Reading wrong data from Cache > > > > Hi all > > > > I'm looking into Exec flag trace on arm_detalied on se mode. > > > > Let A be a virtual address. > > *Instruction 1* *writes *value *10* to *address A* > > *Instruction 50* *reads *value *20* from * address A* > > > > However there is *no data written* to address A *between *Instruction *1 > and 50*. > > > > Why is this happening? > > > > Thanks > > V Vanchinathan > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Reading wrong data from Cache
Hi all I'm looking into Exec flag trace on arm_detalied on se mode. Let A be a virtual address. *Instruction 1* *writes *value *10* to *address A* *Instruction 50* *reads *value *20* from *address A* However there is *no data written* to address A *between *Instruction *1 and 50*. Why is this happening? Thanks V Vanchinathan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
